commit 2614a38ab2b21894ae5a8cf39b28eb4afd49ed01 parent 0fa724c2d30a98334cb33d093f20b38b8f04158f Author: Martin Kloeckner <mjkloeckner@gmail.com> Date: Thu, 16 Apr 2026 11:44:28 -0300 Update `/**` Diffstat:
50 files changed, 577 insertions(+), 2 deletions(-) diff --git a/vhdl/README.md b/vhdl/README.md @@ -1,5 +1,12 @@ # VHDL Examples -[Basic VHDL course](https://www.youtube.com/playlist?list=PLIbRYKjjYOPkhpxnkQ0fwTXnmgsiCMcVV) +> NOTE: All vhdl containing keyword `wait` is not synthesizable, its only +> purpose is to test the device. In that case the best practice is to separate +> the module containing the device itself from the module containing the test +> case. Thats why in the `dev` folder modules are located on the non `_tb` +> ending file, and the test case, containing the non synthesizable parts are +> located on files ending with `_tb`. + +## Resources used -> NOTE: All vhdl containing keyword `wait` is not synthesizable +[Basic VHDL course](https://www.youtube.com/playlist?list=PLIbRYKjjYOPkhpxnkQ0fwTXnmgsiCMcVV) diff --git a/vhdl/basics/case_when/Makefile b/vhdl/basics/case_when/Makefile @@ -0,0 +1,21 @@ +GHDL = ghdl +TOP = case_when_tb +SRCS = $(TOP).vhd +WAVEFORM_FILE = $(TOP).vcd + +all: run + +analyze: + $(GHDL) -a $(SRCS) + +elaborate: analyze + $(GHDL) -e $(TOP) + +run: elaborate + $(GHDL) -r $(TOP) --vcd=$(WAVEFORM_FILE) --stop-time=1ms + +clean: + rm -f *.o *.cf $(TOP) $(TOP).vcd + +view: all + nohup surfer $(WAVEFORM_FILE) >/dev/null 2>&1 & diff --git a/vhdl/basics/case_when/case_when_tb.vcd b/vhdl/basics/case_when/case_when_tb.vcd @@ -0,0 +1,73 @@ +$date + Thu Apr 16 11:18:55 2026 +$end +$version + GHDL v0 +$end +$timescale + 1 fs +$end +$scope module standard $end +$upscope $end +$scope module std_logic_1164 $end +$upscope $end +$scope module numeric_std $end +$upscope $end +$scope module case_when_tb $end +$var reg 8 ! sig_a[7:0] $end +$var reg 8 " sig_b[7:0] $end +$var reg 8 # sig_c[7:0] $end +$var reg 8 $ sig_d[7:0] $end +$var reg 2 % sig_sel[1:0] $end +$var reg 8 & sig_out_a[7:0] $end +$var reg 8 ' sig_out_b[7:0] $end +$upscope $end +$enddefinitions $end +#0 +b10101010 ! +b10111011 " +b11001100 # +b11011101 $ +b00 % +b10101010 & +b10101010 ' +#100000000000 +b01 % +b10111011 & +b10111011 ' +#200000000000 +b10 % +b11001100 & +b11001100 ' +#300000000000 +b11 % +b11011101 & +b11011101 ' +#400000000000 +b00 % +b10101010 & +b10101010 ' +#500000000000 +b01 % +b10111011 & +b10111011 ' +#600000000000 +b10 % +b11001100 & +b11001100 ' +#700000000000 +b11 % +b11011101 & +b11011101 ' +#800000000000 +b00 % +b10101010 & +b10101010 ' +#900000000000 +b01 % +b10111011 & +b10111011 ' +#1000000000000 +b10 % +b11001100 & +b11001100 ' diff --git a/vhdl/basics/case_when/case_when_tb.vhd b/vhdl/basics/case_when/case_when_tb.vhd @@ -0,0 +1,63 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity case_when_tb is +end entity; + +architecture case_when_arq of case_when_tb is + + signal sig_a : unsigned(7 downto 0) := x"AA"; + signal sig_b : unsigned(7 downto 0) := x"BB"; + signal sig_c : unsigned(7 downto 0) := x"CC"; + signal sig_d : unsigned(7 downto 0) := x"DD"; + + -- initialize `sig_sel` to 0xFF to start at 0x00 after first increment + signal sig_sel : unsigned(1 downto 0) := (others => '1'); + + signal sig_out_a : unsigned(7 downto 0); + signal sig_out_b : unsigned(7 downto 0); + + +begin + + process is + begin + sig_sel <= sig_sel + 1; + wait for 100 us; + end process; + + process(sig_sel, sig_a, sig_b, sig_c, sig_d) is + begin + + -- mux using if-elsif-else + if sig_sel = "00" then + sig_out_a <= sig_a; + elsif sig_sel = "01" then + sig_out_a <= sig_b; + elsif sig_sel = "10" then + sig_out_a <= sig_c; + elsif sig_sel = "11" then + sig_out_a <= sig_d; + else + sig_out_a <= (others => 'X'); + end if; + + case sig_sel is + when "00" => + sig_out_b <= sig_a; + when "01" => + sig_out_b <= sig_b; + when "10" => + sig_out_b <= sig_c; + when "11" => + sig_out_b <= sig_d; + when others => + sig_out_b <= (others => 'X'); + end case; + + + end process; + + +end architecture; diff --git a/vhdl/basics/case_when/work-obj93.cf b/vhdl/basics/case_when/work-obj93.cf @@ -0,0 +1,4 @@ +v 4 +file . "case_when_tb.vhd" "173733ea182b065cfd9d63636bf0f022fe61a923" "20260416141854.989": + entity case_when_tb at 1( 0) + 0 on 33; + architecture case_when_arq of case_when_tb at 8( 106) + 0 on 34; diff --git a/vhdl/clock/Makefile b/vhdl/basics/clock/Makefile diff --git a/vhdl/clock/clock_tb.vcd b/vhdl/basics/clock/clock_tb.vcd diff --git a/vhdl/clock/clock_tb.vhd b/vhdl/basics/clock/clock_tb.vhd diff --git a/vhdl/hello_world/Makefile b/vhdl/basics/hello_world/Makefile diff --git a/vhdl/hello_world/hello_world_tb.vcd b/vhdl/basics/hello_world/hello_world_tb.vcd diff --git a/vhdl/hello_world/hello_world_tb.vhd b/vhdl/basics/hello_world/hello_world_tb.vhd diff --git a/vhdl/hello_world/work-obj93.cf b/vhdl/basics/hello_world/work-obj93.cf diff --git a/vhdl/if_elsif_else/Makefile b/vhdl/basics/if_elsif_else/Makefile diff --git a/vhdl/if_elsif_else/if_elsif_else_tb.vcd b/vhdl/basics/if_elsif_else/if_elsif_else_tb.vcd diff --git a/vhdl/if_elsif_else/if_elsif_else_tb.vhd b/vhdl/basics/if_elsif_else/if_elsif_else_tb.vhd diff --git a/vhdl/if_elsif_else/work-obj93.cf b/vhdl/basics/if_elsif_else/work-obj93.cf diff --git a/vhdl/loop/Makefile b/vhdl/basics/loop/Makefile diff --git a/vhdl/loop/loop_tb.vcd b/vhdl/basics/loop/loop_tb.vcd diff --git a/vhdl/loop/loop_tb.vhd b/vhdl/basics/loop/loop_tb.vhd diff --git a/vhdl/loop/work-obj93.cf b/vhdl/basics/loop/work-obj93.cf diff --git a/vhdl/sensitivity_list/Makefile b/vhdl/basics/sensitivity_list/Makefile diff --git a/vhdl/sensitivity_list/sensitivity_list_tb.vcd b/vhdl/basics/sensitivity_list/sensitivity_list_tb.vcd diff --git a/vhdl/sensitivity_list/sensitivity_list_tb.vhd b/vhdl/basics/sensitivity_list/sensitivity_list_tb.vhd diff --git a/vhdl/sensitivity_list/work-obj93.cf b/vhdl/basics/sensitivity_list/work-obj93.cf diff --git a/vhdl/signal/Makefile b/vhdl/basics/signal/Makefile diff --git a/vhdl/signal/signal_tb.vcd b/vhdl/basics/signal/signal_tb.vcd diff --git a/vhdl/signal/signal_tb.vhd b/vhdl/basics/signal/signal_tb.vhd diff --git a/vhdl/signal/work-obj93.cf b/vhdl/basics/signal/work-obj93.cf diff --git a/vhdl/std_logic/Makefile b/vhdl/basics/std_logic/Makefile diff --git a/vhdl/std_logic/std_logic_tb.vhd b/vhdl/basics/std_logic/std_logic_tb.vhd diff --git a/vhdl/std_logic_vector/Makefile b/vhdl/basics/std_logic_vector/Makefile diff --git a/vhdl/std_logic_vector/std_logic_vector_tb.vhd b/vhdl/basics/std_logic_vector/std_logic_vector_tb.vhd diff --git a/vhdl/std_signed_unsigned/Makefile b/vhdl/basics/std_signed_unsigned/Makefile diff --git a/vhdl/std_signed_unsigned/std_signed_unsigned_tb.vhd b/vhdl/basics/std_signed_unsigned/std_signed_unsigned_tb.vhd diff --git a/vhdl/wait/Makefile b/vhdl/basics/wait/Makefile diff --git a/vhdl/wait/wait_tb.vhd b/vhdl/basics/wait/wait_tb.vhd diff --git a/vhdl/wait_for/Makefile b/vhdl/basics/wait_for/Makefile diff --git a/vhdl/wait_for/wait_for_tb.vcd b/vhdl/basics/wait_for/wait_for_tb.vcd diff --git a/vhdl/wait_for/wait_for_tb.vhd b/vhdl/basics/wait_for/wait_for_tb.vhd diff --git a/vhdl/wait_for/work-obj93.cf b/vhdl/basics/wait_for/work-obj93.cf diff --git a/vhdl/dev/mux/Makefile b/vhdl/dev/mux/Makefile @@ -0,0 +1,24 @@ +GHDL = ghdl +DEV_NAME = mux +TOP = $(DEV_NAME)_tb +TOP_SRC = $(TOP).vhd +SRCS = $(DEV_NAME).vhd +WAVEFORM_FILE = $(TOP).vcd + +all: run + +analyze: + $(GHDL) -a $(SRCS) + $(GHDL) -a $(TOP_SRC) + +elaborate: analyze + $(GHDL) -e $(TOP) + +run: elaborate + $(GHDL) -r $(TOP) --vcd=$(WAVEFORM_FILE) --stop-time=1ms + +clean: + rm -f *.o *.cf $(TOP) $(TOP).vcd + +view: all + nohup surfer $(WAVEFORM_FILE) >/dev/null 2>&1 & diff --git a/vhdl/dev/mux/mux.vhd b/vhdl/dev/mux/mux.vhd @@ -0,0 +1,40 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- expose signals outside of this module +entity mux is +port( + -- inputs + sig_a : in unsigned(7 downto 0); + sig_b : in unsigned(7 downto 0); + sig_c : in unsigned(7 downto 0); + sig_d : in unsigned(7 downto 0); + sig_sel : in unsigned(1 downto 0); + + -- outputs + sig_out : out unsigned(7 downto 0)); +end entity; + +architecture mux_arq of mux is +begin + + process(sig_sel, sig_a, sig_b, sig_c, sig_d) is + begin + + case sig_sel is + when "00" => + sig_out <= sig_a; + when "01" => + sig_out <= sig_b; + when "10" => + sig_out <= sig_c; + when "11" => + sig_out <= sig_d; + when others => + sig_out <= (others => 'X'); + end case; + + end process; + +end architecture; diff --git a/vhdl/dev/mux/mux_tb.vcd b/vhdl/dev/mux/mux_tb.vcd @@ -0,0 +1,95 @@ +$date + Thu Apr 16 11:22:17 2026 +$end +$version + GHDL v0 +$end +$timescale + 1 fs +$end +$scope module standard $end +$upscope $end +$scope module std_logic_1164 $end +$upscope $end +$scope module numeric_std $end +$upscope $end +$scope module mux_tb $end +$var reg 8 ! sig_a[7:0] $end +$var reg 8 " sig_b[7:0] $end +$var reg 8 # sig_c[7:0] $end +$var reg 8 $ sig_d[7:0] $end +$var reg 2 % sig_sel[1:0] $end +$var reg 8 & sig_out[7:0] $end +$scope module mux_a $end +$var reg 8 ' sig_a[7:0] $end +$var reg 8 ( sig_b[7:0] $end +$var reg 8 ) sig_c[7:0] $end +$var reg 8 * sig_d[7:0] $end +$var reg 2 + sig_sel[1:0] $end +$var reg 8 , sig_out[7:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +b10101010 ! +b10111011 " +b11001100 # +b11011101 $ +b00 % +b10101010 & +b10101010 ' +b10111011 ( +b11001100 ) +b11011101 * +b00 + +b10101010 , +#100000000000 +b01 % +b10111011 & +b01 + +b10111011 , +#200000000000 +b10 % +b11001100 & +b10 + +b11001100 , +#300000000000 +b11 % +b11011101 & +b11 + +b11011101 , +#400000000000 +b00 % +b10101010 & +b00 + +b10101010 , +#500000000000 +b01 % +b10111011 & +b01 + +b10111011 , +#600000000000 +b10 % +b11001100 & +b10 + +b11001100 , +#700000000000 +b11 % +b11011101 & +b11 + +b11011101 , +#800000000000 +b00 % +b10101010 & +b00 + +b10101010 , +#900000000000 +b01 % +b10111011 & +b01 + +b10111011 , +#1000000000000 +b10 % +b11001100 & +b10 + +b11001100 , diff --git a/vhdl/dev/mux/mux_tb.vhd b/vhdl/dev/mux/mux_tb.vhd @@ -0,0 +1,35 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mux_tb is +end entity; + +architecture mux_arq of mux_tb is + + signal sig_a : unsigned(7 downto 0) := x"AA"; + signal sig_b : unsigned(7 downto 0) := x"BB"; + signal sig_c : unsigned(7 downto 0) := x"CC"; + signal sig_d : unsigned(7 downto 0) := x"DD"; + + signal sig_sel : unsigned(1 downto 0) := (others => '1'); + signal sig_out : unsigned(7 downto 0); + +begin + + -- instance of `mux` module + mux_a : entity work.mux(mux_arq) port map( + sig_sel => sig_sel, + sig_a => sig_a, + sig_b => sig_b, + sig_c => sig_c, + sig_d => sig_d, + sig_out => sig_out); + + process is + begin + sig_sel <= sig_sel + 1; + wait for 100 us; + end process; + +end architecture; diff --git a/vhdl/dev/mux/work-obj93.cf b/vhdl/dev/mux/work-obj93.cf @@ -0,0 +1,7 @@ +v 4 +file . "mux_tb.vhd" "eebb9efbd8b02a9ed95aa841c833f5d34c742bd0" "20260416142217.585": + entity mux_tb at 1( 0) + 0 on 21; + architecture mux_arq of mux_tb at 8( 100) + 0 on 22; +file . "mux.vhd" "82e3845f949873605ca5cca3fb65e06798420f22" "20260416142217.582": + entity mux at 1( 0) + 0 on 19; + architecture mux_arq of mux at 19( 410) + 0 on 20; diff --git a/vhdl/dev/mux_generic/Makefile b/vhdl/dev/mux_generic/Makefile @@ -0,0 +1,24 @@ +GHDL = ghdl +DEV_NAME = mux_generic +TOP = $(DEV_NAME)_tb +TOP_SRC = $(TOP).vhd +SRCS = $(DEV_NAME).vhd +WAVEFORM_FILE = $(TOP).vcd + +all: run + +analyze: + $(GHDL) -a $(SRCS) + $(GHDL) -a $(TOP_SRC) + +elaborate: analyze + $(GHDL) -e $(TOP) + +run: elaborate + $(GHDL) -r $(TOP) --vcd=$(WAVEFORM_FILE) --stop-time=1ms + +clean: + rm -f *.o *.cf $(TOP) $(TOP).vcd + +view: all + nohup surfer $(WAVEFORM_FILE) >/dev/null 2>&1 & diff --git a/vhdl/dev/mux_generic/mux_generic.vhd b/vhdl/dev/mux_generic/mux_generic.vhd @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- expose signals outside of this module +entity mux_generic is +generic(mux_data_width : integer); +port( + -- inputs + sig_a : in unsigned(mux_data_width - 1 downto 0); + sig_b : in unsigned(mux_data_width - 1 downto 0); + sig_c : in unsigned(mux_data_width - 1 downto 0); + sig_d : in unsigned(mux_data_width - 1 downto 0); + sig_sel : in unsigned(1 downto 0); + + -- outputs + sig_out : out unsigned(mux_data_width - 1 downto 0)); +end entity; + +architecture mux_generic_arq of mux_generic is +begin + + process(sig_sel, sig_a, sig_b, sig_c, sig_d) is + begin + + case sig_sel is + when "00" => + sig_out <= sig_a; + when "01" => + sig_out <= sig_b; + when "10" => + sig_out <= sig_c; + when "11" => + sig_out <= sig_d; + when others => + sig_out <= (others => 'X'); + end case; + + end process; + +end architecture; diff --git a/vhdl/dev/mux_generic/mux_generic_tb.vcd b/vhdl/dev/mux_generic/mux_generic_tb.vcd @@ -0,0 +1,95 @@ +$date + Thu Apr 16 11:35:40 2026 +$end +$version + GHDL v0 +$end +$timescale + 1 fs +$end +$scope module standard $end +$upscope $end +$scope module std_logic_1164 $end +$upscope $end +$scope module numeric_std $end +$upscope $end +$scope module mux_generic_tb $end +$var reg 8 ! sig_a[7:0] $end +$var reg 8 " sig_b[7:0] $end +$var reg 8 # sig_c[7:0] $end +$var reg 8 $ sig_d[7:0] $end +$var reg 2 % sig_sel[1:0] $end +$var reg 8 & sig_out[7:0] $end +$scope module mux_a $end +$var reg 8 ' sig_a[7:0] $end +$var reg 8 ( sig_b[7:0] $end +$var reg 8 ) sig_c[7:0] $end +$var reg 8 * sig_d[7:0] $end +$var reg 2 + sig_sel[1:0] $end +$var reg 8 , sig_out[7:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +b10101010 ! +b10111011 " +b11001100 # +b11011101 $ +b00 % +b10101010 & +b10101010 ' +b10111011 ( +b11001100 ) +b11011101 * +b00 + +b10101010 , +#100000000000 +b01 % +b10111011 & +b01 + +b10111011 , +#200000000000 +b10 % +b11001100 & +b10 + +b11001100 , +#300000000000 +b11 % +b11011101 & +b11 + +b11011101 , +#400000000000 +b00 % +b10101010 & +b00 + +b10101010 , +#500000000000 +b01 % +b10111011 & +b01 + +b10111011 , +#600000000000 +b10 % +b11001100 & +b10 + +b11001100 , +#700000000000 +b11 % +b11011101 & +b11 + +b11011101 , +#800000000000 +b00 % +b10101010 & +b00 + +b10101010 , +#900000000000 +b01 % +b10111011 & +b01 + +b10111011 , +#1000000000000 +b10 % +b11001100 & +b10 + +b11001100 , diff --git a/vhdl/dev/mux_generic/mux_generic_tb.vhd b/vhdl/dev/mux_generic/mux_generic_tb.vhd @@ -0,0 +1,39 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mux_generic_tb is +end entity; + +architecture mux_generic_tb_arq of mux_generic_tb is + + constant mux_data_width : integer := 8; + + signal sig_a : unsigned(mux_data_width - 1 downto 0) := x"AA"; + signal sig_b : unsigned(mux_data_width - 1 downto 0) := x"BB"; + signal sig_c : unsigned(mux_data_width - 1 downto 0) := x"CC"; + signal sig_d : unsigned(mux_data_width - 1 downto 0) := x"DD"; + + signal sig_sel : unsigned(1 downto 0) := (others => '1'); + signal sig_out : unsigned(mux_data_width - 1 downto 0); + +begin + + -- instance of `mux` module + mux_a : entity work.mux_generic(mux_generic_arq) + generic map(mux_data_width => 8) + port map( + sig_sel => sig_sel, + sig_a => sig_a, + sig_b => sig_b, + sig_c => sig_c, + sig_d => sig_d, + sig_out => sig_out); + + process is + begin + sig_sel <= sig_sel + 1; + wait for 100 us; + end process; + +end architecture; diff --git a/vhdl/dev/mux_generic/work-obj93.cf b/vhdl/dev/mux_generic/work-obj93.cf @@ -0,0 +1,7 @@ +v 4 +file . "mux_generic.vhd" "e5d2dbf32aa100f3fc361627f930f2a3b912bf67" "20260416143540.322": + entity mux_generic at 1( 0) + 0 on 27; + architecture mux_generic_arq of mux_generic at 20( 538) + 0 on 28; +file . "mux_generic_tb.vhd" "a4eb6f06ed846cfc48453efbaf479bbf397e39a8" "20260416143540.325": + entity mux_generic_tb at 1( 0) + 0 on 29; + architecture mux_generic_tb_arq of mux_generic_tb at 8( 108) + 0 on 30;