vhdl/basics/if_elsif_else/if_elsif_else_tb.vhd (642B)
1 entity if_elsif_else_tb is 2 end entity; 3 4 architecture if_elsif_else_arq of if_elsif_else_tb is 5 6 signal count_up: integer := 0; 7 8 begin 9 10 process is 11 begin 12 13 count_up <= count_up + 1; 14 15 wait for 10 ms; 16 17 if count_up <= 2 then 18 report "count_up: " & integer'image(count_up) & " <= 2"; 19 elsif count_up <= 4 then 20 report "count_up: " & integer'image(count_up) & " <= 4"; 21 elsif count_up <= 6 then 22 report "count_up: " & integer'image(count_up) & " <= 6"; 23 else 24 -- wait forever 25 wait; 26 end if; 27 28 29 end process; 30 31 end architecture;