vhdl/basics/std_signed_unsigned/std_signed_unsigned_tb.vhd (1286B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity std_signed_unsigned_tb is 6 end entity; 7 8 architecture std_signed_unsigned_arq of std_signed_unsigned_tb is 9 10 -- the difference between signed/unsigned and logic_vector is that this 11 -- vectors are interpreted by the compiler as numbers, so they can be used 12 -- in calculations 13 signal sig_unsigned_cnt : unsigned(7 downto 0) := (others => '0'); 14 signal sig_signed_cnt : signed(7 downto 0) := (others => '0'); 15 16 signal sig_4_unsigned : unsigned(3 downto 0) := "1000"; 17 signal sig_4_signed : signed(3 downto 0) := "1000"; 18 19 signal sig_8_unsigned : unsigned(7 downto 0) := (others => '0'); 20 signal sig_8_signed : signed(7 downto 0) := (others => '0'); 21 22 begin 23 process is 24 begin 25 26 wait for 10 ns; 27 28 -- wrapping signals 29 sig_unsigned_cnt <= sig_unsigned_cnt + 1; 30 sig_signed_cnt <= sig_signed_cnt + 1; 31 32 -- adding signals 33 -- this is incremented by 4 on every run 34 sig_8_unsigned <= sig_8_unsigned + sig_4_unsigned; 35 36 -- this is decremented by 4 on every run because sig_4_signed with value 37 -- 0b1000 is -8 in decimal 38 sig_8_signed <= sig_8_signed + sig_4_signed; 39 40 end process; 41 end architecture;