vhdl/dev/mux/mux_tb.vhd (809B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity mux_tb is 6 end entity; 7 8 architecture mux_arq of mux_tb is 9 10 signal sig_a : unsigned(7 downto 0) := x"AA"; 11 signal sig_b : unsigned(7 downto 0) := x"BB"; 12 signal sig_c : unsigned(7 downto 0) := x"CC"; 13 signal sig_d : unsigned(7 downto 0) := x"DD"; 14 15 signal sig_sel : unsigned(1 downto 0) := (others => '1'); 16 signal sig_out : unsigned(7 downto 0); 17 18 begin 19 20 -- instance of `mux` module 21 mux_a : entity work.mux(mux_arq) port map( 22 sig_sel => sig_sel, 23 sig_a => sig_a, 24 sig_b => sig_b, 25 sig_c => sig_c, 26 sig_d => sig_d, 27 sig_out => sig_out); 28 29 process is 30 begin 31 sig_sel <= sig_sel + 1; 32 wait for 100 us; 33 end process; 34 35 end architecture;
