commit 0fa724c2d30a98334cb33d093f20b38b8f04158f
parent 3ceebb58de14df6029381c1d6693703154c3e015
Author: Martin Klöckner <mjkloeckner@gmail.com>
Date: Thu, 16 Apr 2026 01:38:26 -0300
Update `/**`
Diffstat:
12 files changed, 154 insertions(+), 32 deletions(-)
diff --git a/gtkwave_waveform_viewer.png b/gtkwave_waveform_viewer.png
Binary files differ.
diff --git a/surfer_waveform_viewer.png b/surfer_waveform_viewer.png
Binary files differ.
diff --git a/vhdl/README.md b/vhdl/README.md
@@ -1,3 +1,5 @@
# VHDL Examples
[Basic VHDL course](https://www.youtube.com/playlist?list=PLIbRYKjjYOPkhpxnkQ0fwTXnmgsiCMcVV)
+
+> NOTE: All vhdl containing keyword `wait` is not synthesizable
diff --git a/vhdl/clock/Makefile b/vhdl/clock/Makefile
@@ -0,0 +1,21 @@
+GHDL = ghdl
+TOP = clock_tb
+SRCS = $(TOP).vhd
+WAVEFORM_FILE = $(TOP).vcd
+
+all: run
+
+analyze:
+ $(GHDL) -a $(SRCS)
+
+elaborate: analyze
+ $(GHDL) -e $(TOP)
+
+run: elaborate
+ $(GHDL) -r $(TOP) --vcd=$(WAVEFORM_FILE) --stop-time=1ms
+
+clean:
+ rm -f *.o *.cf $(TOP) $(TOP).vcd
+
+view:
+ surfer $(WAVEFORM_FILE)
diff --git a/vhdl/clock/clock_tb.vcd b/vhdl/clock/clock_tb.vcd
@@ -0,0 +1,29 @@
+$date
+ Thu Apr 16 01:28:28 2026
+$end
+$version
+ GHDL v0
+$end
+$timescale
+ 1 fs
+$end
+$scope module standard $end
+$upscope $end
+$scope module std_logic_1164 $end
+$upscope $end
+$scope module clock_tb $end
+$var reg 1 ! clk $end
+$upscope $end
+$enddefinitions $end
+#0
+0!
+#200000000000
+1!
+#400000000000
+0!
+#600000000000
+1!
+#800000000000
+0!
+#1000000000000
+1!
diff --git a/vhdl/clock/clock_tb.vhd b/vhdl/clock/clock_tb.vhd
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+-- this implementation of clock is not synthesizable
+
+entity clock_tb is
+end entity;
+
+architecture clock_arq of clock_tb is
+
+ signal clk : std_logic := '0';
+
+begin
+
+ clk <= not clk after 200 us;
+
+end architecture;
diff --git a/vhdl/std_logic_vector/Makefile b/vhdl/std_logic_vector/Makefile
@@ -17,5 +17,5 @@ run: elaborate
clean:
rm -f *.o *.cf $(TOP) $(TOP).vcd
-view:
- surfer -c $(HOME)/.config/surfer/surfer-commands $(WAVEFORM_FILE)
+view: all
+ nohup surfer $(WAVEFORM_FILE) >/dev/null 2>&1 &
diff --git a/vhdl/std_logic_vector/std_logic_vector_tb.vcd b/vhdl/std_logic_vector/std_logic_vector_tb.vcd
@@ -1,23 +0,0 @@
-$date
- Wed Apr 15 23:03:28 2026
-$end
-$version
- GHDL v0
-$end
-$timescale
- 1 fs
-$end
-$scope module standard $end
-$upscope $end
-$scope module std_logic_1164 $end
-$upscope $end
-$scope module std_logic_vector_tb $end
-$var reg 8 ! sig_vec_a[7:0] $end
-$var reg 5 " sig_vec_b[4:0] $end
-$upscope $end
-$enddefinitions $end
-#0
-b00000000 !
-b00000 "
-#500000000000
-#1000000000000
diff --git a/vhdl/std_logic_vector/std_logic_vector_tb.vhd b/vhdl/std_logic_vector/std_logic_vector_tb.vhd
@@ -10,14 +10,32 @@ architecture std_logic_vector_arq of std_logic_vector_tb is
-- is because not only the can be assigned with 0 or 1 but also other
-- non-numeric values, such as 'Z' for a high impedance signal or '-' for a
-- don't care, etc.
- signal sig_vec_a : std_logic_vector(7 downto 0) := (others => '0');
- signal sig_vec_b : std_logic_vector(4 downto 0) := (others => '0');
+ signal sig_vec_a: std_logic_vector(7 downto 0) := "U1010101";
+ signal sig_vec_b: std_logic_vector(3 downto 0) := (others => '0');
+ signal sig_vec_c: std_logic_vector(0 to 3) := (others => '0');
+ signal sig_vec_d: std_logic_vector(7 downto 0) := "00000001";
+ signal sig_vec_e: std_logic_vector(7 downto 0) := "00000001";
begin
process is
begin
- wait for 500 us;
+ wait for 100 us;
+
+ -- shift register
+ for i in 7 downto 1 loop
+ sig_vec_d(i) <= sig_vec_d(i - 1);
+ end loop;
+
+ sig_vec_d(0) <= sig_vec_d(7);
+
+ -- shift register more generic (using signal attributes)
+ for i in sig_vec_e'left downto sig_vec_e'right + 1 loop
+ sig_vec_e(i) <= sig_vec_e(i - 1);
+ end loop;
+
+ sig_vec_e(sig_vec_e'right) <= sig_vec_e(sig_vec_e'left);
+
end process;
end architecture;
diff --git a/vhdl/std_logic_vector/work-obj93.cf b/vhdl/std_logic_vector/work-obj93.cf
@@ -1,4 +0,0 @@
-v 4
-file . "std_logic_vector_tb.vhd" "4026a7eadf796cdaf7e3b970343cce57a563ba09" "20260416020328.676":
- entity std_logic_vector_tb at 1( 0) + 0 on 15;
- architecture std_logic_vector_arq of std_logic_vector_tb at 7( 87) + 0 on 16;
diff --git a/vhdl/std_signed_unsigned/Makefile b/vhdl/std_signed_unsigned/Makefile
@@ -0,0 +1,21 @@
+GHDL = ghdl
+TOP = std_signed_unsigned_tb
+SRCS = $(TOP).vhd
+WAVEFORM_FILE = $(TOP).vcd
+
+all: run
+
+analyze:
+ $(GHDL) -a $(SRCS)
+
+elaborate: analyze
+ $(GHDL) -e $(TOP)
+
+run: elaborate
+ $(GHDL) -r $(TOP) --vcd=$(WAVEFORM_FILE) --stop-time=1ms
+
+clean:
+ rm -f *.o *.cf $(TOP) $(TOP).vcd
+
+view: all
+ nohup surfer $(WAVEFORM_FILE) >/dev/null 2>&1 &
diff --git a/vhdl/std_signed_unsigned/std_signed_unsigned_tb.vhd b/vhdl/std_signed_unsigned/std_signed_unsigned_tb.vhd
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity std_signed_unsigned_tb is
+end entity;
+
+architecture std_signed_unsigned_arq of std_signed_unsigned_tb is
+
+ -- the difference between signed/unsigned and logic_vector is that this
+ -- vectors are interpreted by the compiler as numbers, so they can be used
+ -- in calculations
+ signal sig_unsigned_cnt : unsigned(7 downto 0) := (others => '0');
+ signal sig_signed_cnt : signed(7 downto 0) := (others => '0');
+
+ signal sig_4_unsigned : unsigned(3 downto 0) := "1000";
+ signal sig_4_signed : signed(3 downto 0) := "1000";
+
+ signal sig_8_unsigned : unsigned(7 downto 0) := (others => '0');
+ signal sig_8_signed : signed(7 downto 0) := (others => '0');
+
+begin
+ process is
+ begin
+
+ wait for 10 ns;
+
+ -- wrapping signals
+ sig_unsigned_cnt <= sig_unsigned_cnt + 1;
+ sig_signed_cnt <= sig_signed_cnt + 1;
+
+ -- adding signals
+ -- this is incremented by 4 on every run
+ sig_8_unsigned <= sig_8_unsigned + sig_4_unsigned;
+
+ -- this is decremented by 4 on every run because sig_4_signed with value
+ -- 0b1000 is -8 in decimal
+ sig_8_signed <= sig_8_signed + sig_4_signed;
+
+ end process;
+end architecture;
