vhdl/basics/case_when/case_when_tb.vhd (1521B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity case_when_tb is 6 end entity; 7 8 architecture case_when_arq of case_when_tb is 9 10 signal sig_a : unsigned(7 downto 0) := x"AA"; 11 signal sig_b : unsigned(7 downto 0) := x"BB"; 12 signal sig_c : unsigned(7 downto 0) := x"CC"; 13 signal sig_d : unsigned(7 downto 0) := x"DD"; 14 15 -- initialize `sig_sel` to 0xFF to start at 0x00 after first increment 16 signal sig_sel : unsigned(1 downto 0) := (others => '1'); 17 18 signal sig_out_a : unsigned(7 downto 0); 19 signal sig_out_b : unsigned(7 downto 0); 20 21 22 begin 23 24 process is 25 begin 26 sig_sel <= sig_sel + 1; 27 wait for 100 us; 28 end process; 29 30 process(sig_sel, sig_a, sig_b, sig_c, sig_d) is 31 begin 32 33 -- mux using if-elsif-else 34 if sig_sel = "00" then 35 sig_out_a <= sig_a; 36 elsif sig_sel = "01" then 37 sig_out_a <= sig_b; 38 elsif sig_sel = "10" then 39 sig_out_a <= sig_c; 40 elsif sig_sel = "11" then 41 sig_out_a <= sig_d; 42 else 43 sig_out_a <= (others => 'X'); 44 end if; 45 46 case sig_sel is 47 when "00" => 48 sig_out_b <= sig_a; 49 when "01" => 50 sig_out_b <= sig_b; 51 when "10" => 52 sig_out_b <= sig_c; 53 when "11" => 54 sig_out_b <= sig_d; 55 when others => 56 sig_out_b <= (others => 'X'); 57 end case; 58 59 60 end process; 61 62 63 end architecture;