vhdl/dev/mux_generic/mux_generic.vhd (1042B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 -- expose signals outside of this module 6 entity mux_generic is 7 generic(mux_data_width : integer); 8 port( 9 -- inputs 10 sig_a : in unsigned(mux_data_width - 1 downto 0); 11 sig_b : in unsigned(mux_data_width - 1 downto 0); 12 sig_c : in unsigned(mux_data_width - 1 downto 0); 13 sig_d : in unsigned(mux_data_width - 1 downto 0); 14 sig_sel : in unsigned(1 downto 0); 15 16 -- outputs 17 sig_out : out unsigned(mux_data_width - 1 downto 0)); 18 end entity; 19 20 architecture mux_generic_arq of mux_generic is 21 begin 22 23 process(sig_sel, sig_a, sig_b, sig_c, sig_d) is 24 begin 25 26 case sig_sel is 27 when "00" => 28 sig_out <= sig_a; 29 when "01" => 30 sig_out <= sig_b; 31 when "10" => 32 sig_out <= sig_c; 33 when "11" => 34 sig_out <= sig_d; 35 when others => 36 sig_out <= (others => 'X'); 37 end case; 38 39 end process; 40 41 end architecture;