vhdl/basics/sensitivity_list/sensitivity_list_tb.vhd (812B)
1 entity sensitivity_list_tb is 2 end entity; 3 4 architecture sensitivity_list_arq of sensitivity_list_tb is 5 6 signal count_up: integer := 0; 7 signal count_down: integer := 10; 8 9 begin 10 11 process is 12 begin 13 14 count_up <= count_up + 1; 15 count_down <= count_down - 1; 16 17 wait for 10 ns; 18 19 end process; 20 21 process is 22 begin 23 24 if count_up = count_down then 25 report "count_up is equal to count_down"; 26 end if; 27 28 -- signal change trigger 29 wait on count_up, count_down; 30 31 end process; 32 33 -- signal change trigger but there is no need to use wait on 34 process(count_up, count_down) is 35 begin 36 37 if count_up = count_down then 38 report "count_up is equal to count_down"; 39 end if; 40 41 end process; 42 43 end architecture;