clock_tb.vhd - TA147 - Ejecicios y trabajos prácticos de la materia Taller de Sistemas Digitales (TA147)

Line numbers

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 
   4 -- this implementation of clock is not synthesizable
   5 
   6 entity clock_tb is
   7 end entity;
   8 
   9 architecture clock_arq of clock_tb is
  10 
  11     signal clk : std_logic := '0';
  12 
  13 begin
  14 
  15     clk <= not clk after 200 us;
  16 
  17 end architecture;