vhdl/basics/std_logic/std_logic_tb.vhd (619B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity std_logic_tb is 5 end entity; 6 7 architecture std_logic_arq of std_logic_tb is 8 9 -- std_logic signals use single quotation marks when assigning values, this 10 -- is because not only the can be assigned with 0 or 1 but also other 11 -- non-numeric values, such as 'Z' for a high impedance signal or '-' for a 12 -- don't care, etc. 13 signal sig_a : std_logic := '0'; 14 signal sig_b : std_logic := '0'; 15 signal sig_c : std_logic := '0'; 16 17 begin 18 process is 19 begin 20 21 wait for 500 us; 22 23 sig_a <= not sig_a; 24 25 end process; 26 end architecture;