vhdl/basics/std_logic_vector/std_logic_vector_tb.vhd (1264B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity std_logic_vector_tb is 5 end entity; 6 7 architecture std_logic_vector_arq of std_logic_vector_tb is 8 9 -- std_logic signals use single quotation marks when assigning values, this 10 -- is because not only the can be assigned with 0 or 1 but also other 11 -- non-numeric values, such as 'Z' for a high impedance signal or '-' for a 12 -- don't care, etc. 13 signal sig_vec_a: std_logic_vector(7 downto 0) := "U1010101"; 14 signal sig_vec_b: std_logic_vector(3 downto 0) := (others => '0'); 15 signal sig_vec_c: std_logic_vector(0 to 3) := (others => '0'); 16 signal sig_vec_d: std_logic_vector(7 downto 0) := "00000001"; 17 signal sig_vec_e: std_logic_vector(7 downto 0) := "00000001"; 18 19 begin 20 process is 21 begin 22 23 wait for 100 us; 24 25 -- shift register 26 for i in 7 downto 1 loop 27 sig_vec_d(i) <= sig_vec_d(i - 1); 28 end loop; 29 30 sig_vec_d(0) <= sig_vec_d(7); 31 32 -- shift register more generic (using signal attributes) 33 for i in sig_vec_e'left downto sig_vec_e'right + 1 loop 34 sig_vec_e(i) <= sig_vec_e(i - 1); 35 end loop; 36 37 sig_vec_e(sig_vec_e'right) <= sig_vec_e(sig_vec_e'left); 38 39 40 end process; 41 end architecture;