vhdl/dev/mux/mux.vhd (898B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 -- expose signals outside of this module 6 entity mux is 7 port( 8 -- inputs 9 sig_a : in unsigned(7 downto 0); 10 sig_b : in unsigned(7 downto 0); 11 sig_c : in unsigned(7 downto 0); 12 sig_d : in unsigned(7 downto 0); 13 sig_sel : in unsigned(1 downto 0); 14 15 -- outputs 16 sig_out : out unsigned(7 downto 0)); 17 end entity; 18 19 architecture mux_arq of mux is 20 begin 21 22 process(sig_sel, sig_a, sig_b, sig_c, sig_d) is 23 begin 24 25 case sig_sel is 26 when "00" => 27 sig_out <= sig_a; 28 when "01" => 29 sig_out <= sig_b; 30 when "10" => 31 sig_out <= sig_c; 32 when "11" => 33 sig_out <= sig_d; 34 when others => 35 sig_out <= (others => 'X'); 36 end case; 37 38 end process; 39 40 end architecture;