vhdl/dev/mux_generic/mux_generic_tb.vhd (1037B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity mux_generic_tb is 6 end entity; 7 8 architecture mux_generic_tb_arq of mux_generic_tb is 9 10 constant mux_data_width : integer := 8; 11 12 signal sig_a : unsigned(mux_data_width - 1 downto 0) := x"AA"; 13 signal sig_b : unsigned(mux_data_width - 1 downto 0) := x"BB"; 14 signal sig_c : unsigned(mux_data_width - 1 downto 0) := x"CC"; 15 signal sig_d : unsigned(mux_data_width - 1 downto 0) := x"DD"; 16 17 signal sig_sel : unsigned(1 downto 0) := (others => '1'); 18 signal sig_out : unsigned(mux_data_width - 1 downto 0); 19 20 begin 21 22 -- instance of `mux` module 23 mux_a : entity work.mux_generic(mux_generic_arq) 24 generic map(mux_data_width => mux_data_width) 25 port map( 26 sig_sel => sig_sel, 27 sig_a => sig_a, 28 sig_b => sig_b, 29 sig_c => sig_c, 30 sig_d => sig_d, 31 sig_out => sig_out); 32 33 process is 34 begin 35 sig_sel <= sig_sel + 1; 36 wait for 100 us; 37 end process; 38 39 end architecture;