commit 5bb0f1d09d6f974a431b8e7e7ca026efc4595d06
parent f18647bd49d642cca7c273f878d93178ecfef846
Author: Martin Klöckner <mjkloeckner@gmail.com>
Date: Fri, 17 Apr 2026 01:07:06 -0300
Update `vhdl/dev/multiplier`
Diffstat:
6 files changed, 56 insertions(+), 42 deletions(-)
diff --git a/vhdl/dev/adder_generic/adder_tb.vhd b/vhdl/dev/adder_generic/adder_tb.vhd
@@ -21,10 +21,10 @@ begin
adder : entity work.adder(adder_arq)
generic map(N => N)
port map(
- A => sig_A,
- B => sig_B,
- C_in => sig_C_in,
- res => sig_res,
- C_out => sig_C_out);
+ A => sig_A,
+ B => sig_B,
+ C_in => sig_C_in,
+ res => sig_res,
+ C_out => sig_C_out);
end architecture;
diff --git a/vhdl/dev/multiplier/Makefile b/vhdl/dev/multiplier/Makefile
@@ -1,21 +1,27 @@
-GHDL = ghdl
+GHDL = ghdl
+
DEV_NAME = multiplier
TOP = $(DEV_NAME)_tb
TOP_SRC = $(TOP).vhd
SRCS = reg.vhd adder.vhd multiplier.vhd
WAVEFORM_FILE = $(TOP).vcd
+SIM_AFLAGS = --std=93
+SIM_EFLAGS = --std=93
+SIM_RFLAGS = --std=93
+SIM_RUNOPTS = --vcd=$(WAVEFORM_FILE) --stop-time=1ms
+
all: run
analyze:
- $(GHDL) -a $(SRCS)
- $(GHDL) -a $(TOP_SRC)
+ $(GHDL) -a $(SIM_AFLAGS) $(SRCS)
+ $(GHDL) -a $(SIM_AFLAGS) $(TOP_SRC)
elaborate: analyze
- $(GHDL) -e $(TOP)
+ $(GHDL) -e $(SIM_EFLAGS) $(TOP)
run: elaborate
- $(GHDL) -r $(TOP) --vcd=$(WAVEFORM_FILE) --stop-time=1ms
+ $(GHDL) -r $(SIM_RFLAGS) $(TOP) $(SIM_RUNOPTS)
clean:
rm -f *.o *.cf $(TOP) $(TOP).vcd
diff --git a/vhdl/dev/multiplier/adder.vhd b/vhdl/dev/multiplier/adder.vhd
@@ -3,16 +3,16 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
- generic(N : integer := 4); -- number of bits
+ generic(N : natural := 4); -- number of bits
port(
-- inputs
- op_A : in std_logic_vector(N-1 downto 0);
- op_B : in std_logic_vector(N-1 downto 0);
- c_in : in std_logic;
+ A : in std_logic_vector(N-1 downto 0);
+ B : in std_logic_vector(N-1 downto 0);
+ C_in : in std_logic;
-- outputs
res : out std_logic_vector(N-1 downto 0);
- c_out : out std_logic);
+ C_out : out std_logic);
end entity;
architecture adder_arq of adder is
@@ -21,8 +21,8 @@ architecture adder_arq of adder is
begin
- res_aux <= std_logic_vector(unsigned('0' & op_A & c_in) + unsigned('0' & op_B & '1'));
+ res_aux <= std_logic_vector(unsigned('0' & A & C_in) + unsigned('0' & B & '1'));
res <= res_aux(N downto 1);
- c_out <= res_aux(N+1);
+ C_out <= res_aux(N+1);
end architecture;
diff --git a/vhdl/dev/multiplier/multiplier.vhd b/vhdl/dev/multiplier/multiplier.vhd
@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
- generic(N : natural := 8);
+ generic(N : natural := 4);
port(
op_A : in std_logic_vector(N-1 downto 0);
op_B : in std_logic_vector(N-1 downto 0);
@@ -21,7 +21,7 @@ architecture multiplier_arq of multiplier is
begin
A_reg : entity work.reg(reg_arq)
- generic map(N => 8)
+ generic map(N => N)
port map(
D => op_A,
clk => clk,
@@ -30,7 +30,7 @@ begin
Q => A_out);
B_reg : entity work.reg(reg_arq)
- generic map(N => 8)
+ generic map(N => N)
port map(
D => B_in,
clk => clk,
@@ -39,7 +39,7 @@ begin
Q => B_out);
P_reg : entity work.reg(reg_arq)
- generic map(N => 8)
+ generic map(N => N)
port map(
D => P_in,
clk => clk,
@@ -48,17 +48,17 @@ begin
Q => P_out);
adder : entity work.adder(adder_arq)
- generic map(N => 8)
+ generic map(N => N)
port map(
- op_A => P_out,
- op_B => aux,
- c_in => '0',
- res => sum_out,
- c_out => C_out);
+ A => P_out,
+ B => aux,
+ C_in => '0',
+ res => sum_out,
+ C_out => C_out);
- in_P <= c_out & out_sum(N-1 downto 1);
- in_B <= op_B when load = '1' else out_sum(0) & out_B(N-1 downto 1);
- aux <= out_A when out_B(0) = '1' else (others => '0');
- res <= out_P & out_B;
+ P_in <= C_out & sum_out(N-1 downto 1);
+ B_in <= op_B when load = '1' else sum_out(0) & B_out(N-1 downto 1);
+ aux <= A_out when B_out(0) = '1' else (others => '0');
+ res <= P_out & B_out;
end architecture;
diff --git a/vhdl/dev/multiplier/multiplier_tb.vhd b/vhdl/dev/multiplier/multiplier_tb.vhd
@@ -7,25 +7,33 @@ end entity;
architecture multiplier_tb_arq of multiplier_tb is
- constant N : integer := 8;
+ constant N : natural := 4;
- signal A : std_logic_vector(N - 1 downto 0) := x"01";
- signal B : std_logic_vector(N - 1 downto 0) := x"02";
+ signal A : std_logic_vector(N - 1 downto 0) := x"2";
+ signal B : std_logic_vector(N - 1 downto 0) := x"3";
signal load : std_logic := '1';
signal clk : std_logic := '0';
signal res : std_logic_vector(2*N-1 downto 0);
begin
- DUT : entity work.multiplier(multiplier_arq)
+ multiplier : entity work.multiplier(multiplier_arq)
generic map(N => N)
port map(
+
op_A => A,
op_B => B,
load => load,
- clk => clk,
- res => res);
+ clk => clk,
+ res => res);
+
+ process(clk) is
+ begin
+
+ load <= '0' after 10 us;
+
+ end process;
- clk <= not clk after 1 us;
+ clk <= not clk after 50 us;
end architecture;
diff --git a/vhdl/dev/multiplier/reg.vhd b/vhdl/dev/multiplier/reg.vhd
@@ -6,10 +6,10 @@ entity reg is
generic(N: integer:= 4);
port(
-- inputs
- D : in std_logic_vector(N-1 downto 0);
- clk : in std_logic;
- rst : in std_logic;
- ena : in std_logic;
+ D : in std_logic_vector(N-1 downto 0);
+ clk : in std_logic;
+ rst : in std_logic;
+ ena : in std_logic;
-- outputs
Q : out std_logic_vector(N-1 downto 0)
