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commit f18647bd49d642cca7c273f878d93178ecfef846
parent 48102e6f8dba965779fc88e0d88759c7263c61f8
Author: Martin Kloeckner <mjkloeckner@gmail.com>
Date:   Thu, 16 Apr 2026 23:36:31 -0300

Updated `vhdl/dev/multiplier/`

Diffstat:
M
vhdl/dev/multiplier/multiplier.vhd
 | 
46
++++++++++++++++++++++------------------------
M
vhdl/dev/multiplier/multiplier_tb.vhd
 | 
3
+--

2 files changed, 23 insertions(+), 26 deletions(-)
diff --git a/vhdl/dev/multiplier/multiplier.vhd b/vhdl/dev/multiplier/multiplier.vhd
@@ -5,62 +5,60 @@ use ieee.numeric_std.all;
 entity multiplier is
     generic(N : natural := 8);
     port(
-        op_A : in std_logic_vector(N-1 downto 0);
-        op_B : in std_logic_vector(N-1 downto 0);
-        load : in std_logic;
-        clk  : in std_logic;
+        op_A : in  std_logic_vector(N-1 downto 0);
+        op_B : in  std_logic_vector(N-1 downto 0);
+        load : in  std_logic;
+        clk  : in  std_logic;
         res  : out std_logic_vector(2*N-1 downto 0));
 end entity;
 
 architecture multiplier_arq of multiplier is
-    signal in_P, in_B, aux              : std_logic_vector(N-1 downto 0);
-    signal out_P, out_B, out_sum, out_A : std_logic_vector(N-1 downto 0);
-    signal c_out : std_logic;
+
+    signal B_in, P_in, aux              : std_logic_vector(N-1 downto 0);
+    signal A_out, B_out, P_out, sum_out : std_logic_vector(N-1 downto 0);
+    signal C_out : std_logic;
 
 begin
 
-    reg_A : entity work.reg(reg_arq)
+    A_reg : entity work.reg(reg_arq)
     generic map(N => 8)
     port map(
         D   => op_A,
         clk => clk,
         rst => '0',
         ena => '1',
-        Q   => out_A);
+        Q   => A_out);
 
-    reg_B : entity work.reg(reg_arq)
+    B_reg : entity work.reg(reg_arq)
     generic map(N => 8)
     port map(
-        D   => in_B,
+        D   => B_in,
         clk => clk,
         rst => '0',
         ena => '1',
-        Q   => out_B);
+        Q   => B_out);
 
-    reg_P : entity work.reg(reg_arq)
+    P_reg : entity work.reg(reg_arq)
     generic map(N => 8)
     port map(
-        D   => in_P,
+        D   => P_in,
         clk => clk,
         rst => load,
         ena => '1',
-        Q   => out_P);
+        Q   => P_out);
 
-    adder_A : entity work.adder(adder_arq)
+    adder : entity work.adder(adder_arq)
     generic map(N => 8)
     port map(
-       op_A => out_P,
-       op_B => aux,
-       c_in => '0',
-       res => out_sum,
-       c_out => c_out);
+       op_A  => P_out,
+       op_B  => aux,
+       c_in  => '0',
+       res   => sum_out,
+       c_out => C_out);
 
     in_P <= c_out & out_sum(N-1 downto 1);
-
     in_B <= op_B when load = '1' else out_sum(0) & out_B(N-1 downto 1);
-
     aux <= out_A when out_B(0) = '1' else (others => '0');
-
     res <= out_P & out_B;
 
 end architecture;
diff --git a/vhdl/dev/multiplier/multiplier_tb.vhd b/vhdl/dev/multiplier/multiplier_tb.vhd
@@ -10,7 +10,7 @@ architecture multiplier_tb_arq of multiplier_tb is
     constant N : integer := 8;
 
     signal A    : std_logic_vector(N - 1 downto 0) := x"01";
-    signal B    : std_logic_vector(N - 1 downto 0) := x"01";
+    signal B    : std_logic_vector(N - 1 downto 0) := x"02";
     signal load : std_logic := '1';
     signal clk  : std_logic := '0';
     signal res  : std_logic_vector(2*N-1 downto 0);
@@ -27,6 +27,5 @@ begin
         res => res);
 
     clk <= not clk after 1 us;
-    A <= x"20" after 100 us;
 
 end architecture;