vhdl/dev/multiplier/multiplier.vhd (1552B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity multiplier is 6 generic(N : natural := 4); 7 port( 8 op_A : in std_logic_vector(N-1 downto 0); 9 op_B : in std_logic_vector(N-1 downto 0); 10 load : in std_logic; 11 clk : in std_logic; 12 res : out std_logic_vector(2*N-1 downto 0)); 13 end entity; 14 15 architecture multiplier_arq of multiplier is 16 17 signal B_in, P_in, aux : std_logic_vector(N-1 downto 0); 18 signal A_out, B_out, P_out, sum_out : std_logic_vector(N-1 downto 0); 19 signal C_out : std_logic; 20 21 begin 22 23 A_reg : entity work.reg(reg_arq) 24 generic map(N => N) 25 port map( 26 D => op_A, 27 clk => clk, 28 rst => '0', 29 ena => '1', 30 Q => A_out); 31 32 B_reg : entity work.reg(reg_arq) 33 generic map(N => N) 34 port map( 35 D => B_in, 36 clk => clk, 37 rst => '0', 38 ena => '1', 39 Q => B_out); 40 41 P_reg : entity work.reg(reg_arq) 42 generic map(N => N) 43 port map( 44 D => P_in, 45 clk => clk, 46 rst => load, 47 ena => '1', 48 Q => P_out); 49 50 adder : entity work.adder(adder_arq) 51 generic map(N => N) 52 port map( 53 A => P_out, 54 B => aux, 55 C_in => '0', 56 res => sum_out, 57 C_out => C_out); 58 59 P_in <= C_out & sum_out(N-1 downto 1); 60 B_in <= op_B when load = '1' else sum_out(0) & B_out(N-1 downto 1); 61 aux <= A_out when B_out(0) = '1' else (others => '0'); 62 res <= P_out & B_out; 63 64 end architecture;