vhdl/dev/multiplier/multiplier_tb.vhd (777B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity multiplier_tb is 6 end entity; 7 8 architecture multiplier_tb_arq of multiplier_tb is 9 10 constant N : natural := 4; 11 12 signal A : std_logic_vector(N - 1 downto 0) := x"2"; 13 signal B : std_logic_vector(N - 1 downto 0) := x"3"; 14 signal load : std_logic := '1'; 15 signal clk : std_logic := '0'; 16 signal res : std_logic_vector(2*N-1 downto 0); 17 18 begin 19 20 multiplier : entity work.multiplier(multiplier_arq) 21 generic map(N => N) 22 port map( 23 24 op_A => A, 25 op_B => B, 26 load => load, 27 clk => clk, 28 res => res); 29 30 process(clk) is 31 begin 32 33 load <= '0' after 10 us; 34 35 end process; 36 37 clk <= not clk after 50 us; 38 39 end architecture;