adder_tb.vhd - TA147 - Ejecicios y trabajos prácticos de la materia Taller de Sistemas Digitales (TA147)

vhdl/dev/adder_generic/adder_tb.vhd (718B)

Line numbers

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 
   5 entity adder_tb is
   6 end entity;
   7 
   8 architecture adder_tb_arq of adder_tb is
   9 
  10     constant N : natural := 4;
  11 
  12     signal sig_A    : std_logic_vector(N-1 downto 0) := std_logic_vector(to_unsigned(3, N));
  13     signal sig_B    : std_logic_vector(N-1 downto 0) := std_logic_vector(to_unsigned(7, N));
  14     signal sig_C_in : std_logic := '0';
  15 
  16     signal sig_res   : std_logic_vector(N-1 downto 0);
  17     signal sig_C_out : std_logic;
  18 
  19 begin
  20 
  21     adder : entity work.adder(adder_arq)
  22     generic map(N => N)
  23     port map(
  24       A     => sig_A,
  25       B     => sig_B,
  26       C_in  => sig_C_in,
  27       res   => sig_res,
  28       C_out => sig_C_out);
  29 
  30 end architecture;