vhdl/dev/multiplier/adder.vhd (672B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity adder is 6 generic(N : natural := 4); -- number of bits 7 port( 8 -- inputs 9 A : in std_logic_vector(N-1 downto 0); 10 B : in std_logic_vector(N-1 downto 0); 11 C_in : in std_logic; 12 13 -- outputs 14 res : out std_logic_vector(N-1 downto 0); 15 C_out : out std_logic); 16 end entity; 17 18 architecture adder_arq of adder is 19 20 signal res_aux : std_logic_vector(N+1 downto 0); 21 22 begin 23 24 res_aux <= std_logic_vector(unsigned('0' & A & C_in) + unsigned('0' & B & '1')); 25 res <= res_aux(N downto 1); 26 C_out <= res_aux(N+1); 27 28 end architecture;