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commit d8c7f977087dfb32e0af2856c0eabe208bb7d705
parent 5bb0f1d09d6f974a431b8e7e7ca026efc4595d06
Author: Martin Klöckner <mjkloeckner@gmail.com>
Date:   Fri, 17 Apr 2026 10:29:18 -0300

Add `vhdl/dev/rtc/`

Diffstat:
A
vhdl/dev/rtc/Makefile
 | 
24
++++++++++++++++++++++++
A
vhdl/dev/rtc/rtc.vhd
 | 
42
++++++++++++++++++++++++++++++++++++++++++
A
vhdl/dev/rtc/rtc_tb.vhd
 | 
27
+++++++++++++++++++++++++++

3 files changed, 93 insertions(+), 0 deletions(-)
diff --git a/vhdl/dev/rtc/Makefile b/vhdl/dev/rtc/Makefile
@@ -0,0 +1,24 @@
+GHDL          = ghdl
+DEV_NAME      = rtc
+TOP           = $(DEV_NAME)_tb
+TOP_SRC       = $(TOP).vhd
+SRCS          = $(DEV_NAME).vhd
+WAVEFORM_FILE = $(TOP).vcd
+
+all: run
+
+analyze:
+    $(GHDL) -a $(SRCS)
+    $(GHDL) -a $(TOP_SRC)
+
+elaborate: analyze
+    $(GHDL) -e $(TOP)
+
+run: elaborate
+    $(GHDL) -r $(TOP) --vcd=$(WAVEFORM_FILE) --stop-time=2ms
+
+clean:
+    rm -f *.o *.cf $(TOP) $(TOP).vcd
+
+view: all
+    nohup surfer $(WAVEFORM_FILE) >/dev/null 2>&1 &
diff --git a/vhdl/dev/rtc/rtc.vhd b/vhdl/dev/rtc/rtc.vhd
@@ -0,0 +1,42 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity rtc is
+    generic(clk_freq: integer := 50e6);
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+
+        clk_ms : out std_logic);
+end;
+
+architecture rtc_arq of rtc is
+
+    signal tick_cnt : unsigned(31 downto 0) := (others => '0');
+    signal clk_aux  : std_logic := '0';
+
+begin
+
+    process(clk, rst)
+    begin
+
+        if rising_edge(clk) then
+            if rst = '1' then
+                tick_cnt <= (others => '0');
+                clk_aux <= '0';
+            else
+                tick_cnt <= tick_cnt + 1;
+
+                if tick_cnt = clk_freq/(2*1e3) then
+                    tick_cnt <= (others => '0');
+                    clk_aux <= not clk_aux;
+                end if;
+            end if;
+        end if;
+
+    end process;
+
+    clk_ms <= clk_aux;
+
+end architecture;
diff --git a/vhdl/dev/rtc/rtc_tb.vhd b/vhdl/dev/rtc/rtc_tb.vhd
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity rtc_tb is
+end entity;
+
+architecture rtc_arq of rtc_tb is
+
+    constant clk_freq : integer := 1e6;
+
+    signal sig_clk : std_logic := '0';
+    signal sig_rst : std_logic := '0';
+    signal sig_clk_ms : std_logic;
+
+begin
+
+    rtc : entity work.rtc(rtc_arq)
+    generic map(clk_freq => clk_freq)
+    port map(
+        clk    => sig_clk,
+        rst    => sig_rst,
+        clk_ms => sig_clk_ms);
+
+    sig_clk <= not sig_clk after 1 us;
+
+end architecture;