vhdl/dev/rtc/rtc.vhd (873B)
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity rtc is 6 generic(clk_freq: integer := 50e6); 7 port( 8 clk : in std_logic; 9 rst : in std_logic; 10 11 clk_ms : out std_logic); 12 end; 13 14 architecture rtc_arq of rtc is 15 16 signal tick_cnt : unsigned(31 downto 0) := (others => '0'); 17 signal clk_aux : std_logic := '0'; 18 19 begin 20 21 process(clk, rst) 22 begin 23 24 if rising_edge(clk) then 25 if rst = '1' then 26 tick_cnt <= (others => '0'); 27 clk_aux <= '0'; 28 else 29 tick_cnt <= tick_cnt + 1; 30 31 if tick_cnt = clk_freq/(2*1e3) then 32 tick_cnt <= (others => '0'); 33 clk_aux <= not clk_aux; 34 end if; 35 end if; 36 end if; 37 38 end process; 39 40 clk_ms <= clk_aux; 41 42 end architecture;