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commit 98774a9841a13736072a62d6369d4ccc64d34b53
parent 9e67793bccc46cb26c8e9ef68e5e203fd1ebbdef
Author: Martin Kloeckner <mjkloeckner@gmail.com>
Date:   Thu, 16 Apr 2026 23:15:08 -0300

Add `vhdl/dev/flip_flop_d`

Diffstat:
A
vhdl/dev/flip_flop_d/Makefile
 | 
24
++++++++++++++++++++++++
A
vhdl/dev/flip_flop_d/flip_flop_d.vhd
 | 
35
+++++++++++++++++++++++++++++++++++
A
vhdl/dev/flip_flop_d/flip_flop_d_tb.vhd
 | 
33
+++++++++++++++++++++++++++++++++

3 files changed, 92 insertions(+), 0 deletions(-)
diff --git a/vhdl/dev/flip_flop_d/Makefile b/vhdl/dev/flip_flop_d/Makefile
@@ -0,0 +1,24 @@
+GHDL          = ghdl
+DEV_NAME      = flip_flop_d
+TOP           = $(DEV_NAME)_tb
+TOP_SRC       = $(TOP).vhd
+SRCS          = $(DEV_NAME).vhd
+WAVEFORM_FILE = $(TOP).vcd
+
+all: run
+
+analyze:
+    $(GHDL) -a $(SRCS)
+    $(GHDL) -a $(TOP_SRC)
+
+elaborate: analyze
+    $(GHDL) -e $(TOP)
+
+run: elaborate
+    $(GHDL) -r $(TOP) --vcd=$(WAVEFORM_FILE) --stop-time=1ms
+
+clean:
+    rm -f *.o *.cf $(TOP) $(TOP).vcd
+
+view: all
+    nohup surfer $(WAVEFORM_FILE) >/dev/null 2>&1 &
diff --git a/vhdl/dev/flip_flop_d/flip_flop_d.vhd b/vhdl/dev/flip_flop_d/flip_flop_d.vhd
@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity flip_flop_d is
+    generic(N: integer:= 4);
+    port(
+        -- inputs
+        D   : in  std_logic_vector(N-1 downto 0);
+        clk : in  std_logic;
+        rst : in  std_logic;
+        ena : in  std_logic;
+
+        -- outputs
+        Q   : out std_logic_vector(N-1 downto 0)
+    );
+end;
+
+architecture flip_flop_d_arq of flip_flop_d is
+begin
+
+    process(clk, rst)
+    begin
+
+        if rising_edge(clk) then
+            if rst = '1' then
+                Q <= (others => '0');
+            elsif ena = '1' then
+                Q <= D;
+            end if;
+        end if;
+
+    end process;
+
+end architecture;
diff --git a/vhdl/dev/flip_flop_d/flip_flop_d_tb.vhd b/vhdl/dev/flip_flop_d/flip_flop_d_tb.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity flip_flop_d_tb is
+end entity;
+
+architecture flip_flop_d_arq of flip_flop_d_tb is
+
+    constant N : integer := 4;
+
+    signal sig_D   : std_logic_vector(N-1 downto 0) := (others => '0');
+    signal sig_Q   : std_logic_vector(N-1 downto 0);
+    signal sig_clk : std_logic := '0';
+    signal sig_rst : std_logic := '0';
+    signal sig_ena : std_logic := '1';
+
+begin
+
+    flip_flop_d : entity work.flip_flop_d(flip_flop_d_arq)
+    generic map(N => N)
+    port map(
+        D   => sig_D,
+        Q   => sig_Q,
+        clk => sig_clk,
+        rst => sig_rst,
+        ena => sig_ena);
+
+    sig_D <= (others => '1') after 5 us;
+    sig_clk <= not sig_clk after 1 us;
+    sig_rst <= '1' after 10 us, '0' after 20 us;
+
+end architecture;