Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h (24806B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_system.h 4 * @author MCD Application Team 5 * @brief Header file of SYSTEM LL module. 6 * 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2016 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 @verbatim 19 ============================================================================== 20 ##### How to use this driver ##### 21 ============================================================================== 22 [..] 23 The LL SYSTEM driver contains a set of generic APIs that can be 24 used by user: 25 (+) Some of the FLASH features need to be handled in the SYSTEM file. 26 (+) Access to DBGCMU registers 27 (+) Access to SYSCFG registers 28 29 @endverbatim 30 ****************************************************************************** 31 */ 32 33 /* Define to prevent recursive inclusion -------------------------------------*/ 34 #ifndef __STM32F1xx_LL_SYSTEM_H 35 #define __STM32F1xx_LL_SYSTEM_H 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /* Includes ------------------------------------------------------------------*/ 42 #include "stm32f1xx.h" 43 44 /** @addtogroup STM32F1xx_LL_Driver 45 * @{ 46 */ 47 48 #if defined (FLASH) || defined (DBGMCU) 49 50 /** @defgroup SYSTEM_LL SYSTEM 51 * @{ 52 */ 53 54 /* Private types -------------------------------------------------------------*/ 55 /* Private variables ---------------------------------------------------------*/ 56 57 /* Private constants ---------------------------------------------------------*/ 58 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants 59 * @{ 60 */ 61 62 /** 63 * @} 64 */ 65 66 /* Private macros ------------------------------------------------------------*/ 67 68 /* Exported types ------------------------------------------------------------*/ 69 /* Exported constants --------------------------------------------------------*/ 70 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants 71 * @{ 72 */ 73 74 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment 75 * @{ 76 */ 77 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ 78 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ 79 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ 80 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ 81 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ 82 /** 83 * @} 84 */ 85 86 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP 87 * @{ 88 */ 89 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ 90 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ 91 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ 92 #if defined(DBGMCU_CR_DBG_TIM5_STOP) 93 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ 94 #endif /* DBGMCU_CR_DBG_TIM5_STOP */ 95 #if defined(DBGMCU_CR_DBG_TIM6_STOP) 96 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ 97 #endif /* DBGMCU_CR_DBG_TIM6_STOP */ 98 #if defined(DBGMCU_CR_DBG_TIM7_STOP) 99 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ 100 #endif /* DBGMCU_CR_DBG_TIM7_STOP */ 101 #if defined(DBGMCU_CR_DBG_TIM12_STOP) 102 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ 103 #endif /* DBGMCU_CR_DBG_TIM12_STOP */ 104 #if defined(DBGMCU_CR_DBG_TIM13_STOP) 105 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ 106 #endif /* DBGMCU_CR_DBG_TIM13_STOP */ 107 #if defined(DBGMCU_CR_DBG_TIM14_STOP) 108 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ 109 #endif /* DBGMCU_CR_DBG_TIM14_STOP */ 110 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ 111 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ 112 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 113 #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 114 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ 115 #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ 116 #if defined(DBGMCU_CR_DBG_CAN1_STOP) 117 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ 118 #endif /* DBGMCU_CR_DBG_CAN1_STOP */ 119 #if defined(DBGMCU_CR_DBG_CAN2_STOP) 120 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ 121 #endif /* DBGMCU_CR_DBG_CAN2_STOP */ 122 /** 123 * @} 124 */ 125 126 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP 127 * @{ 128 */ 129 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ 130 #if defined(DBGMCU_CR_DBG_TIM8_STOP) 131 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ 132 #endif /* DBGMCU_CR_DBG_CAN1_STOP */ 133 #if defined(DBGMCU_CR_DBG_TIM9_STOP) 134 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ 135 #endif /* DBGMCU_CR_DBG_TIM9_STOP */ 136 #if defined(DBGMCU_CR_DBG_TIM10_STOP) 137 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ 138 #endif /* DBGMCU_CR_DBG_TIM10_STOP */ 139 #if defined(DBGMCU_CR_DBG_TIM11_STOP) 140 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ 141 #endif /* DBGMCU_CR_DBG_TIM11_STOP */ 142 #if defined(DBGMCU_CR_DBG_TIM15_STOP) 143 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ 144 #endif /* DBGMCU_CR_DBG_TIM15_STOP */ 145 #if defined(DBGMCU_CR_DBG_TIM16_STOP) 146 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ 147 #endif /* DBGMCU_CR_DBG_TIM16_STOP */ 148 #if defined(DBGMCU_CR_DBG_TIM17_STOP) 149 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ 150 #endif /* DBGMCU_CR_DBG_TIM17_STOP */ 151 /** 152 * @} 153 */ 154 155 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY 156 * @{ 157 */ 158 #if defined(FLASH_ACR_LATENCY) 159 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ 160 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ 161 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ 162 #else 163 #endif /* FLASH_ACR_LATENCY */ 164 /** 165 * @} 166 */ 167 168 /** 169 * @} 170 */ 171 172 /* Exported macro ------------------------------------------------------------*/ 173 174 /* Exported functions --------------------------------------------------------*/ 175 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions 176 * @{ 177 */ 178 179 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU 180 * @{ 181 */ 182 183 /** 184 * @brief Return the device identifier 185 * @note For Low Density devices, the device ID is 0x412 186 * @note For Medium Density devices, the device ID is 0x410 187 * @note For High Density devices, the device ID is 0x414 188 * @note For XL Density devices, the device ID is 0x430 189 * @note For Connectivity Line devices, the device ID is 0x418 190 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID 191 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF 192 */ 193 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) 194 { 195 return (uint32_t) (READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); 196 } 197 198 /** 199 * @brief Return the device revision identifier 200 * @note This field indicates the revision of the device. 201 For example, it is read as revA -> 0x1000,for Low Density devices 202 For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices 203 For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices 204 For example, it is read as revA or 1 -> 0x1003,for XL Density devices 205 For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices 206 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID 207 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF 208 */ 209 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) 210 { 211 return (uint32_t) (READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) 212 >> DBGMCU_IDCODE_REV_ID_Pos); 213 } 214 215 /** 216 * @brief Enable the Debug Module during SLEEP mode 217 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode 218 * @retval None 219 */ 220 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) 221 { 222 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 223 } 224 225 /** 226 * @brief Disable the Debug Module during SLEEP mode 227 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode 228 * @retval None 229 */ 230 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) 231 { 232 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 233 } 234 235 /** 236 * @brief Enable the Debug Module during STOP mode 237 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode 238 * @retval None 239 */ 240 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) 241 { 242 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 243 } 244 245 /** 246 * @brief Disable the Debug Module during STOP mode 247 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode 248 * @retval None 249 */ 250 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) 251 { 252 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 253 } 254 255 /** 256 * @brief Enable the Debug Module during STANDBY mode 257 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode 258 * @retval None 259 */ 260 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) 261 { 262 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 263 } 264 265 /** 266 * @brief Disable the Debug Module during STANDBY mode 267 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode 268 * @retval None 269 */ 270 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) 271 { 272 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 273 } 274 275 /** 276 * @brief Set Trace pin assignment control 277 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n 278 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment 279 * @param PinAssignment This parameter can be one of the following values: 280 * @arg @ref LL_DBGMCU_TRACE_NONE 281 * @arg @ref LL_DBGMCU_TRACE_ASYNCH 282 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 283 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 284 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 285 * @retval None 286 */ 287 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) 288 { 289 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, 290 PinAssignment); 291 } 292 293 /** 294 * @brief Get Trace pin assignment control 295 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n 296 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment 297 * @retval Returned value can be one of the following values: 298 * @arg @ref LL_DBGMCU_TRACE_NONE 299 * @arg @ref LL_DBGMCU_TRACE_ASYNCH 300 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 301 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 302 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 303 */ 304 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) 305 { 306 return (uint32_t) (READ_BIT(DBGMCU->CR, 307 DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); 308 } 309 310 /** 311 * @brief Freeze APB1 peripherals (group1 peripherals) 312 * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 313 * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 314 * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 315 * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 316 * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 317 * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 318 * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 319 * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 320 * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 321 * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 322 * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 323 * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 324 * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n 325 * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n 326 * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 327 * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph 328 * @param Periphs This parameter can be a combination of the following values: 329 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 330 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP 331 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP 332 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 333 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 334 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP 335 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP 336 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP 337 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP 338 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP 339 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP 340 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 341 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) 342 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) 343 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) 344 * 345 * (*) value not defined in all devices. 346 * @retval None 347 */ 348 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) 349 { 350 SET_BIT(DBGMCU->CR, Periphs); 351 } 352 353 /** 354 * @brief Unfreeze APB1 peripherals (group1 peripherals) 355 * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 356 * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 357 * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 358 * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 359 * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 360 * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 361 * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 362 * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 363 * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 364 * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 365 * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 366 * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 367 * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 368 * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 369 * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 370 * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph 371 * @param Periphs This parameter can be a combination of the following values: 372 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 373 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP 374 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP 375 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 376 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 377 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP 378 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP 379 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP 380 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP 381 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP 382 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP 383 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP 384 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 385 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) 386 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) 387 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) 388 * 389 * (*) value not defined in all devices. 390 * @retval None 391 */ 392 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) 393 { 394 CLEAR_BIT(DBGMCU->CR, Periphs); 395 } 396 397 /** 398 * @brief Freeze APB2 peripherals 399 * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 400 * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 401 * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 402 * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 403 * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 404 * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 405 * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 406 * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph 407 * @param Periphs This parameter can be a combination of the following values: 408 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 409 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) 410 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) 411 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) 412 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) 413 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) 414 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) 415 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) 416 * 417 * (*) value not defined in all devices. 418 * @retval None 419 */ 420 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) 421 { 422 SET_BIT(DBGMCU->CR, Periphs); 423 } 424 425 /** 426 * @brief Unfreeze APB2 peripherals 427 * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 428 * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 429 * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 430 * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 431 * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 432 * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 433 * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 434 * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph 435 * @param Periphs This parameter can be a combination of the following values: 436 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 437 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) 438 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) 439 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) 440 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) 441 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) 442 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) 443 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) 444 * 445 * (*) value not defined in all devices. 446 * @retval None 447 */ 448 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) 449 { 450 CLEAR_BIT(DBGMCU->CR, Periphs); 451 } 452 /** 453 * @} 454 */ 455 456 #if defined(FLASH_ACR_LATENCY) 457 /** @defgroup SYSTEM_LL_EF_FLASH FLASH 458 * @{ 459 */ 460 461 /** 462 * @brief Set FLASH Latency 463 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency 464 * @param Latency This parameter can be one of the following values: 465 * @arg @ref LL_FLASH_LATENCY_0 466 * @arg @ref LL_FLASH_LATENCY_1 467 * @arg @ref LL_FLASH_LATENCY_2 468 * @retval None 469 */ 470 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) 471 { 472 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 473 } 474 475 /** 476 * @brief Get FLASH Latency 477 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency 478 * @retval Returned value can be one of the following values: 479 * @arg @ref LL_FLASH_LATENCY_0 480 * @arg @ref LL_FLASH_LATENCY_1 481 * @arg @ref LL_FLASH_LATENCY_2 482 */ 483 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) 484 { 485 return (uint32_t) (READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); 486 } 487 488 /** 489 * @brief Enable Prefetch 490 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch 491 * @retval None 492 */ 493 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) 494 { 495 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); 496 } 497 498 /** 499 * @brief Disable Prefetch 500 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch 501 * @retval None 502 */ 503 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) 504 { 505 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); 506 } 507 508 /** 509 * @brief Check if Prefetch buffer is enabled 510 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled 511 * @retval State of bit (1 or 0). 512 */ 513 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) 514 { 515 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); 516 } 517 518 #endif /* FLASH_ACR_LATENCY */ 519 /** 520 * @brief Enable Flash Half Cycle Access 521 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess 522 * @retval None 523 */ 524 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) 525 { 526 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); 527 } 528 529 /** 530 * @brief Disable Flash Half Cycle Access 531 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess 532 * @retval None 533 */ 534 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) 535 { 536 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); 537 } 538 539 /** 540 * @brief Check if Flash Half Cycle Access is enabled or not 541 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled 542 * @retval State of bit (1 or 0). 543 */ 544 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) 545 { 546 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); 547 } 548 549 /** 550 * @} 551 */ 552 553 /** 554 * @} 555 */ 556 557 /** 558 * @} 559 */ 560 561 #endif /* defined (FLASH) || defined (DBGMCU) */ 562 563 /** 564 * @} 565 */ 566 567 #ifdef __cplusplus 568 } 569 #endif 570 571 #endif /* __STM32F1xx_LL_SYSTEM_H */ 572