Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h (75810B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F1xx_LL_DMA_H 21 #define __STM32F1xx_LL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f1xx.h" 29 30 /** @addtogroup STM32F1xx_LL_Driver 31 * @{ 32 */ 33 34 #if defined (DMA1) || defined (DMA2) 35 36 /** @defgroup DMA_LL DMA 37 * @{ 38 */ 39 40 /* Private types -------------------------------------------------------------*/ 41 /* Private variables ---------------------------------------------------------*/ 42 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 43 * @{ 44 */ 45 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ 46 static const uint8_t CHANNEL_OFFSET_TAB[] = { (uint8_t) (DMA1_Channel1_BASE 47 - DMA1_BASE), (uint8_t) (DMA1_Channel2_BASE - DMA1_BASE), 48 (uint8_t) (DMA1_Channel3_BASE - DMA1_BASE), 49 (uint8_t) (DMA1_Channel4_BASE - DMA1_BASE), 50 (uint8_t) (DMA1_Channel5_BASE - DMA1_BASE), 51 (uint8_t) (DMA1_Channel6_BASE - DMA1_BASE), 52 (uint8_t) (DMA1_Channel7_BASE - DMA1_BASE) }; 53 /** 54 * @} 55 */ 56 /* Private constants ---------------------------------------------------------*/ 57 /* Private macros ------------------------------------------------------------*/ 58 #if defined(USE_FULL_LL_DRIVER) 59 /** @defgroup DMA_LL_Private_Macros DMA Private Macros 60 * @{ 61 */ 62 /** 63 * @} 64 */ 65 #endif /*USE_FULL_LL_DRIVER*/ 66 67 /* Exported types ------------------------------------------------------------*/ 68 #if defined(USE_FULL_LL_DRIVER) 69 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 70 * @{ 71 */ 72 typedef struct 73 { 74 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 75 or as Source base address in case of memory to memory transfer direction. 76 77 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 78 79 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 80 or as Destination base address in case of memory to memory transfer direction. 81 82 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 83 84 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 85 from memory to memory or from peripheral to memory. 86 This parameter can be a value of @ref DMA_LL_EC_DIRECTION 87 88 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ 89 90 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 91 This parameter can be a value of @ref DMA_LL_EC_MODE 92 @note: The circular buffer mode cannot be used if the memory to memory 93 data transfer direction is configured on the selected Channel 94 95 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ 96 97 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 98 is incremented or not. 99 This parameter can be a value of @ref DMA_LL_EC_PERIPH 100 101 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ 102 103 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 104 is incremented or not. 105 This parameter can be a value of @ref DMA_LL_EC_MEMORY 106 107 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ 108 109 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 110 in case of memory to memory transfer direction. 111 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 112 113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ 114 115 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 116 in case of memory to memory transfer direction. 117 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 118 119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ 120 121 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 122 The data unit is equal to the source buffer configuration set in PeripheralSize 123 or MemorySize parameters depending in the transfer direction. 124 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 125 126 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ 127 128 uint32_t Priority; /*!< Specifies the channel priority level. 129 This parameter can be a value of @ref DMA_LL_EC_PRIORITY 130 131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ 132 133 }LL_DMA_InitTypeDef; 134 /** 135 * @} 136 */ 137 #endif /*USE_FULL_LL_DRIVER*/ 138 139 /* Exported constants --------------------------------------------------------*/ 140 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 141 * @{ 142 */ 143 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines 144 * @brief Flags defines which can be used with LL_DMA_WriteReg function 145 * @{ 146 */ 147 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ 148 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ 149 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ 150 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ 151 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ 152 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ 153 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ 154 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ 155 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ 156 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ 157 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ 158 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ 159 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ 160 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ 161 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ 162 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ 163 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ 164 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ 165 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ 166 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ 167 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ 168 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ 169 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ 170 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ 171 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ 172 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ 173 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ 174 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ 175 /** 176 * @} 177 */ 178 179 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines 180 * @brief Flags defines which can be used with LL_DMA_ReadReg function 181 * @{ 182 */ 183 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ 184 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 185 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 186 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 187 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ 188 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 189 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 190 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 191 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ 192 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 193 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 194 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 195 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ 196 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 197 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 198 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 199 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ 200 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 201 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 202 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 203 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ 204 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 205 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 206 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 207 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ 208 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 209 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 210 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 211 /** 212 * @} 213 */ 214 215 /** @defgroup DMA_LL_EC_IT IT Defines 216 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions 217 * @{ 218 */ 219 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ 220 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ 221 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 227 * @{ 228 */ 229 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ 230 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ 231 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ 232 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ 233 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ 234 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ 235 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ 236 #if defined(USE_FULL_LL_DRIVER) 237 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ 238 #endif /*USE_FULL_LL_DRIVER*/ 239 /** 240 * @} 241 */ 242 243 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction 244 * @{ 245 */ 246 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 247 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 248 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 249 /** 250 * @} 251 */ 252 253 /** @defgroup DMA_LL_EC_MODE Transfer mode 254 * @{ 255 */ 256 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 257 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ 258 /** 259 * @} 260 */ 261 262 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode 263 * @{ 264 */ 265 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 266 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 267 /** 268 * @} 269 */ 270 271 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode 272 * @{ 273 */ 274 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ 275 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 276 /** 277 * @} 278 */ 279 280 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment 281 * @{ 282 */ 283 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 284 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 285 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment 291 * @{ 292 */ 293 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 294 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 295 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 296 /** 297 * @} 298 */ 299 300 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level 301 * @{ 302 */ 303 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 304 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 305 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 306 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ 307 /** 308 * @} 309 */ 310 311 /** 312 * @} 313 */ 314 315 /* Exported macro ------------------------------------------------------------*/ 316 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 317 * @{ 318 */ 319 320 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 321 * @{ 322 */ 323 /** 324 * @brief Write a value in DMA register 325 * @param __INSTANCE__ DMA Instance 326 * @param __REG__ Register to be written 327 * @param __VALUE__ Value to be written in the register 328 * @retval None 329 */ 330 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 331 332 /** 333 * @brief Read a value in DMA register 334 * @param __INSTANCE__ DMA Instance 335 * @param __REG__ Register to be read 336 * @retval Register value 337 */ 338 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 339 /** 340 * @} 341 */ 342 343 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely 344 * @{ 345 */ 346 347 /** 348 * @brief Convert DMAx_Channely into DMAx 349 * @param __CHANNEL_INSTANCE__ DMAx_Channely 350 * @retval DMAx 351 */ 352 #if defined(DMA2) 353 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ 354 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) 355 #else 356 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) 357 #endif 358 359 /** 360 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y 361 * @param __CHANNEL_INSTANCE__ DMAx_Channely 362 * @retval LL_DMA_CHANNEL_y 363 */ 364 #if defined (DMA2) 365 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 366 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 367 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ 368 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 369 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ 370 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 371 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ 372 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 373 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ 374 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 375 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ 376 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 377 LL_DMA_CHANNEL_7) 378 #else 379 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 380 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 381 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 382 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 383 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 384 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 385 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 386 LL_DMA_CHANNEL_7) 387 #endif 388 389 /** 390 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely 391 * @param __DMA_INSTANCE__ DMAx 392 * @param __CHANNEL__ LL_DMA_CHANNEL_y 393 * @retval DMAx_Channely 394 */ 395 #if defined (DMA2) 396 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 397 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 398 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ 399 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 400 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ 401 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 402 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ 403 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 404 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ 405 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 406 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ 407 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 408 DMA1_Channel7) 409 #else 410 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 411 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 412 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 413 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 414 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 415 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 416 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 417 DMA1_Channel7) 418 #endif 419 420 /** 421 * @} 422 */ 423 424 /** 425 * @} 426 */ 427 428 /* Exported functions --------------------------------------------------------*/ 429 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 430 * @{ 431 */ 432 433 /** @defgroup DMA_LL_EF_Configuration Configuration 434 * @{ 435 */ 436 /** 437 * @brief Enable DMA channel. 438 * @rmtoll CCR EN LL_DMA_EnableChannel 439 * @param DMAx DMAx Instance 440 * @param Channel This parameter can be one of the following values: 441 * @arg @ref LL_DMA_CHANNEL_1 442 * @arg @ref LL_DMA_CHANNEL_2 443 * @arg @ref LL_DMA_CHANNEL_3 444 * @arg @ref LL_DMA_CHANNEL_4 445 * @arg @ref LL_DMA_CHANNEL_5 446 * @arg @ref LL_DMA_CHANNEL_6 447 * @arg @ref LL_DMA_CHANNEL_7 448 * @retval None 449 */ 450 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 451 { 452 SET_BIT( 453 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 454 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); 455 } 456 457 /** 458 * @brief Disable DMA channel. 459 * @rmtoll CCR EN LL_DMA_DisableChannel 460 * @param DMAx DMAx Instance 461 * @param Channel This parameter can be one of the following values: 462 * @arg @ref LL_DMA_CHANNEL_1 463 * @arg @ref LL_DMA_CHANNEL_2 464 * @arg @ref LL_DMA_CHANNEL_3 465 * @arg @ref LL_DMA_CHANNEL_4 466 * @arg @ref LL_DMA_CHANNEL_5 467 * @arg @ref LL_DMA_CHANNEL_6 468 * @arg @ref LL_DMA_CHANNEL_7 469 * @retval None 470 */ 471 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 472 { 473 CLEAR_BIT( 474 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 475 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); 476 } 477 478 /** 479 * @brief Check if DMA channel is enabled or disabled. 480 * @rmtoll CCR EN LL_DMA_IsEnabledChannel 481 * @param DMAx DMAx Instance 482 * @param Channel This parameter can be one of the following values: 483 * @arg @ref LL_DMA_CHANNEL_1 484 * @arg @ref LL_DMA_CHANNEL_2 485 * @arg @ref LL_DMA_CHANNEL_3 486 * @arg @ref LL_DMA_CHANNEL_4 487 * @arg @ref LL_DMA_CHANNEL_5 488 * @arg @ref LL_DMA_CHANNEL_6 489 * @arg @ref LL_DMA_CHANNEL_7 490 * @retval State of bit (1 or 0). 491 */ 492 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, 493 uint32_t Channel) 494 { 495 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 496 DMA_CCR_EN) == (DMA_CCR_EN)); 497 } 498 499 /** 500 * @brief Configure all parameters link to DMA transfer. 501 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n 502 * CCR MEM2MEM LL_DMA_ConfigTransfer\n 503 * CCR CIRC LL_DMA_ConfigTransfer\n 504 * CCR PINC LL_DMA_ConfigTransfer\n 505 * CCR MINC LL_DMA_ConfigTransfer\n 506 * CCR PSIZE LL_DMA_ConfigTransfer\n 507 * CCR MSIZE LL_DMA_ConfigTransfer\n 508 * CCR PL LL_DMA_ConfigTransfer 509 * @param DMAx DMAx Instance 510 * @param Channel This parameter can be one of the following values: 511 * @arg @ref LL_DMA_CHANNEL_1 512 * @arg @ref LL_DMA_CHANNEL_2 513 * @arg @ref LL_DMA_CHANNEL_3 514 * @arg @ref LL_DMA_CHANNEL_4 515 * @arg @ref LL_DMA_CHANNEL_5 516 * @arg @ref LL_DMA_CHANNEL_6 517 * @arg @ref LL_DMA_CHANNEL_7 518 * @param Configuration This parameter must be a combination of all the following values: 519 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 520 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR 521 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 522 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 523 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 524 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 525 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 526 * @retval None 527 */ 528 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, 529 uint32_t Configuration) 530 { 531 MODIFY_REG( 532 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 533 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 534 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, 535 Configuration); 536 } 537 538 /** 539 * @brief Set Data transfer direction (read from peripheral or from memory). 540 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n 541 * CCR MEM2MEM LL_DMA_SetDataTransferDirection 542 * @param DMAx DMAx Instance 543 * @param Channel This parameter can be one of the following values: 544 * @arg @ref LL_DMA_CHANNEL_1 545 * @arg @ref LL_DMA_CHANNEL_2 546 * @arg @ref LL_DMA_CHANNEL_3 547 * @arg @ref LL_DMA_CHANNEL_4 548 * @arg @ref LL_DMA_CHANNEL_5 549 * @arg @ref LL_DMA_CHANNEL_6 550 * @arg @ref LL_DMA_CHANNEL_7 551 * @param Direction This parameter can be one of the following values: 552 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 553 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 554 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 555 * @retval None 556 */ 557 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, 558 uint32_t Channel, uint32_t Direction) 559 { 560 MODIFY_REG( 561 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 562 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 563 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); 564 } 565 566 /** 567 * @brief Get Data transfer direction (read from peripheral or from memory). 568 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n 569 * CCR MEM2MEM LL_DMA_GetDataTransferDirection 570 * @param DMAx DMAx Instance 571 * @param Channel This parameter can be one of the following values: 572 * @arg @ref LL_DMA_CHANNEL_1 573 * @arg @ref LL_DMA_CHANNEL_2 574 * @arg @ref LL_DMA_CHANNEL_3 575 * @arg @ref LL_DMA_CHANNEL_4 576 * @arg @ref LL_DMA_CHANNEL_5 577 * @arg @ref LL_DMA_CHANNEL_6 578 * @arg @ref LL_DMA_CHANNEL_7 579 * @retval Returned value can be one of the following values: 580 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 581 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 582 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 583 */ 584 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, 585 uint32_t Channel) 586 { 587 return (READ_BIT( 588 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 589 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 590 DMA_CCR_DIR | DMA_CCR_MEM2MEM)); 591 } 592 593 /** 594 * @brief Set DMA mode circular or normal. 595 * @note The circular buffer mode cannot be used if the memory-to-memory 596 * data transfer is configured on the selected Channel. 597 * @rmtoll CCR CIRC LL_DMA_SetMode 598 * @param DMAx DMAx Instance 599 * @param Channel This parameter can be one of the following values: 600 * @arg @ref LL_DMA_CHANNEL_1 601 * @arg @ref LL_DMA_CHANNEL_2 602 * @arg @ref LL_DMA_CHANNEL_3 603 * @arg @ref LL_DMA_CHANNEL_4 604 * @arg @ref LL_DMA_CHANNEL_5 605 * @arg @ref LL_DMA_CHANNEL_6 606 * @arg @ref LL_DMA_CHANNEL_7 607 * @param Mode This parameter can be one of the following values: 608 * @arg @ref LL_DMA_MODE_NORMAL 609 * @arg @ref LL_DMA_MODE_CIRCULAR 610 * @retval None 611 */ 612 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, 613 uint32_t Mode) 614 { 615 MODIFY_REG( 616 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 617 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, 618 Mode); 619 } 620 621 /** 622 * @brief Get DMA mode circular or normal. 623 * @rmtoll CCR CIRC LL_DMA_GetMode 624 * @param DMAx DMAx Instance 625 * @param Channel This parameter can be one of the following values: 626 * @arg @ref LL_DMA_CHANNEL_1 627 * @arg @ref LL_DMA_CHANNEL_2 628 * @arg @ref LL_DMA_CHANNEL_3 629 * @arg @ref LL_DMA_CHANNEL_4 630 * @arg @ref LL_DMA_CHANNEL_5 631 * @arg @ref LL_DMA_CHANNEL_6 632 * @arg @ref LL_DMA_CHANNEL_7 633 * @retval Returned value can be one of the following values: 634 * @arg @ref LL_DMA_MODE_NORMAL 635 * @arg @ref LL_DMA_MODE_CIRCULAR 636 */ 637 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) 638 { 639 return (READ_BIT( 640 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 641 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC)); 642 } 643 644 /** 645 * @brief Set Peripheral increment mode. 646 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode 647 * @param DMAx DMAx Instance 648 * @param Channel This parameter can be one of the following values: 649 * @arg @ref LL_DMA_CHANNEL_1 650 * @arg @ref LL_DMA_CHANNEL_2 651 * @arg @ref LL_DMA_CHANNEL_3 652 * @arg @ref LL_DMA_CHANNEL_4 653 * @arg @ref LL_DMA_CHANNEL_5 654 * @arg @ref LL_DMA_CHANNEL_6 655 * @arg @ref LL_DMA_CHANNEL_7 656 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: 657 * @arg @ref LL_DMA_PERIPH_INCREMENT 658 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 659 * @retval None 660 */ 661 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, 662 uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) 663 { 664 MODIFY_REG( 665 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 666 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, 667 PeriphOrM2MSrcIncMode); 668 } 669 670 /** 671 * @brief Get Peripheral increment mode. 672 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode 673 * @param DMAx DMAx Instance 674 * @param Channel This parameter can be one of the following values: 675 * @arg @ref LL_DMA_CHANNEL_1 676 * @arg @ref LL_DMA_CHANNEL_2 677 * @arg @ref LL_DMA_CHANNEL_3 678 * @arg @ref LL_DMA_CHANNEL_4 679 * @arg @ref LL_DMA_CHANNEL_5 680 * @arg @ref LL_DMA_CHANNEL_6 681 * @arg @ref LL_DMA_CHANNEL_7 682 * @retval Returned value can be one of the following values: 683 * @arg @ref LL_DMA_PERIPH_INCREMENT 684 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 685 */ 686 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, 687 uint32_t Channel) 688 { 689 return (READ_BIT( 690 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 691 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC)); 692 } 693 694 /** 695 * @brief Set Memory increment mode. 696 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode 697 * @param DMAx DMAx Instance 698 * @param Channel This parameter can be one of the following values: 699 * @arg @ref LL_DMA_CHANNEL_1 700 * @arg @ref LL_DMA_CHANNEL_2 701 * @arg @ref LL_DMA_CHANNEL_3 702 * @arg @ref LL_DMA_CHANNEL_4 703 * @arg @ref LL_DMA_CHANNEL_5 704 * @arg @ref LL_DMA_CHANNEL_6 705 * @arg @ref LL_DMA_CHANNEL_7 706 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: 707 * @arg @ref LL_DMA_MEMORY_INCREMENT 708 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 709 * @retval None 710 */ 711 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, 712 uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) 713 { 714 MODIFY_REG( 715 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 716 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, 717 MemoryOrM2MDstIncMode); 718 } 719 720 /** 721 * @brief Get Memory increment mode. 722 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode 723 * @param DMAx DMAx Instance 724 * @param Channel This parameter can be one of the following values: 725 * @arg @ref LL_DMA_CHANNEL_1 726 * @arg @ref LL_DMA_CHANNEL_2 727 * @arg @ref LL_DMA_CHANNEL_3 728 * @arg @ref LL_DMA_CHANNEL_4 729 * @arg @ref LL_DMA_CHANNEL_5 730 * @arg @ref LL_DMA_CHANNEL_6 731 * @arg @ref LL_DMA_CHANNEL_7 732 * @retval Returned value can be one of the following values: 733 * @arg @ref LL_DMA_MEMORY_INCREMENT 734 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 735 */ 736 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, 737 uint32_t Channel) 738 { 739 return (READ_BIT( 740 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 741 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC)); 742 } 743 744 /** 745 * @brief Set Peripheral size. 746 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize 747 * @param DMAx DMAx Instance 748 * @param Channel This parameter can be one of the following values: 749 * @arg @ref LL_DMA_CHANNEL_1 750 * @arg @ref LL_DMA_CHANNEL_2 751 * @arg @ref LL_DMA_CHANNEL_3 752 * @arg @ref LL_DMA_CHANNEL_4 753 * @arg @ref LL_DMA_CHANNEL_5 754 * @arg @ref LL_DMA_CHANNEL_6 755 * @arg @ref LL_DMA_CHANNEL_7 756 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: 757 * @arg @ref LL_DMA_PDATAALIGN_BYTE 758 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 759 * @arg @ref LL_DMA_PDATAALIGN_WORD 760 * @retval None 761 */ 762 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, 763 uint32_t PeriphOrM2MSrcDataSize) 764 { 765 MODIFY_REG( 766 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 767 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, 768 PeriphOrM2MSrcDataSize); 769 } 770 771 /** 772 * @brief Get Peripheral size. 773 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize 774 * @param DMAx DMAx Instance 775 * @param Channel This parameter can be one of the following values: 776 * @arg @ref LL_DMA_CHANNEL_1 777 * @arg @ref LL_DMA_CHANNEL_2 778 * @arg @ref LL_DMA_CHANNEL_3 779 * @arg @ref LL_DMA_CHANNEL_4 780 * @arg @ref LL_DMA_CHANNEL_5 781 * @arg @ref LL_DMA_CHANNEL_6 782 * @arg @ref LL_DMA_CHANNEL_7 783 * @retval Returned value can be one of the following values: 784 * @arg @ref LL_DMA_PDATAALIGN_BYTE 785 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 786 * @arg @ref LL_DMA_PDATAALIGN_WORD 787 */ 788 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, 789 uint32_t Channel) 790 { 791 return (READ_BIT( 792 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 793 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE)); 794 } 795 796 /** 797 * @brief Set Memory size. 798 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize 799 * @param DMAx DMAx Instance 800 * @param Channel This parameter can be one of the following values: 801 * @arg @ref LL_DMA_CHANNEL_1 802 * @arg @ref LL_DMA_CHANNEL_2 803 * @arg @ref LL_DMA_CHANNEL_3 804 * @arg @ref LL_DMA_CHANNEL_4 805 * @arg @ref LL_DMA_CHANNEL_5 806 * @arg @ref LL_DMA_CHANNEL_6 807 * @arg @ref LL_DMA_CHANNEL_7 808 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: 809 * @arg @ref LL_DMA_MDATAALIGN_BYTE 810 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 811 * @arg @ref LL_DMA_MDATAALIGN_WORD 812 * @retval None 813 */ 814 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, 815 uint32_t MemoryOrM2MDstDataSize) 816 { 817 MODIFY_REG( 818 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 819 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, 820 MemoryOrM2MDstDataSize); 821 } 822 823 /** 824 * @brief Get Memory size. 825 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize 826 * @param DMAx DMAx Instance 827 * @param Channel This parameter can be one of the following values: 828 * @arg @ref LL_DMA_CHANNEL_1 829 * @arg @ref LL_DMA_CHANNEL_2 830 * @arg @ref LL_DMA_CHANNEL_3 831 * @arg @ref LL_DMA_CHANNEL_4 832 * @arg @ref LL_DMA_CHANNEL_5 833 * @arg @ref LL_DMA_CHANNEL_6 834 * @arg @ref LL_DMA_CHANNEL_7 835 * @retval Returned value can be one of the following values: 836 * @arg @ref LL_DMA_MDATAALIGN_BYTE 837 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 838 * @arg @ref LL_DMA_MDATAALIGN_WORD 839 */ 840 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, 841 uint32_t Channel) 842 { 843 return (READ_BIT( 844 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 845 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE)); 846 } 847 848 /** 849 * @brief Set Channel priority level. 850 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel 851 * @param DMAx DMAx Instance 852 * @param Channel This parameter can be one of the following values: 853 * @arg @ref LL_DMA_CHANNEL_1 854 * @arg @ref LL_DMA_CHANNEL_2 855 * @arg @ref LL_DMA_CHANNEL_3 856 * @arg @ref LL_DMA_CHANNEL_4 857 * @arg @ref LL_DMA_CHANNEL_5 858 * @arg @ref LL_DMA_CHANNEL_6 859 * @arg @ref LL_DMA_CHANNEL_7 860 * @param Priority This parameter can be one of the following values: 861 * @arg @ref LL_DMA_PRIORITY_LOW 862 * @arg @ref LL_DMA_PRIORITY_MEDIUM 863 * @arg @ref LL_DMA_PRIORITY_HIGH 864 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 865 * @retval None 866 */ 867 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, 868 uint32_t Channel, uint32_t Priority) 869 { 870 MODIFY_REG( 871 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 872 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, 873 Priority); 874 } 875 876 /** 877 * @brief Get Channel priority level. 878 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel 879 * @param DMAx DMAx Instance 880 * @param Channel This parameter can be one of the following values: 881 * @arg @ref LL_DMA_CHANNEL_1 882 * @arg @ref LL_DMA_CHANNEL_2 883 * @arg @ref LL_DMA_CHANNEL_3 884 * @arg @ref LL_DMA_CHANNEL_4 885 * @arg @ref LL_DMA_CHANNEL_5 886 * @arg @ref LL_DMA_CHANNEL_6 887 * @arg @ref LL_DMA_CHANNEL_7 888 * @retval Returned value can be one of the following values: 889 * @arg @ref LL_DMA_PRIORITY_LOW 890 * @arg @ref LL_DMA_PRIORITY_MEDIUM 891 * @arg @ref LL_DMA_PRIORITY_HIGH 892 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 893 */ 894 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, 895 uint32_t Channel) 896 { 897 return (READ_BIT( 898 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 899 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL)); 900 } 901 902 /** 903 * @brief Set Number of data to transfer. 904 * @note This action has no effect if 905 * channel is enabled. 906 * @rmtoll CNDTR NDT LL_DMA_SetDataLength 907 * @param DMAx DMAx Instance 908 * @param Channel This parameter can be one of the following values: 909 * @arg @ref LL_DMA_CHANNEL_1 910 * @arg @ref LL_DMA_CHANNEL_2 911 * @arg @ref LL_DMA_CHANNEL_3 912 * @arg @ref LL_DMA_CHANNEL_4 913 * @arg @ref LL_DMA_CHANNEL_5 914 * @arg @ref LL_DMA_CHANNEL_6 915 * @arg @ref LL_DMA_CHANNEL_7 916 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF 917 * @retval None 918 */ 919 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, 920 uint32_t NbData) 921 { 922 MODIFY_REG( 923 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 924 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, DMA_CNDTR_NDT, 925 NbData); 926 } 927 928 /** 929 * @brief Get Number of data to transfer. 930 * @note Once the channel is enabled, the return value indicate the 931 * remaining bytes to be transmitted. 932 * @rmtoll CNDTR NDT LL_DMA_GetDataLength 933 * @param DMAx DMAx Instance 934 * @param Channel This parameter can be one of the following values: 935 * @arg @ref LL_DMA_CHANNEL_1 936 * @arg @ref LL_DMA_CHANNEL_2 937 * @arg @ref LL_DMA_CHANNEL_3 938 * @arg @ref LL_DMA_CHANNEL_4 939 * @arg @ref LL_DMA_CHANNEL_5 940 * @arg @ref LL_DMA_CHANNEL_6 941 * @arg @ref LL_DMA_CHANNEL_7 942 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 943 */ 944 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, 945 uint32_t Channel) 946 { 947 return (READ_BIT( 948 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 949 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, DMA_CNDTR_NDT)); 950 } 951 952 /** 953 * @brief Configure the Source and Destination addresses. 954 * @note This API must not be called when the DMA channel is enabled. 955 * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). 956 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n 957 * CMAR MA LL_DMA_ConfigAddresses 958 * @param DMAx DMAx Instance 959 * @param Channel This parameter can be one of the following values: 960 * @arg @ref LL_DMA_CHANNEL_1 961 * @arg @ref LL_DMA_CHANNEL_2 962 * @arg @ref LL_DMA_CHANNEL_3 963 * @arg @ref LL_DMA_CHANNEL_4 964 * @arg @ref LL_DMA_CHANNEL_5 965 * @arg @ref LL_DMA_CHANNEL_6 966 * @arg @ref LL_DMA_CHANNEL_7 967 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 968 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 969 * @param Direction This parameter can be one of the following values: 970 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 971 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 972 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 973 * @retval None 974 */ 975 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, 976 uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) 977 { 978 /* Direction Memory to Periph */ 979 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) { 980 WRITE_REG( 981 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 982 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, 983 SrcAddress); 984 WRITE_REG( 985 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 986 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, 987 DstAddress); 988 } 989 /* Direction Periph to Memory and Memory to Memory */ 990 else { 991 WRITE_REG( 992 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 993 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, 994 SrcAddress); 995 WRITE_REG( 996 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 997 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, 998 DstAddress); 999 } 1000 } 1001 1002 /** 1003 * @brief Set the Memory address. 1004 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1005 * @note This API must not be called when the DMA channel is enabled. 1006 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress 1007 * @param DMAx DMAx Instance 1008 * @param Channel This parameter can be one of the following values: 1009 * @arg @ref LL_DMA_CHANNEL_1 1010 * @arg @ref LL_DMA_CHANNEL_2 1011 * @arg @ref LL_DMA_CHANNEL_3 1012 * @arg @ref LL_DMA_CHANNEL_4 1013 * @arg @ref LL_DMA_CHANNEL_5 1014 * @arg @ref LL_DMA_CHANNEL_6 1015 * @arg @ref LL_DMA_CHANNEL_7 1016 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1017 * @retval None 1018 */ 1019 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, 1020 uint32_t Channel, uint32_t MemoryAddress) 1021 { 1022 WRITE_REG( 1023 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1024 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); 1025 } 1026 1027 /** 1028 * @brief Set the Peripheral address. 1029 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1030 * @note This API must not be called when the DMA channel is enabled. 1031 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress 1032 * @param DMAx DMAx Instance 1033 * @param Channel This parameter can be one of the following values: 1034 * @arg @ref LL_DMA_CHANNEL_1 1035 * @arg @ref LL_DMA_CHANNEL_2 1036 * @arg @ref LL_DMA_CHANNEL_3 1037 * @arg @ref LL_DMA_CHANNEL_4 1038 * @arg @ref LL_DMA_CHANNEL_5 1039 * @arg @ref LL_DMA_CHANNEL_6 1040 * @arg @ref LL_DMA_CHANNEL_7 1041 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1042 * @retval None 1043 */ 1044 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, 1045 uint32_t Channel, uint32_t PeriphAddress) 1046 { 1047 WRITE_REG( 1048 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1049 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); 1050 } 1051 1052 /** 1053 * @brief Get Memory address. 1054 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1055 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress 1056 * @param DMAx DMAx Instance 1057 * @param Channel This parameter can be one of the following values: 1058 * @arg @ref LL_DMA_CHANNEL_1 1059 * @arg @ref LL_DMA_CHANNEL_2 1060 * @arg @ref LL_DMA_CHANNEL_3 1061 * @arg @ref LL_DMA_CHANNEL_4 1062 * @arg @ref LL_DMA_CHANNEL_5 1063 * @arg @ref LL_DMA_CHANNEL_6 1064 * @arg @ref LL_DMA_CHANNEL_7 1065 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1066 */ 1067 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, 1068 uint32_t Channel) 1069 { 1070 return (READ_REG( 1071 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1072 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); 1073 } 1074 1075 /** 1076 * @brief Get Peripheral address. 1077 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 1078 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress 1079 * @param DMAx DMAx Instance 1080 * @param Channel This parameter can be one of the following values: 1081 * @arg @ref LL_DMA_CHANNEL_1 1082 * @arg @ref LL_DMA_CHANNEL_2 1083 * @arg @ref LL_DMA_CHANNEL_3 1084 * @arg @ref LL_DMA_CHANNEL_4 1085 * @arg @ref LL_DMA_CHANNEL_5 1086 * @arg @ref LL_DMA_CHANNEL_6 1087 * @arg @ref LL_DMA_CHANNEL_7 1088 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1089 */ 1090 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, 1091 uint32_t Channel) 1092 { 1093 return (READ_REG( 1094 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1095 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); 1096 } 1097 1098 /** 1099 * @brief Set the Memory to Memory Source address. 1100 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1101 * @note This API must not be called when the DMA channel is enabled. 1102 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress 1103 * @param DMAx DMAx Instance 1104 * @param Channel This parameter can be one of the following values: 1105 * @arg @ref LL_DMA_CHANNEL_1 1106 * @arg @ref LL_DMA_CHANNEL_2 1107 * @arg @ref LL_DMA_CHANNEL_3 1108 * @arg @ref LL_DMA_CHANNEL_4 1109 * @arg @ref LL_DMA_CHANNEL_5 1110 * @arg @ref LL_DMA_CHANNEL_6 1111 * @arg @ref LL_DMA_CHANNEL_7 1112 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1113 * @retval None 1114 */ 1115 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, 1116 uint32_t Channel, uint32_t MemoryAddress) 1117 { 1118 WRITE_REG( 1119 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1120 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); 1121 } 1122 1123 /** 1124 * @brief Set the Memory to Memory Destination address. 1125 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1126 * @note This API must not be called when the DMA channel is enabled. 1127 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress 1128 * @param DMAx DMAx Instance 1129 * @param Channel This parameter can be one of the following values: 1130 * @arg @ref LL_DMA_CHANNEL_1 1131 * @arg @ref LL_DMA_CHANNEL_2 1132 * @arg @ref LL_DMA_CHANNEL_3 1133 * @arg @ref LL_DMA_CHANNEL_4 1134 * @arg @ref LL_DMA_CHANNEL_5 1135 * @arg @ref LL_DMA_CHANNEL_6 1136 * @arg @ref LL_DMA_CHANNEL_7 1137 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1138 * @retval None 1139 */ 1140 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, 1141 uint32_t Channel, uint32_t MemoryAddress) 1142 { 1143 WRITE_REG( 1144 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1145 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); 1146 } 1147 1148 /** 1149 * @brief Get the Memory to Memory Source address. 1150 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1151 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress 1152 * @param DMAx DMAx Instance 1153 * @param Channel This parameter can be one of the following values: 1154 * @arg @ref LL_DMA_CHANNEL_1 1155 * @arg @ref LL_DMA_CHANNEL_2 1156 * @arg @ref LL_DMA_CHANNEL_3 1157 * @arg @ref LL_DMA_CHANNEL_4 1158 * @arg @ref LL_DMA_CHANNEL_5 1159 * @arg @ref LL_DMA_CHANNEL_6 1160 * @arg @ref LL_DMA_CHANNEL_7 1161 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1162 */ 1163 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, 1164 uint32_t Channel) 1165 { 1166 return (READ_REG( 1167 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1168 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); 1169 } 1170 1171 /** 1172 * @brief Get the Memory to Memory Destination address. 1173 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 1174 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress 1175 * @param DMAx DMAx Instance 1176 * @param Channel This parameter can be one of the following values: 1177 * @arg @ref LL_DMA_CHANNEL_1 1178 * @arg @ref LL_DMA_CHANNEL_2 1179 * @arg @ref LL_DMA_CHANNEL_3 1180 * @arg @ref LL_DMA_CHANNEL_4 1181 * @arg @ref LL_DMA_CHANNEL_5 1182 * @arg @ref LL_DMA_CHANNEL_6 1183 * @arg @ref LL_DMA_CHANNEL_7 1184 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 1185 */ 1186 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, 1187 uint32_t Channel) 1188 { 1189 return (READ_REG( 1190 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1191 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); 1192 } 1193 1194 /** 1195 * @} 1196 */ 1197 1198 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 1199 * @{ 1200 */ 1201 1202 /** 1203 * @brief Get Channel 1 global interrupt flag. 1204 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 1205 * @param DMAx DMAx Instance 1206 * @retval State of bit (1 or 0). 1207 */ 1208 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) 1209 { 1210 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); 1211 } 1212 1213 /** 1214 * @brief Get Channel 2 global interrupt flag. 1215 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 1216 * @param DMAx DMAx Instance 1217 * @retval State of bit (1 or 0). 1218 */ 1219 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) 1220 { 1221 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); 1222 } 1223 1224 /** 1225 * @brief Get Channel 3 global interrupt flag. 1226 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 1227 * @param DMAx DMAx Instance 1228 * @retval State of bit (1 or 0). 1229 */ 1230 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) 1231 { 1232 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); 1233 } 1234 1235 /** 1236 * @brief Get Channel 4 global interrupt flag. 1237 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 1238 * @param DMAx DMAx Instance 1239 * @retval State of bit (1 or 0). 1240 */ 1241 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) 1242 { 1243 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); 1244 } 1245 1246 /** 1247 * @brief Get Channel 5 global interrupt flag. 1248 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 1249 * @param DMAx DMAx Instance 1250 * @retval State of bit (1 or 0). 1251 */ 1252 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) 1253 { 1254 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); 1255 } 1256 1257 /** 1258 * @brief Get Channel 6 global interrupt flag. 1259 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 1260 * @param DMAx DMAx Instance 1261 * @retval State of bit (1 or 0). 1262 */ 1263 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) 1264 { 1265 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); 1266 } 1267 1268 /** 1269 * @brief Get Channel 7 global interrupt flag. 1270 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 1271 * @param DMAx DMAx Instance 1272 * @retval State of bit (1 or 0). 1273 */ 1274 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) 1275 { 1276 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); 1277 } 1278 1279 /** 1280 * @brief Get Channel 1 transfer complete flag. 1281 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 1282 * @param DMAx DMAx Instance 1283 * @retval State of bit (1 or 0). 1284 */ 1285 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 1286 { 1287 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); 1288 } 1289 1290 /** 1291 * @brief Get Channel 2 transfer complete flag. 1292 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 1293 * @param DMAx DMAx Instance 1294 * @retval State of bit (1 or 0). 1295 */ 1296 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 1297 { 1298 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); 1299 } 1300 1301 /** 1302 * @brief Get Channel 3 transfer complete flag. 1303 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 1304 * @param DMAx DMAx Instance 1305 * @retval State of bit (1 or 0). 1306 */ 1307 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 1308 { 1309 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); 1310 } 1311 1312 /** 1313 * @brief Get Channel 4 transfer complete flag. 1314 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 1315 * @param DMAx DMAx Instance 1316 * @retval State of bit (1 or 0). 1317 */ 1318 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 1319 { 1320 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); 1321 } 1322 1323 /** 1324 * @brief Get Channel 5 transfer complete flag. 1325 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 1326 * @param DMAx DMAx Instance 1327 * @retval State of bit (1 or 0). 1328 */ 1329 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 1330 { 1331 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); 1332 } 1333 1334 /** 1335 * @brief Get Channel 6 transfer complete flag. 1336 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 1337 * @param DMAx DMAx Instance 1338 * @retval State of bit (1 or 0). 1339 */ 1340 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 1341 { 1342 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); 1343 } 1344 1345 /** 1346 * @brief Get Channel 7 transfer complete flag. 1347 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 1348 * @param DMAx DMAx Instance 1349 * @retval State of bit (1 or 0). 1350 */ 1351 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 1352 { 1353 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); 1354 } 1355 1356 /** 1357 * @brief Get Channel 1 half transfer flag. 1358 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 1359 * @param DMAx DMAx Instance 1360 * @retval State of bit (1 or 0). 1361 */ 1362 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 1363 { 1364 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); 1365 } 1366 1367 /** 1368 * @brief Get Channel 2 half transfer flag. 1369 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 1370 * @param DMAx DMAx Instance 1371 * @retval State of bit (1 or 0). 1372 */ 1373 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 1374 { 1375 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); 1376 } 1377 1378 /** 1379 * @brief Get Channel 3 half transfer flag. 1380 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 1381 * @param DMAx DMAx Instance 1382 * @retval State of bit (1 or 0). 1383 */ 1384 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 1385 { 1386 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); 1387 } 1388 1389 /** 1390 * @brief Get Channel 4 half transfer flag. 1391 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 1392 * @param DMAx DMAx Instance 1393 * @retval State of bit (1 or 0). 1394 */ 1395 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 1396 { 1397 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); 1398 } 1399 1400 /** 1401 * @brief Get Channel 5 half transfer flag. 1402 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 1403 * @param DMAx DMAx Instance 1404 * @retval State of bit (1 or 0). 1405 */ 1406 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 1407 { 1408 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); 1409 } 1410 1411 /** 1412 * @brief Get Channel 6 half transfer flag. 1413 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 1414 * @param DMAx DMAx Instance 1415 * @retval State of bit (1 or 0). 1416 */ 1417 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 1418 { 1419 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); 1420 } 1421 1422 /** 1423 * @brief Get Channel 7 half transfer flag. 1424 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 1425 * @param DMAx DMAx Instance 1426 * @retval State of bit (1 or 0). 1427 */ 1428 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 1429 { 1430 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); 1431 } 1432 1433 /** 1434 * @brief Get Channel 1 transfer error flag. 1435 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 1436 * @param DMAx DMAx Instance 1437 * @retval State of bit (1 or 0). 1438 */ 1439 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 1440 { 1441 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); 1442 } 1443 1444 /** 1445 * @brief Get Channel 2 transfer error flag. 1446 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 1447 * @param DMAx DMAx Instance 1448 * @retval State of bit (1 or 0). 1449 */ 1450 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 1451 { 1452 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); 1453 } 1454 1455 /** 1456 * @brief Get Channel 3 transfer error flag. 1457 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 1458 * @param DMAx DMAx Instance 1459 * @retval State of bit (1 or 0). 1460 */ 1461 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 1462 { 1463 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); 1464 } 1465 1466 /** 1467 * @brief Get Channel 4 transfer error flag. 1468 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 1469 * @param DMAx DMAx Instance 1470 * @retval State of bit (1 or 0). 1471 */ 1472 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 1473 { 1474 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); 1475 } 1476 1477 /** 1478 * @brief Get Channel 5 transfer error flag. 1479 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 1480 * @param DMAx DMAx Instance 1481 * @retval State of bit (1 or 0). 1482 */ 1483 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 1484 { 1485 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); 1486 } 1487 1488 /** 1489 * @brief Get Channel 6 transfer error flag. 1490 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 1491 * @param DMAx DMAx Instance 1492 * @retval State of bit (1 or 0). 1493 */ 1494 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 1495 { 1496 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); 1497 } 1498 1499 /** 1500 * @brief Get Channel 7 transfer error flag. 1501 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 1502 * @param DMAx DMAx Instance 1503 * @retval State of bit (1 or 0). 1504 */ 1505 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 1506 { 1507 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); 1508 } 1509 1510 /** 1511 * @brief Clear Channel 1 global interrupt flag. 1512 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 1513 * @param DMAx DMAx Instance 1514 * @retval None 1515 */ 1516 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) 1517 { 1518 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); 1519 } 1520 1521 /** 1522 * @brief Clear Channel 2 global interrupt flag. 1523 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 1524 * @param DMAx DMAx Instance 1525 * @retval None 1526 */ 1527 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) 1528 { 1529 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); 1530 } 1531 1532 /** 1533 * @brief Clear Channel 3 global interrupt flag. 1534 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 1535 * @param DMAx DMAx Instance 1536 * @retval None 1537 */ 1538 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) 1539 { 1540 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); 1541 } 1542 1543 /** 1544 * @brief Clear Channel 4 global interrupt flag. 1545 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 1546 * @param DMAx DMAx Instance 1547 * @retval None 1548 */ 1549 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) 1550 { 1551 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); 1552 } 1553 1554 /** 1555 * @brief Clear Channel 5 global interrupt flag. 1556 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 1557 * @param DMAx DMAx Instance 1558 * @retval None 1559 */ 1560 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) 1561 { 1562 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); 1563 } 1564 1565 /** 1566 * @brief Clear Channel 6 global interrupt flag. 1567 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 1568 * @param DMAx DMAx Instance 1569 * @retval None 1570 */ 1571 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) 1572 { 1573 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); 1574 } 1575 1576 /** 1577 * @brief Clear Channel 7 global interrupt flag. 1578 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 1579 * @param DMAx DMAx Instance 1580 * @retval None 1581 */ 1582 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) 1583 { 1584 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); 1585 } 1586 1587 /** 1588 * @brief Clear Channel 1 transfer complete flag. 1589 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 1590 * @param DMAx DMAx Instance 1591 * @retval None 1592 */ 1593 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 1594 { 1595 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); 1596 } 1597 1598 /** 1599 * @brief Clear Channel 2 transfer complete flag. 1600 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 1601 * @param DMAx DMAx Instance 1602 * @retval None 1603 */ 1604 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 1605 { 1606 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); 1607 } 1608 1609 /** 1610 * @brief Clear Channel 3 transfer complete flag. 1611 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 1612 * @param DMAx DMAx Instance 1613 * @retval None 1614 */ 1615 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 1616 { 1617 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); 1618 } 1619 1620 /** 1621 * @brief Clear Channel 4 transfer complete flag. 1622 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 1623 * @param DMAx DMAx Instance 1624 * @retval None 1625 */ 1626 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 1627 { 1628 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); 1629 } 1630 1631 /** 1632 * @brief Clear Channel 5 transfer complete flag. 1633 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 1634 * @param DMAx DMAx Instance 1635 * @retval None 1636 */ 1637 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 1638 { 1639 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); 1640 } 1641 1642 /** 1643 * @brief Clear Channel 6 transfer complete flag. 1644 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 1645 * @param DMAx DMAx Instance 1646 * @retval None 1647 */ 1648 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 1649 { 1650 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); 1651 } 1652 1653 /** 1654 * @brief Clear Channel 7 transfer complete flag. 1655 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 1656 * @param DMAx DMAx Instance 1657 * @retval None 1658 */ 1659 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 1660 { 1661 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); 1662 } 1663 1664 /** 1665 * @brief Clear Channel 1 half transfer flag. 1666 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 1667 * @param DMAx DMAx Instance 1668 * @retval None 1669 */ 1670 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 1671 { 1672 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); 1673 } 1674 1675 /** 1676 * @brief Clear Channel 2 half transfer flag. 1677 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 1678 * @param DMAx DMAx Instance 1679 * @retval None 1680 */ 1681 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 1682 { 1683 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); 1684 } 1685 1686 /** 1687 * @brief Clear Channel 3 half transfer flag. 1688 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 1689 * @param DMAx DMAx Instance 1690 * @retval None 1691 */ 1692 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 1693 { 1694 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); 1695 } 1696 1697 /** 1698 * @brief Clear Channel 4 half transfer flag. 1699 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 1700 * @param DMAx DMAx Instance 1701 * @retval None 1702 */ 1703 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 1704 { 1705 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); 1706 } 1707 1708 /** 1709 * @brief Clear Channel 5 half transfer flag. 1710 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 1711 * @param DMAx DMAx Instance 1712 * @retval None 1713 */ 1714 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 1715 { 1716 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); 1717 } 1718 1719 /** 1720 * @brief Clear Channel 6 half transfer flag. 1721 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 1722 * @param DMAx DMAx Instance 1723 * @retval None 1724 */ 1725 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 1726 { 1727 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); 1728 } 1729 1730 /** 1731 * @brief Clear Channel 7 half transfer flag. 1732 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 1733 * @param DMAx DMAx Instance 1734 * @retval None 1735 */ 1736 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 1737 { 1738 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); 1739 } 1740 1741 /** 1742 * @brief Clear Channel 1 transfer error flag. 1743 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 1744 * @param DMAx DMAx Instance 1745 * @retval None 1746 */ 1747 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 1748 { 1749 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); 1750 } 1751 1752 /** 1753 * @brief Clear Channel 2 transfer error flag. 1754 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 1755 * @param DMAx DMAx Instance 1756 * @retval None 1757 */ 1758 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 1759 { 1760 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); 1761 } 1762 1763 /** 1764 * @brief Clear Channel 3 transfer error flag. 1765 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 1766 * @param DMAx DMAx Instance 1767 * @retval None 1768 */ 1769 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 1770 { 1771 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); 1772 } 1773 1774 /** 1775 * @brief Clear Channel 4 transfer error flag. 1776 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 1777 * @param DMAx DMAx Instance 1778 * @retval None 1779 */ 1780 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 1781 { 1782 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); 1783 } 1784 1785 /** 1786 * @brief Clear Channel 5 transfer error flag. 1787 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 1788 * @param DMAx DMAx Instance 1789 * @retval None 1790 */ 1791 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 1792 { 1793 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); 1794 } 1795 1796 /** 1797 * @brief Clear Channel 6 transfer error flag. 1798 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 1799 * @param DMAx DMAx Instance 1800 * @retval None 1801 */ 1802 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 1803 { 1804 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); 1805 } 1806 1807 /** 1808 * @brief Clear Channel 7 transfer error flag. 1809 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 1810 * @param DMAx DMAx Instance 1811 * @retval None 1812 */ 1813 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 1814 { 1815 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); 1816 } 1817 1818 /** 1819 * @} 1820 */ 1821 1822 /** @defgroup DMA_LL_EF_IT_Management IT_Management 1823 * @{ 1824 */ 1825 1826 /** 1827 * @brief Enable Transfer complete interrupt. 1828 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC 1829 * @param DMAx DMAx Instance 1830 * @param Channel This parameter can be one of the following values: 1831 * @arg @ref LL_DMA_CHANNEL_1 1832 * @arg @ref LL_DMA_CHANNEL_2 1833 * @arg @ref LL_DMA_CHANNEL_3 1834 * @arg @ref LL_DMA_CHANNEL_4 1835 * @arg @ref LL_DMA_CHANNEL_5 1836 * @arg @ref LL_DMA_CHANNEL_6 1837 * @arg @ref LL_DMA_CHANNEL_7 1838 * @retval None 1839 */ 1840 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 1841 { 1842 SET_BIT( 1843 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1844 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); 1845 } 1846 1847 /** 1848 * @brief Enable Half transfer interrupt. 1849 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT 1850 * @param DMAx DMAx Instance 1851 * @param Channel This parameter can be one of the following values: 1852 * @arg @ref LL_DMA_CHANNEL_1 1853 * @arg @ref LL_DMA_CHANNEL_2 1854 * @arg @ref LL_DMA_CHANNEL_3 1855 * @arg @ref LL_DMA_CHANNEL_4 1856 * @arg @ref LL_DMA_CHANNEL_5 1857 * @arg @ref LL_DMA_CHANNEL_6 1858 * @arg @ref LL_DMA_CHANNEL_7 1859 * @retval None 1860 */ 1861 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 1862 { 1863 SET_BIT( 1864 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1865 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); 1866 } 1867 1868 /** 1869 * @brief Enable Transfer error interrupt. 1870 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE 1871 * @param DMAx DMAx Instance 1872 * @param Channel This parameter can be one of the following values: 1873 * @arg @ref LL_DMA_CHANNEL_1 1874 * @arg @ref LL_DMA_CHANNEL_2 1875 * @arg @ref LL_DMA_CHANNEL_3 1876 * @arg @ref LL_DMA_CHANNEL_4 1877 * @arg @ref LL_DMA_CHANNEL_5 1878 * @arg @ref LL_DMA_CHANNEL_6 1879 * @arg @ref LL_DMA_CHANNEL_7 1880 * @retval None 1881 */ 1882 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 1883 { 1884 SET_BIT( 1885 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1886 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); 1887 } 1888 1889 /** 1890 * @brief Disable Transfer complete interrupt. 1891 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC 1892 * @param DMAx DMAx Instance 1893 * @param Channel This parameter can be one of the following values: 1894 * @arg @ref LL_DMA_CHANNEL_1 1895 * @arg @ref LL_DMA_CHANNEL_2 1896 * @arg @ref LL_DMA_CHANNEL_3 1897 * @arg @ref LL_DMA_CHANNEL_4 1898 * @arg @ref LL_DMA_CHANNEL_5 1899 * @arg @ref LL_DMA_CHANNEL_6 1900 * @arg @ref LL_DMA_CHANNEL_7 1901 * @retval None 1902 */ 1903 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 1904 { 1905 CLEAR_BIT( 1906 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1907 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); 1908 } 1909 1910 /** 1911 * @brief Disable Half transfer interrupt. 1912 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT 1913 * @param DMAx DMAx Instance 1914 * @param Channel This parameter can be one of the following values: 1915 * @arg @ref LL_DMA_CHANNEL_1 1916 * @arg @ref LL_DMA_CHANNEL_2 1917 * @arg @ref LL_DMA_CHANNEL_3 1918 * @arg @ref LL_DMA_CHANNEL_4 1919 * @arg @ref LL_DMA_CHANNEL_5 1920 * @arg @ref LL_DMA_CHANNEL_6 1921 * @arg @ref LL_DMA_CHANNEL_7 1922 * @retval None 1923 */ 1924 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 1925 { 1926 CLEAR_BIT( 1927 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1928 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); 1929 } 1930 1931 /** 1932 * @brief Disable Transfer error interrupt. 1933 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE 1934 * @param DMAx DMAx Instance 1935 * @param Channel This parameter can be one of the following values: 1936 * @arg @ref LL_DMA_CHANNEL_1 1937 * @arg @ref LL_DMA_CHANNEL_2 1938 * @arg @ref LL_DMA_CHANNEL_3 1939 * @arg @ref LL_DMA_CHANNEL_4 1940 * @arg @ref LL_DMA_CHANNEL_5 1941 * @arg @ref LL_DMA_CHANNEL_6 1942 * @arg @ref LL_DMA_CHANNEL_7 1943 * @retval None 1944 */ 1945 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 1946 { 1947 CLEAR_BIT( 1948 ((DMA_Channel_TypeDef* )((uint32_t )((uint32_t )DMAx 1949 + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); 1950 } 1951 1952 /** 1953 * @brief Check if Transfer complete Interrupt is enabled. 1954 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC 1955 * @param DMAx DMAx Instance 1956 * @param Channel This parameter can be one of the following values: 1957 * @arg @ref LL_DMA_CHANNEL_1 1958 * @arg @ref LL_DMA_CHANNEL_2 1959 * @arg @ref LL_DMA_CHANNEL_3 1960 * @arg @ref LL_DMA_CHANNEL_4 1961 * @arg @ref LL_DMA_CHANNEL_5 1962 * @arg @ref LL_DMA_CHANNEL_6 1963 * @arg @ref LL_DMA_CHANNEL_7 1964 * @retval State of bit (1 or 0). 1965 */ 1966 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, 1967 uint32_t Channel) 1968 { 1969 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 1970 DMA_CCR_TCIE) == (DMA_CCR_TCIE)); 1971 } 1972 1973 /** 1974 * @brief Check if Half transfer Interrupt is enabled. 1975 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT 1976 * @param DMAx DMAx Instance 1977 * @param Channel This parameter can be one of the following values: 1978 * @arg @ref LL_DMA_CHANNEL_1 1979 * @arg @ref LL_DMA_CHANNEL_2 1980 * @arg @ref LL_DMA_CHANNEL_3 1981 * @arg @ref LL_DMA_CHANNEL_4 1982 * @arg @ref LL_DMA_CHANNEL_5 1983 * @arg @ref LL_DMA_CHANNEL_6 1984 * @arg @ref LL_DMA_CHANNEL_7 1985 * @retval State of bit (1 or 0). 1986 */ 1987 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, 1988 uint32_t Channel) 1989 { 1990 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 1991 DMA_CCR_HTIE) == (DMA_CCR_HTIE)); 1992 } 1993 1994 /** 1995 * @brief Check if Transfer error Interrupt is enabled. 1996 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE 1997 * @param DMAx DMAx Instance 1998 * @param Channel This parameter can be one of the following values: 1999 * @arg @ref LL_DMA_CHANNEL_1 2000 * @arg @ref LL_DMA_CHANNEL_2 2001 * @arg @ref LL_DMA_CHANNEL_3 2002 * @arg @ref LL_DMA_CHANNEL_4 2003 * @arg @ref LL_DMA_CHANNEL_5 2004 * @arg @ref LL_DMA_CHANNEL_6 2005 * @arg @ref LL_DMA_CHANNEL_7 2006 * @retval State of bit (1 or 0). 2007 */ 2008 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, 2009 uint32_t Channel) 2010 { 2011 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 2012 DMA_CCR_TEIE) == (DMA_CCR_TEIE)); 2013 } 2014 2015 /** 2016 * @} 2017 */ 2018 2019 #if defined(USE_FULL_LL_DRIVER) 2020 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions 2021 * @{ 2022 */ 2023 2024 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); 2025 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); 2026 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); 2027 2028 /** 2029 * @} 2030 */ 2031 #endif /* USE_FULL_LL_DRIVER */ 2032 2033 /** 2034 * @} 2035 */ 2036 2037 /** 2038 * @} 2039 */ 2040 2041 #endif /* DMA1 || DMA2 */ 2042 2043 /** 2044 * @} 2045 */ 2046 2047 #ifdef __cplusplus 2048 } 2049 #endif 2050 2051 #endif /* __STM32F1xx_LL_DMA_H */ 2052