Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h (98657B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_rcc_ex.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL Extension module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F1xx_HAL_RCC_EX_H 20 #define __STM32F1xx_HAL_RCC_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f1xx_hal_def.h" 28 29 /** @addtogroup STM32F1xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCCEx 34 * @{ 35 */ 36 37 /** @addtogroup RCCEx_Private_Constants 38 * @{ 39 */ 40 41 #if defined(STM32F105xC) || defined(STM32F107xC) 42 43 /* Alias word address of PLLI2SON bit */ 44 #define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos 45 #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) 46 /* Alias word address of PLL2ON bit */ 47 #define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos 48 #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) 49 50 #define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ 51 #define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ 52 53 #endif /* STM32F105xC || STM32F107xC */ 54 55 #define CR_REG_INDEX ((uint8_t)1) 56 57 /** 58 * @} 59 */ 60 61 /** @addtogroup RCCEx_Private_Macros 62 * @{ 63 */ 64 65 #if defined(STM32F105xC) || defined(STM32F107xC) 66 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \ 67 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2)) 68 #endif /* STM32F105xC || STM32F107xC */ 69 70 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 71 || defined(STM32F100xE) 72 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \ 73 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \ 74 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \ 75 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \ 76 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \ 77 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \ 78 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \ 79 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16)) 80 81 #else 82 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2)) 83 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 84 85 #if defined(STM32F105xC) || defined(STM32F107xC) 86 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 87 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 88 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 89 ((__MUL__) == RCC_PLL_MUL6_5)) 90 91 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ 92 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ 93 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \ 94 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \ 95 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 96 97 #else 98 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \ 99 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \ 100 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \ 101 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \ 102 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \ 103 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \ 104 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \ 105 ((__MUL__) == RCC_PLL_MUL16)) 106 107 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \ 108 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \ 109 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) 110 111 #endif /* STM32F105xC || STM32F107xC*/ 112 113 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \ 114 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8)) 115 116 #if defined(STM32F105xC) || defined(STM32F107xC) 117 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO)) 118 119 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO)) 120 121 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3)) 122 123 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \ 124 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \ 125 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \ 126 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \ 127 ((__MUL__) == RCC_PLLI2S_MUL20)) 128 129 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \ 130 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \ 131 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \ 132 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \ 133 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \ 134 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \ 135 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \ 136 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16)) 137 138 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \ 139 ((__PLL__) == RCC_PLL2_ON)) 140 141 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \ 142 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \ 143 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \ 144 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \ 145 ((__MUL__) == RCC_PLL2_MUL20)) 146 147 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 148 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 149 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 150 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 151 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ 152 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 153 154 #elif defined(STM32F103xE) || defined(STM32F103xG) 155 156 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) 157 158 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) 159 160 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 161 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 162 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 163 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ 164 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \ 165 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 166 167 168 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 169 || defined(STM32F103xB) 170 171 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 172 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 173 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ 174 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) 175 176 #else 177 178 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ 179 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ 180 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)) 181 182 #endif /* STM32F105xC || STM32F107xC */ 183 184 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 185 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 186 187 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5)) 188 189 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 190 191 /** 192 * @} 193 */ 194 195 /* Exported types ------------------------------------------------------------*/ 196 197 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types 198 * @{ 199 */ 200 201 #if defined(STM32F105xC) || defined(STM32F107xC) 202 /** 203 * @brief RCC PLL2 configuration structure definition 204 */ 205 typedef struct 206 { 207 uint32_t PLL2State; /*!< The new state of the PLL2. 208 This parameter can be a value of @ref RCCEx_PLL2_Config */ 209 210 uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock 211 This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/ 212 213 #if defined(STM32F105xC) || defined(STM32F107xC) 214 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. 215 This parameter can be a value of @ref RCCEx_Prediv2_Factor */ 216 217 #endif /* STM32F105xC || STM32F107xC */ 218 } RCC_PLL2InitTypeDef; 219 220 #endif /* STM32F105xC || STM32F107xC */ 221 222 /** 223 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 224 */ 225 typedef struct { 226 uint32_t OscillatorType; /*!< The oscillators to be configured. 227 This parameter can be a value of @ref RCC_Oscillator_Type */ 228 229 #if defined(STM32F105xC) || defined(STM32F107xC) 230 uint32_t Prediv1Source; /*!< The Prediv1 source value. 231 This parameter can be a value of @ref RCCEx_Prediv1_Source */ 232 #endif /* STM32F105xC || STM32F107xC */ 233 234 uint32_t HSEState; /*!< The new state of the HSE. 235 This parameter can be a value of @ref RCC_HSE_Config */ 236 237 uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM) 238 This parameter can be a value of @ref RCCEx_Prediv1_Factor */ 239 240 uint32_t LSEState; /*!< The new state of the LSE. 241 This parameter can be a value of @ref RCC_LSE_Config */ 242 243 uint32_t HSIState; /*!< The new state of the HSI. 244 This parameter can be a value of @ref RCC_HSI_Config */ 245 246 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 247 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 248 249 uint32_t LSIState; /*!< The new state of the LSI. 250 This parameter can be a value of @ref RCC_LSI_Config */ 251 252 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ 253 254 #if defined(STM32F105xC) || defined(STM32F107xC) 255 RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */ 256 #endif /* STM32F105xC || STM32F107xC */ 257 } RCC_OscInitTypeDef; 258 259 #if defined(STM32F105xC) || defined(STM32F107xC) 260 /** 261 * @brief RCC PLLI2S configuration structure definition 262 */ 263 typedef struct 264 { 265 uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock 266 This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/ 267 268 #if defined(STM32F105xC) || defined(STM32F107xC) 269 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value. 270 This parameter can be a value of @ref RCCEx_Prediv2_Factor */ 271 272 #endif /* STM32F105xC || STM32F107xC */ 273 } RCC_PLLI2SInitTypeDef; 274 #endif /* STM32F105xC || STM32F107xC */ 275 276 /** 277 * @brief RCC extended clocks structure definition 278 */ 279 typedef struct { 280 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. 281 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ 282 283 uint32_t RTCClockSelection; /*!< specifies the RTC clock source. 284 This parameter can be a value of @ref RCC_RTC_Clock_Source */ 285 286 uint32_t AdcClockSelection; /*!< ADC clock source 287 This parameter can be a value of @ref RCCEx_ADC_Prescaler */ 288 289 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 290 || defined(STM32F107xC) 291 uint32_t I2s2ClockSelection; /*!< I2S2 clock source 292 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ 293 294 uint32_t I2s3ClockSelection; /*!< I2S3 clock source 295 This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */ 296 297 #if defined(STM32F105xC) || defined(STM32F107xC) 298 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters 299 This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */ 300 301 #endif /* STM32F105xC || STM32F107xC */ 302 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 303 304 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 305 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 306 || defined(STM32F105xC) || defined(STM32F107xC) 307 uint32_t UsbClockSelection; /*!< USB clock source 308 This parameter can be a value of @ref RCCEx_USB_Prescaler */ 309 310 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 311 } RCC_PeriphCLKInitTypeDef; 312 313 /** 314 * @} 315 */ 316 317 /* Exported constants --------------------------------------------------------*/ 318 319 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants 320 * @{ 321 */ 322 323 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection 324 * @{ 325 */ 326 #define RCC_PERIPHCLK_RTC 0x00000001U 327 #define RCC_PERIPHCLK_ADC 0x00000002U 328 #if defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE)\ 329 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 330 #define RCC_PERIPHCLK_I2S2 0x00000004U 331 #define RCC_PERIPHCLK_I2S3 0x00000008U 332 #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 333 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 334 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 335 || defined(STM32F105xC) || defined(STM32F107xC) 336 #define RCC_PERIPHCLK_USB 0x00000010U 337 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 338 339 /** 340 * @} 341 */ 342 343 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler 344 * @{ 345 */ 346 #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 347 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 348 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 349 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 350 351 /** 352 * @} 353 */ 354 355 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 356 || defined(STM32F107xC) 357 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source 358 * @{ 359 */ 360 #define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U 361 #if defined(STM32F105xC) || defined(STM32F107xC) 362 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC 363 #endif /* STM32F105xC || STM32F107xC */ 364 365 /** 366 * @} 367 */ 368 369 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source 370 * @{ 371 */ 372 #define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U 373 #if defined(STM32F105xC) || defined(STM32F107xC) 374 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC 375 #endif /* STM32F105xC || STM32F107xC */ 376 377 /** 378 * @} 379 */ 380 381 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 382 383 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 384 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 385 386 /** @defgroup RCCEx_USB_Prescaler USB Prescaler 387 * @{ 388 */ 389 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE 390 #define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U 391 392 /** 393 * @} 394 */ 395 396 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 397 398 #if defined(STM32F105xC) || defined(STM32F107xC) 399 /** @defgroup RCCEx_USB_Prescaler USB Prescaler 400 * @{ 401 */ 402 #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE 403 #define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U 404 405 /** 406 * @} 407 */ 408 409 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor 410 * @{ 411 */ 412 413 #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ 414 #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ 415 #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ 416 #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ 417 #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ 418 #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ 419 #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ 420 #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ 421 #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ 422 423 /** 424 * @} 425 */ 426 #endif /* STM32F105xC || STM32F107xC */ 427 428 #if defined(STM32F105xC) || defined(STM32F107xC) 429 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source 430 * @{ 431 */ 432 433 #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE 434 #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2 435 436 /** 437 * @} 438 */ 439 #endif /* STM32F105xC || STM32F107xC */ 440 441 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor 442 * @{ 443 */ 444 445 #define RCC_HSE_PREDIV_DIV1 0x00000000U 446 447 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 448 || defined(STM32F100xE) 449 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2 450 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3 451 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4 452 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5 453 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6 454 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7 455 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8 456 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9 457 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10 458 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11 459 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12 460 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13 461 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14 462 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15 463 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16 464 #else 465 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE 466 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 467 468 /** 469 * @} 470 */ 471 472 #if defined(STM32F105xC) || defined(STM32F107xC) 473 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor 474 * @{ 475 */ 476 477 #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ 478 #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ 479 #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ 480 #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ 481 #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ 482 #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ 483 #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ 484 #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ 485 #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ 486 #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ 487 #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ 488 #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ 489 #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ 490 #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ 491 #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ 492 #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ 493 494 /** 495 * @} 496 */ 497 498 /** @defgroup RCCEx_PLL2_Config PLL Config 499 * @{ 500 */ 501 #define RCC_PLL2_NONE 0x00000000U 502 #define RCC_PLL2_OFF 0x00000001U 503 #define RCC_PLL2_ON 0x00000002U 504 505 /** 506 * @} 507 */ 508 509 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor 510 * @{ 511 */ 512 513 #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ 514 #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ 515 #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ 516 #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ 517 #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ 518 #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ 519 #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ 520 #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ 521 #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ 522 523 /** 524 * @} 525 */ 526 527 #endif /* STM32F105xC || STM32F107xC */ 528 529 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor 530 * @{ 531 */ 532 533 #if defined(STM32F105xC) || defined(STM32F107xC) 534 #else 535 #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2 536 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3 537 #endif /* STM32F105xC || STM32F107xC */ 538 #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4 539 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5 540 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6 541 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7 542 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8 543 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9 544 #if defined(STM32F105xC) || defined(STM32F107xC) 545 #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5 546 #else 547 #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10 548 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11 549 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12 550 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13 551 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14 552 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15 553 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16 554 #endif /* STM32F105xC || STM32F107xC */ 555 556 /** 557 * @} 558 */ 559 560 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source 561 * @{ 562 */ 563 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK) 564 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK) 565 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI) 566 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE) 567 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2) 568 #if defined(STM32F105xC) || defined(STM32F107xC) 569 #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK) 570 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2) 571 #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE) 572 #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK) 573 #endif /* STM32F105xC || STM32F107xC*/ 574 /** 575 * @} 576 */ 577 578 #if defined(STM32F105xC) || defined(STM32F107xC) 579 /** @defgroup RCCEx_Interrupt RCCEx Interrupt 580 * @{ 581 */ 582 #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF) 583 #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF) 584 /** 585 * @} 586 */ 587 588 /** @defgroup RCCEx_Flag RCCEx Flag 589 * Elements values convention: 0XXYYYYYb 590 * - YYYYY : Flag position in the register 591 * - XX : Register index 592 * - 01: CR register 593 * @{ 594 */ 595 /* Flags in the CR register */ 596 #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) 597 #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) 598 /** 599 * @} 600 */ 601 #endif /* STM32F105xC || STM32F107xC*/ 602 603 /** 604 * @} 605 */ 606 607 /* Exported macro ------------------------------------------------------------*/ 608 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros 609 * @{ 610 */ 611 612 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 613 * @brief Enable or disable the AHB1 peripheral clock. 614 * @note After reset, the peripheral clock (used for registers read/write access) 615 * is disabled and the application software has to enable this clock before 616 * using it. 617 * @{ 618 */ 619 620 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 621 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ 622 || defined (STM32F100xE) 623 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 624 __IO uint32_t tmpreg; \ 625 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 626 /* Delay after an RCC peripheral clock enabling */ \ 627 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ 628 UNUSED(tmpreg); \ 629 } while(0U) 630 631 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) 632 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ 633 634 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 635 || defined(STM32F103xG) || defined (STM32F100xE) 636 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \ 637 __IO uint32_t tmpreg; \ 638 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 639 /* Delay after an RCC peripheral clock enabling */ \ 640 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ 641 UNUSED(tmpreg); \ 642 } while(0U) 643 644 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) 645 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ 646 647 #if defined(STM32F103xE) || defined(STM32F103xG) 648 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \ 649 __IO uint32_t tmpreg; \ 650 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 651 /* Delay after an RCC peripheral clock enabling */ \ 652 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ 653 UNUSED(tmpreg); \ 654 } while(0U) 655 656 657 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) 658 #endif /* STM32F103xE || STM32F103xG */ 659 660 #if defined(STM32F105xC) || defined(STM32F107xC) 661 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 662 __IO uint32_t tmpreg; \ 663 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ 664 /* Delay after an RCC peripheral clock enabling */ \ 665 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ 666 UNUSED(tmpreg); \ 667 } while(0U) 668 669 670 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) 671 #endif /* STM32F105xC || STM32F107xC*/ 672 673 #if defined(STM32F107xC) 674 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ 675 __IO uint32_t tmpreg; \ 676 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ 677 /* Delay after an RCC peripheral clock enabling */ \ 678 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ 679 UNUSED(tmpreg); \ 680 } while(0U) 681 682 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ 683 __IO uint32_t tmpreg; \ 684 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ 685 /* Delay after an RCC peripheral clock enabling */ \ 686 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ 687 UNUSED(tmpreg); \ 688 } while(0U) 689 690 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ 691 __IO uint32_t tmpreg; \ 692 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ 693 /* Delay after an RCC peripheral clock enabling */ \ 694 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ 695 UNUSED(tmpreg); \ 696 } while(0U) 697 698 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) 699 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) 700 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN)) 701 702 /** 703 * @brief Enable ETHERNET clock. 704 */ 705 #define __HAL_RCC_ETH_CLK_ENABLE() do { \ 706 __HAL_RCC_ETHMAC_CLK_ENABLE(); \ 707 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ 708 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ 709 } while(0U) 710 /** 711 * @brief Disable ETHERNET clock. 712 */ 713 #define __HAL_RCC_ETH_CLK_DISABLE() do { \ 714 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ 715 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ 716 __HAL_RCC_ETHMAC_CLK_DISABLE(); \ 717 } while(0U) 718 719 #endif /* STM32F107xC*/ 720 721 /** 722 * @} 723 */ 724 725 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status 726 * @brief Get the enable or disable status of the AHB1 peripheral clock. 727 * @note After reset, the peripheral clock (used for registers read/write access) 728 * is disabled and the application software has to enable this clock before 729 * using it. 730 * @{ 731 */ 732 733 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 734 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\ 735 || defined (STM32F100xE) 736 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET) 737 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET) 738 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ 739 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 740 || defined(STM32F103xG) || defined (STM32F100xE) 741 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET) 742 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET) 743 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ 744 #if defined(STM32F103xE) || defined(STM32F103xG) 745 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET) 746 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET) 747 #endif /* STM32F103xE || STM32F103xG */ 748 #if defined(STM32F105xC) || defined(STM32F107xC) 749 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET) 750 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET) 751 #endif /* STM32F105xC || STM32F107xC*/ 752 #if defined(STM32F107xC) 753 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET) 754 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET) 755 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET) 756 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET) 757 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET) 758 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET) 759 #endif /* STM32F107xC*/ 760 761 /** 762 * @} 763 */ 764 765 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 766 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 767 * @note After reset, the peripheral clock (used for registers read/write access) 768 * is disabled and the application software has to enable this clock before 769 * using it. 770 * @{ 771 */ 772 773 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 774 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 775 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 776 __IO uint32_t tmpreg; \ 777 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 778 /* Delay after an RCC peripheral clock enabling */ \ 779 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ 780 UNUSED(tmpreg); \ 781 } while(0U) 782 783 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) 784 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 785 786 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 787 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 788 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 789 || defined(STM32F105xC) || defined(STM32F107xC) 790 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 791 __IO uint32_t tmpreg; \ 792 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 793 /* Delay after an RCC peripheral clock enabling */ \ 794 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ 795 UNUSED(tmpreg); \ 796 } while(0U) 797 798 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 799 __IO uint32_t tmpreg; \ 800 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 801 /* Delay after an RCC peripheral clock enabling */ \ 802 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ 803 UNUSED(tmpreg); \ 804 } while(0U) 805 806 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 807 __IO uint32_t tmpreg; \ 808 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 809 /* Delay after an RCC peripheral clock enabling */ \ 810 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ 811 UNUSED(tmpreg); \ 812 } while(0U) 813 814 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 815 __IO uint32_t tmpreg; \ 816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 817 /* Delay after an RCC peripheral clock enabling */ \ 818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ 819 UNUSED(tmpreg); \ 820 } while(0U) 821 822 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) 823 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) 824 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) 825 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) 826 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 827 828 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 829 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 830 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 831 __IO uint32_t tmpreg; \ 832 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 833 /* Delay after an RCC peripheral clock enabling */ \ 834 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ 835 UNUSED(tmpreg); \ 836 } while(0U) 837 838 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) 839 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 840 841 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 842 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 843 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 844 __IO uint32_t tmpreg; \ 845 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 846 /* Delay after an RCC peripheral clock enabling */ \ 847 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 848 UNUSED(tmpreg); \ 849 } while(0U) 850 851 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 852 __IO uint32_t tmpreg; \ 853 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 854 /* Delay after an RCC peripheral clock enabling */ \ 855 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 856 UNUSED(tmpreg); \ 857 } while(0U) 858 859 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 860 __IO uint32_t tmpreg; \ 861 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 862 /* Delay after an RCC peripheral clock enabling */ \ 863 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 864 UNUSED(tmpreg); \ 865 } while(0U) 866 867 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 868 __IO uint32_t tmpreg; \ 869 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 870 /* Delay after an RCC peripheral clock enabling */ \ 871 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 872 UNUSED(tmpreg); \ 873 } while(0U) 874 875 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 876 __IO uint32_t tmpreg; \ 877 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 878 /* Delay after an RCC peripheral clock enabling */ \ 879 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 880 UNUSED(tmpreg); \ 881 } while(0U) 882 883 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 884 __IO uint32_t tmpreg; \ 885 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 886 /* Delay after an RCC peripheral clock enabling */ \ 887 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 888 UNUSED(tmpreg); \ 889 } while(0U) 890 891 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 892 __IO uint32_t tmpreg; \ 893 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 894 /* Delay after an RCC peripheral clock enabling */ \ 895 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 896 UNUSED(tmpreg); \ 897 } while(0U) 898 899 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 900 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 901 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 902 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 903 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 904 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 905 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 906 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 907 908 #if defined(STM32F100xB) || defined (STM32F100xE) 909 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 910 __IO uint32_t tmpreg; \ 911 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 912 /* Delay after an RCC peripheral clock enabling */ \ 913 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ 914 UNUSED(tmpreg); \ 915 } while(0U) 916 917 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 918 __IO uint32_t tmpreg; \ 919 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 920 /* Delay after an RCC peripheral clock enabling */ \ 921 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ 922 UNUSED(tmpreg); \ 923 } while(0U) 924 925 #define __HAL_RCC_DAC_CLK_ENABLE() do { \ 926 __IO uint32_t tmpreg; \ 927 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 928 /* Delay after an RCC peripheral clock enabling */ \ 929 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ 930 UNUSED(tmpreg); \ 931 } while(0U) 932 933 #define __HAL_RCC_CEC_CLK_ENABLE() do { \ 934 __IO uint32_t tmpreg; \ 935 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 936 /* Delay after an RCC peripheral clock enabling */ \ 937 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ 938 UNUSED(tmpreg); \ 939 } while(0U) 940 941 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) 942 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) 943 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) 944 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) 945 #endif /* STM32F100xB || STM32F100xE */ 946 947 #ifdef STM32F100xE 948 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 949 __IO uint32_t tmpreg; \ 950 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 951 /* Delay after an RCC peripheral clock enabling */ \ 952 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ 953 UNUSED(tmpreg); \ 954 } while(0U) 955 956 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 957 __IO uint32_t tmpreg; \ 958 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 959 /* Delay after an RCC peripheral clock enabling */ \ 960 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 961 UNUSED(tmpreg); \ 962 } while(0U) 963 964 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 965 __IO uint32_t tmpreg; \ 966 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 967 /* Delay after an RCC peripheral clock enabling */ \ 968 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 969 UNUSED(tmpreg); \ 970 } while(0U) 971 972 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 973 __IO uint32_t tmpreg; \ 974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 975 /* Delay after an RCC peripheral clock enabling */ \ 976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 977 UNUSED(tmpreg); \ 978 } while(0U) 979 980 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 981 __IO uint32_t tmpreg; \ 982 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 983 /* Delay after an RCC peripheral clock enabling */ \ 984 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ 985 UNUSED(tmpreg); \ 986 } while(0U) 987 988 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 989 __IO uint32_t tmpreg; \ 990 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 991 /* Delay after an RCC peripheral clock enabling */ \ 992 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ 993 UNUSED(tmpreg); \ 994 } while(0U) 995 996 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 997 __IO uint32_t tmpreg; \ 998 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 999 /* Delay after an RCC peripheral clock enabling */ \ 1000 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ 1001 UNUSED(tmpreg); \ 1002 } while(0U) 1003 1004 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) 1005 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 1006 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 1007 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 1008 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) 1009 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) 1010 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) 1011 #endif /* STM32F100xE */ 1012 1013 #if defined(STM32F105xC) || defined(STM32F107xC) 1014 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \ 1015 __IO uint32_t tmpreg; \ 1016 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1017 /* Delay after an RCC peripheral clock enabling */ \ 1018 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ 1019 UNUSED(tmpreg); \ 1020 } while(0U) 1021 1022 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) 1023 #endif /* STM32F105xC || STM32F107xC */ 1024 1025 #if defined(STM32F101xG) || defined(STM32F103xG) 1026 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ 1027 __IO uint32_t tmpreg; \ 1028 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1029 /* Delay after an RCC peripheral clock enabling */ \ 1030 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ 1031 UNUSED(tmpreg); \ 1032 } while(0U) 1033 1034 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ 1035 __IO uint32_t tmpreg; \ 1036 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1037 /* Delay after an RCC peripheral clock enabling */ \ 1038 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ 1039 UNUSED(tmpreg); \ 1040 } while(0U) 1041 1042 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 1043 __IO uint32_t tmpreg; \ 1044 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1045 /* Delay after an RCC peripheral clock enabling */ \ 1046 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ 1047 UNUSED(tmpreg); \ 1048 } while(0U) 1049 1050 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) 1051 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) 1052 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 1053 #endif /* STM32F101xG || STM32F103xG*/ 1054 1055 /** 1056 * @} 1057 */ 1058 1059 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 1060 * @brief Get the enable or disable status of the APB1 peripheral clock. 1061 * @note After reset, the peripheral clock (used for registers read/write access) 1062 * is disabled and the application software has to enable this clock before 1063 * using it. 1064 * @{ 1065 */ 1066 1067 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 1068 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 1069 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 1070 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 1071 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 1072 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 1073 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 1074 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 1075 || defined(STM32F105xC) || defined(STM32F107xC) 1076 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 1077 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 1078 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) 1079 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) 1080 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 1081 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 1082 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) 1083 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) 1084 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1085 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 1086 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 1087 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET) 1088 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET) 1089 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 1090 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1091 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 1092 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 1093 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 1094 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1095 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1096 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1097 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1098 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 1099 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 1100 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 1101 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 1102 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 1103 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 1104 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1105 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1106 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 1107 #if defined(STM32F100xB) || defined (STM32F100xE) 1108 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 1109 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 1110 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 1111 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 1112 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 1113 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 1114 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) 1115 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) 1116 #endif /* STM32F100xB || STM32F100xE */ 1117 #ifdef STM32F100xE 1118 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) 1119 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) 1120 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 1121 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 1122 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 1123 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 1124 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 1125 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 1126 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 1127 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 1128 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 1129 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 1130 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 1131 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 1132 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 1133 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 1134 #endif /* STM32F100xE */ 1135 #if defined(STM32F105xC) || defined(STM32F107xC) 1136 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 1137 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 1138 #endif /* STM32F105xC || STM32F107xC */ 1139 #if defined(STM32F101xG) || defined(STM32F103xG) 1140 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 1141 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 1142 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 1143 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 1144 #endif /* STM32F101xG || STM32F103xG*/ 1145 1146 /** 1147 * @} 1148 */ 1149 1150 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 1151 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 1152 * @note After reset, the peripheral clock (used for registers read/write access) 1153 * is disabled and the application software has to enable this clock before 1154 * using it. 1155 * @{ 1156 */ 1157 1158 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 1159 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 1160 || defined(STM32F103xG) 1161 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \ 1162 __IO uint32_t tmpreg; \ 1163 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1164 /* Delay after an RCC peripheral clock enabling */ \ 1165 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ 1166 UNUSED(tmpreg); \ 1167 } while(0U) 1168 1169 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) 1170 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 1171 1172 #if defined(STM32F100xB) || defined(STM32F100xE) 1173 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 1174 __IO uint32_t tmpreg; \ 1175 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 1176 /* Delay after an RCC peripheral clock enabling */ \ 1177 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ 1178 UNUSED(tmpreg); \ 1179 } while(0U) 1180 1181 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 1182 __IO uint32_t tmpreg; \ 1183 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 1184 /* Delay after an RCC peripheral clock enabling */ \ 1185 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ 1186 UNUSED(tmpreg); \ 1187 } while(0U) 1188 1189 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 1190 __IO uint32_t tmpreg; \ 1191 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 1192 /* Delay after an RCC peripheral clock enabling */ \ 1193 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ 1194 UNUSED(tmpreg); \ 1195 } while(0U) 1196 1197 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) 1198 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) 1199 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN)) 1200 #endif /* STM32F100xB || STM32F100xE */ 1201 1202 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 1203 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 1204 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 1205 || defined(STM32F107xC) 1206 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 1207 __IO uint32_t tmpreg; \ 1208 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ 1209 /* Delay after an RCC peripheral clock enabling */ \ 1210 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ 1211 UNUSED(tmpreg); \ 1212 } while(0U) 1213 1214 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) 1215 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1216 1217 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1218 || defined(STM32F103xG) 1219 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1220 __IO uint32_t tmpreg; \ 1221 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 1222 /* Delay after an RCC peripheral clock enabling */ \ 1223 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 1224 UNUSED(tmpreg); \ 1225 } while(0U) 1226 1227 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1228 __IO uint32_t tmpreg; \ 1229 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 1230 /* Delay after an RCC peripheral clock enabling */ \ 1231 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 1232 UNUSED(tmpreg); \ 1233 } while(0U) 1234 1235 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) 1236 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) 1237 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 1238 1239 #if defined(STM32F103xE) || defined(STM32F103xG) 1240 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 1241 __IO uint32_t tmpreg; \ 1242 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1243 /* Delay after an RCC peripheral clock enabling */ \ 1244 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ 1245 UNUSED(tmpreg); \ 1246 } while(0U) 1247 1248 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ 1249 __IO uint32_t tmpreg; \ 1250 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1251 /* Delay after an RCC peripheral clock enabling */ \ 1252 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ 1253 UNUSED(tmpreg); \ 1254 } while(0U) 1255 1256 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) 1257 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) 1258 #endif /* STM32F103xE || STM32F103xG */ 1259 1260 #if defined(STM32F100xE) 1261 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 1262 __IO uint32_t tmpreg; \ 1263 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 1264 /* Delay after an RCC peripheral clock enabling */ \ 1265 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ 1266 UNUSED(tmpreg); \ 1267 } while(0U) 1268 1269 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 1270 __IO uint32_t tmpreg; \ 1271 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 1272 /* Delay after an RCC peripheral clock enabling */ \ 1273 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ 1274 UNUSED(tmpreg); \ 1275 } while(0U) 1276 1277 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) 1278 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) 1279 #endif /* STM32F100xE */ 1280 1281 #if defined(STM32F101xG) || defined(STM32F103xG) 1282 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \ 1283 __IO uint32_t tmpreg; \ 1284 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 1285 /* Delay after an RCC peripheral clock enabling */ \ 1286 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ 1287 UNUSED(tmpreg); \ 1288 } while(0U) 1289 1290 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ 1291 __IO uint32_t tmpreg; \ 1292 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1293 /* Delay after an RCC peripheral clock enabling */ \ 1294 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ 1295 UNUSED(tmpreg); \ 1296 } while(0U) 1297 1298 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ 1299 __IO uint32_t tmpreg; \ 1300 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 1301 /* Delay after an RCC peripheral clock enabling */ \ 1302 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ 1303 UNUSED(tmpreg); \ 1304 } while(0U) 1305 1306 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) 1307 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) 1308 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) 1309 #endif /* STM32F101xG || STM32F103xG */ 1310 1311 /** 1312 * @} 1313 */ 1314 1315 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 1316 * @brief Get the enable or disable status of the APB2 peripheral clock. 1317 * @note After reset, the peripheral clock (used for registers read/write access) 1318 * is disabled and the application software has to enable this clock before 1319 * using it. 1320 * @{ 1321 */ 1322 1323 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 1324 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 1325 || defined(STM32F103xG) 1326 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 1327 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 1328 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 1329 #if defined(STM32F100xB) || defined(STM32F100xE) 1330 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET) 1331 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET) 1332 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET) 1333 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET) 1334 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET) 1335 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET) 1336 #endif /* STM32F100xB || STM32F100xE */ 1337 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 1338 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 1339 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 1340 || defined(STM32F107xC) 1341 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET) 1342 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET) 1343 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1344 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1345 || defined(STM32F103xG) 1346 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) 1347 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) 1348 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) 1349 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) 1350 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 1351 #if defined(STM32F103xE) || defined(STM32F103xG) 1352 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 1353 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 1354 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 1355 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 1356 #endif /* STM32F103xE || STM32F103xG */ 1357 #if defined(STM32F100xE) 1358 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET) 1359 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET) 1360 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET) 1361 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET) 1362 #endif /* STM32F100xE */ 1363 #if defined(STM32F101xG) || defined(STM32F103xG) 1364 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) 1365 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) 1366 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 1367 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 1368 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) 1369 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) 1370 #endif /* STM32F101xG || STM32F103xG */ 1371 1372 /** 1373 * @} 1374 */ 1375 1376 #if defined(STM32F105xC) || defined(STM32F107xC) 1377 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release 1378 * @brief Force or release AHB peripheral reset. 1379 * @{ 1380 */ 1381 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) 1382 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST)) 1383 #if defined(STM32F107xC) 1384 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST)) 1385 #endif /* STM32F107xC */ 1386 1387 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) 1388 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST)) 1389 #if defined(STM32F107xC) 1390 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST)) 1391 #endif /* STM32F107xC */ 1392 1393 /** 1394 * @} 1395 */ 1396 #endif /* STM32F105xC || STM32F107xC */ 1397 1398 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 1399 * @brief Force or release APB1 peripheral reset. 1400 * @{ 1401 */ 1402 1403 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\ 1404 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC) 1405 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) 1406 1407 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) 1408 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 1409 1410 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\ 1411 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\ 1412 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ 1413 || defined(STM32F105xC) || defined(STM32F107xC) 1414 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) 1415 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) 1416 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) 1417 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) 1418 1419 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) 1420 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) 1421 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) 1422 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) 1423 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1424 1425 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 1426 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 1427 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) 1428 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) 1429 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 1430 1431 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1432 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) 1433 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 1434 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1435 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1436 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1437 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1438 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1439 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1440 1441 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 1442 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1443 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1444 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1445 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1446 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1447 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1448 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */ 1449 1450 #if defined(STM32F100xB) || defined (STM32F100xE) 1451 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) 1452 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) 1453 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) 1454 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) 1455 1456 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) 1457 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) 1458 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) 1459 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) 1460 #endif /* STM32F100xB || STM32F100xE */ 1461 1462 #if defined (STM32F100xE) 1463 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) 1464 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1465 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1466 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1467 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) 1468 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) 1469 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) 1470 1471 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) 1472 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1473 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1474 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1475 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) 1476 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) 1477 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) 1478 #endif /* STM32F100xE */ 1479 1480 #if defined(STM32F105xC) || defined(STM32F107xC) 1481 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) 1482 1483 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) 1484 #endif /* STM32F105xC || STM32F107xC */ 1485 1486 #if defined(STM32F101xG) || defined(STM32F103xG) 1487 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) 1488 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) 1489 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 1490 1491 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) 1492 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) 1493 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 1494 #endif /* STM32F101xG || STM32F103xG */ 1495 1496 /** 1497 * @} 1498 */ 1499 1500 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 1501 * @brief Force or release APB2 peripheral reset. 1502 * @{ 1503 */ 1504 1505 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\ 1506 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\ 1507 || defined(STM32F103xG) 1508 #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST)) 1509 1510 #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST)) 1511 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ 1512 1513 #if defined(STM32F100xB) || defined(STM32F100xE) 1514 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST)) 1515 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST)) 1516 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST)) 1517 1518 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST)) 1519 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST)) 1520 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST)) 1521 #endif /* STM32F100xB || STM32F100xE */ 1522 1523 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\ 1524 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\ 1525 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ 1526 || defined(STM32F107xC) 1527 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST)) 1528 1529 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST)) 1530 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ 1531 1532 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\ 1533 || defined(STM32F103xG) 1534 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) 1535 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) 1536 1537 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) 1538 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) 1539 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/ 1540 1541 #if defined(STM32F103xE) || defined(STM32F103xG) 1542 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) 1543 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST)) 1544 1545 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) 1546 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST)) 1547 #endif /* STM32F103xE || STM32F103xG */ 1548 1549 #if defined(STM32F100xE) 1550 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST)) 1551 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST)) 1552 1553 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST)) 1554 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST)) 1555 #endif /* STM32F100xE */ 1556 1557 #if defined(STM32F101xG) || defined(STM32F103xG) 1558 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) 1559 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) 1560 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) 1561 1562 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) 1563 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) 1564 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) 1565 #endif /* STM32F101xG || STM32F103xG*/ 1566 1567 /** 1568 * @} 1569 */ 1570 1571 /** @defgroup RCCEx_HSE_Configuration HSE Configuration 1572 * @{ 1573 */ 1574 1575 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 1576 || defined(STM32F100xE) 1577 /** 1578 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 1579 * @note Predivision factor can not be changed if PLL is used as system clock 1580 * In this case, you have to select another source of the system clock, disable the PLL and 1581 * then change the HSE predivision factor. 1582 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 1583 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. 1584 */ 1585 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__)) 1586 #else 1587 /** 1588 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. 1589 * @note Predivision factor can not be changed if PLL is used as system clock 1590 * In this case, you have to select another source of the system clock, disable the PLL and 1591 * then change the HSE predivision factor. 1592 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE. 1593 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2. 1594 */ 1595 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \ 1596 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__)) 1597 1598 #endif /* STM32F105xC || STM32F107xC */ 1599 1600 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ 1601 || defined(STM32F100xE) 1602 /** 1603 * @brief Macro to get prediv1 factor for PLL. 1604 */ 1605 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1) 1606 1607 #else 1608 /** 1609 * @brief Macro to get prediv1 factor for PLL. 1610 */ 1611 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) 1612 1613 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ 1614 1615 /** 1616 * @} 1617 */ 1618 1619 #if defined(STM32F105xC) || defined(STM32F107xC) 1620 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration 1621 * @{ 1622 */ 1623 1624 /** @brief Macros to enable the main PLLI2S. 1625 * @note After enabling the main PLLI2S, the application software should wait on 1626 * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can 1627 * be used as system clock source. 1628 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 1629 */ 1630 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE) 1631 1632 /** @brief Macros to disable the main PLLI2S. 1633 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes. 1634 */ 1635 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE) 1636 1637 /** @brief macros to configure the main PLLI2S multiplication factor. 1638 * @note This function must be used only when the main PLLI2S is disabled. 1639 * 1640 * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock 1641 * This parameter can be one of the following values: 1642 * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8 1643 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9 1644 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10 1645 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11 1646 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12 1647 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13 1648 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14 1649 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16 1650 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20 1651 * 1652 */ 1653 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\ 1654 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__)) 1655 1656 /** 1657 * @} 1658 */ 1659 1660 #endif /* STM32F105xC || STM32F107xC */ 1661 1662 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration 1663 * @brief Macros to configure clock source of different peripherals. 1664 * @{ 1665 */ 1666 1667 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ 1668 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) 1669 /** @brief Macro to configure the USB clock. 1670 * @param __USBCLKSOURCE__ specifies the USB clock source. 1671 * This parameter can be one of the following values: 1672 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock 1673 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock 1674 */ 1675 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 1676 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__)) 1677 1678 /** @brief Macro to get the USB clock (USBCLK). 1679 * @retval The clock source can be one of the following values: 1680 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock 1681 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock 1682 */ 1683 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) 1684 1685 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ 1686 1687 #if defined(STM32F105xC) || defined(STM32F107xC) 1688 1689 /** @brief Macro to configure the USB OTSclock. 1690 * @param __USBCLKSOURCE__ specifies the USB clock source. 1691 * This parameter can be one of the following values: 1692 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock 1693 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock 1694 */ 1695 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \ 1696 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__)) 1697 1698 /** @brief Macro to get the USB clock (USBCLK). 1699 * @retval The clock source can be one of the following values: 1700 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock 1701 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock 1702 */ 1703 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE))) 1704 1705 #endif /* STM32F105xC || STM32F107xC */ 1706 1707 /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices). 1708 * @param __ADCCLKSOURCE__ specifies the ADC clock source. 1709 * This parameter can be one of the following values: 1710 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock 1711 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock 1712 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock 1713 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock 1714 */ 1715 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \ 1716 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__)) 1717 1718 /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices). 1719 * @retval The clock source can be one of the following values: 1720 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock 1721 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock 1722 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock 1723 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock 1724 */ 1725 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) 1726 1727 /** 1728 * @} 1729 */ 1730 1731 #if defined(STM32F105xC) || defined(STM32F107xC) 1732 1733 /** @addtogroup RCCEx_HSE_Configuration 1734 * @{ 1735 */ 1736 1737 /** 1738 * @brief Macro to configure the PLL2 & PLLI2S Predivision factor. 1739 * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock 1740 * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and 1741 * then change the PREDIV2 factor. 1742 * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S. 1743 * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16. 1744 */ 1745 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \ 1746 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__)) 1747 1748 /** 1749 * @brief Macro to get prediv2 factor for PLL2 & PLL3. 1750 */ 1751 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2) 1752 1753 /** 1754 * @} 1755 */ 1756 1757 /** @addtogroup RCCEx_PLLI2S_Configuration 1758 * @{ 1759 */ 1760 1761 /** @brief Macros to enable the main PLL2. 1762 * @note After enabling the main PLL2, the application software should wait on 1763 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can 1764 * be used as system clock source. 1765 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1766 */ 1767 #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE) 1768 1769 /** @brief Macros to disable the main PLL2. 1770 * @note The main PLL2 can not be disabled if it is used indirectly as system clock source 1771 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes. 1772 */ 1773 #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE) 1774 1775 /** @brief macros to configure the main PLL2 multiplication factor. 1776 * @note This function must be used only when the main PLL2 is disabled. 1777 * 1778 * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock 1779 * This parameter can be one of the following values: 1780 * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8 1781 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9 1782 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10 1783 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11 1784 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12 1785 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13 1786 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14 1787 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16 1788 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20 1789 * 1790 */ 1791 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\ 1792 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__)) 1793 1794 /** 1795 * @} 1796 */ 1797 1798 /** @defgroup RCCEx_I2S_Configuration I2S Configuration 1799 * @brief Macros to configure clock source of I2S peripherals. 1800 * @{ 1801 */ 1802 1803 /** @brief Macro to configure the I2S2 clock. 1804 * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source. 1805 * This parameter can be one of the following values: 1806 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 1807 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 1808 */ 1809 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \ 1810 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__)) 1811 1812 /** @brief Macro to get the I2S2 clock (I2S2CLK). 1813 * @retval The clock source can be one of the following values: 1814 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 1815 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 1816 */ 1817 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC))) 1818 1819 /** @brief Macro to configure the I2S3 clock. 1820 * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source. 1821 * This parameter can be one of the following values: 1822 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 1823 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 1824 */ 1825 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \ 1826 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__)) 1827 1828 /** @brief Macro to get the I2S3 clock (I2S3CLK). 1829 * @retval The clock source can be one of the following values: 1830 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry 1831 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry 1832 */ 1833 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC))) 1834 1835 /** 1836 * @} 1837 */ 1838 1839 #endif /* STM32F105xC || STM32F107xC */ 1840 /** 1841 * @} 1842 */ 1843 1844 /* Exported functions --------------------------------------------------------*/ 1845 /** @addtogroup RCCEx_Exported_Functions 1846 * @{ 1847 */ 1848 1849 /** @addtogroup RCCEx_Exported_Functions_Group1 1850 * @{ 1851 */ 1852 1853 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig( 1854 RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1855 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); 1856 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); 1857 1858 /** 1859 * @} 1860 */ 1861 1862 #if defined(STM32F105xC) || defined(STM32F107xC) 1863 /** @addtogroup RCCEx_Exported_Functions_Group2 1864 * @{ 1865 */ 1866 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); 1867 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); 1868 1869 /** 1870 * @} 1871 */ 1872 1873 /** @addtogroup RCCEx_Exported_Functions_Group3 1874 * @{ 1875 */ 1876 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init); 1877 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); 1878 1879 /** 1880 * @} 1881 */ 1882 #endif /* STM32F105xC || STM32F107xC */ 1883 1884 /** 1885 * @} 1886 */ 1887 1888 /** 1889 * @} 1890 */ 1891 1892 /** 1893 * @} 1894 */ 1895 1896 #ifdef __cplusplus 1897 } 1898 #endif 1899 1900 #endif /* __STM32F1xx_HAL_RCC_EX_H */ 1901