Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h (16433B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F1xx_HAL_DMA_H 21 #define __STM32F1xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f1xx_hal_def.h" 29 30 /** @addtogroup STM32F1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct { 48 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 49 from memory to memory or from peripheral to memory. 50 This parameter can be a value of @ref DMA_Data_transfer_direction */ 51 52 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 53 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 54 55 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 56 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 57 58 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 59 This parameter can be a value of @ref DMA_Peripheral_data_size */ 60 61 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 62 This parameter can be a value of @ref DMA_Memory_data_size */ 63 64 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 65 This parameter can be a value of @ref DMA_mode 66 @note The circular buffer mode cannot be used if the memory-to-memory 67 data transfer is configured on the selected Channel */ 68 69 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 70 This parameter can be a value of @ref DMA_Priority_level */ 71 } DMA_InitTypeDef; 72 73 /** 74 * @brief HAL DMA State structures definition 75 */ 76 typedef enum { 77 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 78 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 79 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 80 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ 81 } HAL_DMA_StateTypeDef; 82 83 /** 84 * @brief HAL DMA Error Code structure definition 85 */ 86 typedef enum { 87 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 88 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 89 } HAL_DMA_LevelCompleteTypeDef; 90 91 /** 92 * @brief HAL DMA Callback ID structure definition 93 */ 94 typedef enum { 95 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 96 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 97 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 98 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 99 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 100 101 } HAL_DMA_CallbackIDTypeDef; 102 103 /** 104 * @brief DMA handle Structure definition 105 */ 106 typedef struct __DMA_HandleTypeDef { 107 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 108 109 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 110 111 HAL_LockTypeDef Lock; /*!< DMA locking object */ 112 113 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 114 115 void *Parent; /*!< Parent object state */ 116 117 void (*XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ 118 119 void (*XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ 120 121 void (*XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ 122 123 void (*XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ 124 125 __IO uint32_t ErrorCode; /*!< DMA Error code */ 126 127 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 128 129 uint32_t ChannelIndex; /*!< DMA Channel Index */ 130 131 } DMA_HandleTypeDef; 132 /** 133 * @} 134 */ 135 136 /* Exported constants --------------------------------------------------------*/ 137 138 /** @defgroup DMA_Exported_Constants DMA Exported Constants 139 * @{ 140 */ 141 142 /** @defgroup DMA_Error_Code DMA Error Code 143 * @{ 144 */ 145 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 146 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 147 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ 148 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 149 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 150 /** 151 * @} 152 */ 153 154 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 155 * @{ 156 */ 157 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 158 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ 159 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ 160 161 /** 162 * @} 163 */ 164 165 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 166 * @{ 167 */ 168 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ 169 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 170 /** 171 * @} 172 */ 173 174 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 175 * @{ 176 */ 177 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ 178 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 179 /** 180 * @} 181 */ 182 183 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 184 * @{ 185 */ 186 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 187 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 188 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 189 /** 190 * @} 191 */ 192 193 /** @defgroup DMA_Memory_data_size DMA Memory data size 194 * @{ 195 */ 196 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 197 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 198 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ 199 /** 200 * @} 201 */ 202 203 /** @defgroup DMA_mode DMA mode 204 * @{ 205 */ 206 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 207 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ 208 /** 209 * @} 210 */ 211 212 /** @defgroup DMA_Priority_level DMA Priority level 213 * @{ 214 */ 215 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 216 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ 217 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ 218 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ 219 /** 220 * @} 221 */ 222 223 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 224 * @{ 225 */ 226 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) 227 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) 228 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) 229 /** 230 * @} 231 */ 232 233 /** @defgroup DMA_flag_definitions DMA flag definitions 234 * @{ 235 */ 236 #define DMA_FLAG_GL1 0x00000001U 237 #define DMA_FLAG_TC1 0x00000002U 238 #define DMA_FLAG_HT1 0x00000004U 239 #define DMA_FLAG_TE1 0x00000008U 240 #define DMA_FLAG_GL2 0x00000010U 241 #define DMA_FLAG_TC2 0x00000020U 242 #define DMA_FLAG_HT2 0x00000040U 243 #define DMA_FLAG_TE2 0x00000080U 244 #define DMA_FLAG_GL3 0x00000100U 245 #define DMA_FLAG_TC3 0x00000200U 246 #define DMA_FLAG_HT3 0x00000400U 247 #define DMA_FLAG_TE3 0x00000800U 248 #define DMA_FLAG_GL4 0x00001000U 249 #define DMA_FLAG_TC4 0x00002000U 250 #define DMA_FLAG_HT4 0x00004000U 251 #define DMA_FLAG_TE4 0x00008000U 252 #define DMA_FLAG_GL5 0x00010000U 253 #define DMA_FLAG_TC5 0x00020000U 254 #define DMA_FLAG_HT5 0x00040000U 255 #define DMA_FLAG_TE5 0x00080000U 256 #define DMA_FLAG_GL6 0x00100000U 257 #define DMA_FLAG_TC6 0x00200000U 258 #define DMA_FLAG_HT6 0x00400000U 259 #define DMA_FLAG_TE6 0x00800000U 260 #define DMA_FLAG_GL7 0x01000000U 261 #define DMA_FLAG_TC7 0x02000000U 262 #define DMA_FLAG_HT7 0x04000000U 263 #define DMA_FLAG_TE7 0x08000000U 264 /** 265 * @} 266 */ 267 268 /** 269 * @} 270 */ 271 272 /* Exported macros -----------------------------------------------------------*/ 273 /** @defgroup DMA_Exported_Macros DMA Exported Macros 274 * @{ 275 */ 276 277 /** @brief Reset DMA handle state. 278 * @param __HANDLE__: DMA handle 279 * @retval None 280 */ 281 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 282 283 /** 284 * @brief Enable the specified DMA Channel. 285 * @param __HANDLE__: DMA handle 286 * @retval None 287 */ 288 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) 289 290 /** 291 * @brief Disable the specified DMA Channel. 292 * @param __HANDLE__: DMA handle 293 * @retval None 294 */ 295 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) 296 297 /* Interrupt & Flag management */ 298 299 /** 300 * @brief Enables the specified DMA Channel interrupts. 301 * @param __HANDLE__: DMA handle 302 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 303 * This parameter can be any combination of the following values: 304 * @arg DMA_IT_TC: Transfer complete interrupt mask 305 * @arg DMA_IT_HT: Half transfer complete interrupt mask 306 * @arg DMA_IT_TE: Transfer error interrupt mask 307 * @retval None 308 */ 309 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) 310 311 /** 312 * @brief Disable the specified DMA Channel interrupts. 313 * @param __HANDLE__: DMA handle 314 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 315 * This parameter can be any combination of the following values: 316 * @arg DMA_IT_TC: Transfer complete interrupt mask 317 * @arg DMA_IT_HT: Half transfer complete interrupt mask 318 * @arg DMA_IT_TE: Transfer error interrupt mask 319 * @retval None 320 */ 321 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) 322 323 /** 324 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 325 * @param __HANDLE__: DMA handle 326 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 327 * This parameter can be one of the following values: 328 * @arg DMA_IT_TC: Transfer complete interrupt mask 329 * @arg DMA_IT_HT: Half transfer complete interrupt mask 330 * @arg DMA_IT_TE: Transfer error interrupt mask 331 * @retval The state of DMA_IT (SET or RESET). 332 */ 333 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 334 335 /** 336 * @brief Return the number of remaining data units in the current DMA Channel transfer. 337 * @param __HANDLE__: DMA handle 338 * @retval The number of remaining data units in the current DMA Channel transfer. 339 */ 340 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 341 342 /** 343 * @} 344 */ 345 346 /* Include DMA HAL Extension module */ 347 #include "stm32f1xx_hal_dma_ex.h" 348 349 /* Exported functions --------------------------------------------------------*/ 350 /** @addtogroup DMA_Exported_Functions 351 * @{ 352 */ 353 354 /** @addtogroup DMA_Exported_Functions_Group1 355 * @{ 356 */ 357 /* Initialization and de-initialization functions *****************************/ 358 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 359 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 360 /** 361 * @} 362 */ 363 364 /** @addtogroup DMA_Exported_Functions_Group2 365 * @{ 366 */ 367 /* IO operation functions *****************************************************/ 368 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, 369 uint32_t DstAddress, uint32_t DataLength); 370 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, 371 uint32_t DstAddress, uint32_t DataLength); 372 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 373 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 374 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, 375 uint32_t CompleteLevel, uint32_t Timeout); 376 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 377 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, 378 HAL_DMA_CallbackIDTypeDef CallbackID, 379 void (*pCallback)(DMA_HandleTypeDef *_hdma)); 380 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, 381 HAL_DMA_CallbackIDTypeDef CallbackID); 382 383 /** 384 * @} 385 */ 386 387 /** @addtogroup DMA_Exported_Functions_Group3 388 * @{ 389 */ 390 /* Peripheral State and Error functions ***************************************/ 391 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 392 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 393 /** 394 * @} 395 */ 396 397 /** 398 * @} 399 */ 400 401 /* Private macros ------------------------------------------------------------*/ 402 /** @defgroup DMA_Private_Macros DMA Private Macros 403 * @{ 404 */ 405 406 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 407 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 408 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 409 410 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 411 412 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 413 ((STATE) == DMA_PINC_DISABLE)) 414 415 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 416 ((STATE) == DMA_MINC_DISABLE)) 417 418 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 419 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 420 ((SIZE) == DMA_PDATAALIGN_WORD)) 421 422 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 423 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 424 ((SIZE) == DMA_MDATAALIGN_WORD )) 425 426 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 427 ((MODE) == DMA_CIRCULAR)) 428 429 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 430 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 431 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 432 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 433 434 /** 435 * @} 436 */ 437 438 /* Private functions ---------------------------------------------------------*/ 439 440 /** 441 * @} 442 */ 443 444 /** 445 * @} 446 */ 447 448 #ifdef __cplusplus 449 } 450 #endif 451 452 #endif /* __STM32F1xx_HAL_DMA_H */ 453