Drivers/CMSIS/Include/core_cm4.h (123435B)
1 /**************************************************************************//** 2 * @file core_cm4.h 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File 4 * @version V5.0.8 5 * @date 04. June 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_CM4_H_GENERIC 32 #define __CORE_CM4_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup Cortex_M4 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS CM4 definitions */ 65 #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ 68 __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_M (4U) /*!< Cortex-M Core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 74 */ 75 #if defined ( __CC_ARM ) 76 #if defined __TARGET_FPU_VFP 77 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 78 #define __FPU_USED 1U 79 #else 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 81 #define __FPU_USED 0U 82 #endif 83 #else 84 #define __FPU_USED 0U 85 #endif 86 87 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 88 #if defined __ARM_PCS_VFP 89 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 90 #define __FPU_USED 1U 91 #else 92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 93 #define __FPU_USED 0U 94 #endif 95 #else 96 #define __FPU_USED 0U 97 #endif 98 99 #elif defined ( __GNUC__ ) 100 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 102 #define __FPU_USED 1U 103 #else 104 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 105 #define __FPU_USED 0U 106 #endif 107 #else 108 #define __FPU_USED 0U 109 #endif 110 111 #elif defined ( __ICCARM__ ) 112 #if defined __ARMVFP__ 113 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 114 #define __FPU_USED 1U 115 #else 116 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 117 #define __FPU_USED 0U 118 #endif 119 #else 120 #define __FPU_USED 0U 121 #endif 122 123 #elif defined ( __TI_ARM__ ) 124 #if defined __TI_VFP_SUPPORT__ 125 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 126 #define __FPU_USED 1U 127 #else 128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 129 #define __FPU_USED 0U 130 #endif 131 #else 132 #define __FPU_USED 0U 133 #endif 134 135 #elif defined ( __TASKING__ ) 136 #if defined __FPU_VFP__ 137 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 138 #define __FPU_USED 1U 139 #else 140 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 141 #define __FPU_USED 0U 142 #endif 143 #else 144 #define __FPU_USED 0U 145 #endif 146 147 #elif defined ( __CSMC__ ) 148 #if ( __CSMC__ & 0x400U) 149 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 150 #define __FPU_USED 1U 151 #else 152 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 153 #define __FPU_USED 0U 154 #endif 155 #else 156 #define __FPU_USED 0U 157 #endif 158 159 #endif 160 161 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 162 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif /* __CORE_CM4_H_GENERIC */ 168 169 #ifndef __CMSIS_GENERIC 170 171 #ifndef __CORE_CM4_H_DEPENDANT 172 #define __CORE_CM4_H_DEPENDANT 173 174 #ifdef __cplusplus 175 extern "C" { 176 #endif 177 178 /* check device defines and use defaults */ 179 #if defined __CHECK_DEVICE_DEFINES 180 #ifndef __CM4_REV 181 #define __CM4_REV 0x0000U 182 #warning "__CM4_REV not defined in device header file; using default!" 183 #endif 184 185 #ifndef __FPU_PRESENT 186 #define __FPU_PRESENT 0U 187 #warning "__FPU_PRESENT not defined in device header file; using default!" 188 #endif 189 190 #ifndef __MPU_PRESENT 191 #define __MPU_PRESENT 0U 192 #warning "__MPU_PRESENT not defined in device header file; using default!" 193 #endif 194 195 #ifndef __NVIC_PRIO_BITS 196 #define __NVIC_PRIO_BITS 3U 197 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 198 #endif 199 200 #ifndef __Vendor_SysTickConfig 201 #define __Vendor_SysTickConfig 0U 202 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 203 #endif 204 #endif 205 206 /* IO definitions (access restrictions to peripheral registers) */ 207 /** 208 \defgroup CMSIS_glob_defs CMSIS Global Defines 209 210 <strong>IO Type Qualifiers</strong> are used 211 \li to specify the access to peripheral variables. 212 \li for automatic generation of peripheral register debug information. 213 */ 214 #ifdef __cplusplus 215 #define __I volatile /*!< Defines 'read only' permissions */ 216 #else 217 #define __I volatile const /*!< Defines 'read only' permissions */ 218 #endif 219 #define __O volatile /*!< Defines 'write only' permissions */ 220 #define __IO volatile /*!< Defines 'read / write' permissions */ 221 222 /* following defines should be used for structure members */ 223 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 224 #define __OM volatile /*! Defines 'write only' structure member permissions */ 225 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 226 227 /*@} end of group Cortex_M4 */ 228 229 /******************************************************************************* 230 * Register Abstraction 231 Core Register contain: 232 - Core Register 233 - Core NVIC Register 234 - Core SCB Register 235 - Core SysTick Register 236 - Core Debug Register 237 - Core MPU Register 238 - Core FPU Register 239 ******************************************************************************/ 240 /** 241 \defgroup CMSIS_core_register Defines and Type Definitions 242 \brief Type definitions and defines for Cortex-M processor based devices. 243 */ 244 245 /** 246 \ingroup CMSIS_core_register 247 \defgroup CMSIS_CORE Status and Control Registers 248 \brief Core Register type definitions. 249 @{ 250 */ 251 252 /** 253 \brief Union type to access the Application Program Status Register (APSR). 254 */ 255 typedef union { 256 struct { 257 uint32_t _reserved0 :16; /*!< bit: 0..15 Reserved */ 258 uint32_t GE :4; /*!< bit: 16..19 Greater than or Equal flags */ 259 uint32_t _reserved1 :7; /*!< bit: 20..26 Reserved */ 260 uint32_t Q :1; /*!< bit: 27 Saturation condition flag */ 261 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 262 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 263 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 264 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 265 } b; /*!< Structure used for bit access */ 266 uint32_t w; /*!< Type used for word access */ 267 } APSR_Type; 268 269 /* APSR Register Definitions */ 270 #define APSR_N_Pos 31U /*!< APSR: N Position */ 271 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 272 273 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 274 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 275 276 #define APSR_C_Pos 29U /*!< APSR: C Position */ 277 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 278 279 #define APSR_V_Pos 28U /*!< APSR: V Position */ 280 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 281 282 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 283 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 284 285 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 286 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 287 288 /** 289 \brief Union type to access the Interrupt Program Status Register (IPSR). 290 */ 291 typedef union { 292 struct { 293 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 294 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 295 } b; /*!< Structure used for bit access */ 296 uint32_t w; /*!< Type used for word access */ 297 } IPSR_Type; 298 299 /* IPSR Register Definitions */ 300 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 301 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 302 303 /** 304 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 305 */ 306 typedef union { 307 struct { 308 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 309 uint32_t _reserved0 :1; /*!< bit: 9 Reserved */ 310 uint32_t ICI_IT_1 :6; /*!< bit: 10..15 ICI/IT part 1 */ 311 uint32_t GE :4; /*!< bit: 16..19 Greater than or Equal flags */ 312 uint32_t _reserved1 :4; /*!< bit: 20..23 Reserved */ 313 uint32_t T :1; /*!< bit: 24 Thumb bit */ 314 uint32_t ICI_IT_2 :2; /*!< bit: 25..26 ICI/IT part 2 */ 315 uint32_t Q :1; /*!< bit: 27 Saturation condition flag */ 316 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 317 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 318 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 319 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 320 } b; /*!< Structure used for bit access */ 321 uint32_t w; /*!< Type used for word access */ 322 } xPSR_Type; 323 324 /* xPSR Register Definitions */ 325 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 326 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 327 328 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 329 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 330 331 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 332 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 333 334 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 335 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 336 337 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 338 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 339 340 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 341 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 342 343 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 344 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 345 346 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 347 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 348 349 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 350 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 351 352 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 353 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 354 355 /** 356 \brief Union type to access the Control Registers (CONTROL). 357 */ 358 typedef union { 359 struct { 360 uint32_t nPRIV :1; /*!< bit: 0 Execution privilege in Thread mode */ 361 uint32_t SPSEL :1; /*!< bit: 1 Stack to be used */ 362 uint32_t FPCA :1; /*!< bit: 2 FP extension active flag */ 363 uint32_t _reserved0 :29; /*!< bit: 3..31 Reserved */ 364 } b; /*!< Structure used for bit access */ 365 uint32_t w; /*!< Type used for word access */ 366 } CONTROL_Type; 367 368 /* CONTROL Register Definitions */ 369 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 370 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 371 372 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 373 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 374 375 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 376 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 377 378 /*@} end of group CMSIS_CORE */ 379 380 /** 381 \ingroup CMSIS_core_register 382 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 383 \brief Type definitions for the NVIC Registers 384 @{ 385 */ 386 387 /** 388 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 389 */ 390 typedef struct { 391 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 392 uint32_t RESERVED0[24U]; 393 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 394 uint32_t RSERVED1[24U]; 395 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 396 uint32_t RESERVED2[24U]; 397 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 398 uint32_t RESERVED3[24U]; 399 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 400 uint32_t RESERVED4[56U]; 401 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 402 uint32_t RESERVED5[644U]; 403 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 404 } NVIC_Type; 405 406 /* Software Triggered Interrupt Register Definitions */ 407 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 408 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 409 410 /*@} end of group CMSIS_NVIC */ 411 412 /** 413 \ingroup CMSIS_core_register 414 \defgroup CMSIS_SCB System Control Block (SCB) 415 \brief Type definitions for the System Control Block Registers 416 @{ 417 */ 418 419 /** 420 \brief Structure type to access the System Control Block (SCB). 421 */ 422 typedef struct { 423 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 424 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 425 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 426 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 427 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 428 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 429 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 430 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 431 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 432 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 433 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 434 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 435 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 436 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 437 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 438 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 439 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 440 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 441 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 442 uint32_t RESERVED0[5U]; 443 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 444 } SCB_Type; 445 446 /* SCB CPUID Register Definitions */ 447 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 448 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 449 450 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 451 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 452 453 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 454 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 455 456 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 457 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 458 459 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 460 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 461 462 /* SCB Interrupt Control State Register Definitions */ 463 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 464 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 465 466 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 467 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 468 469 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 470 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 471 472 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 473 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 474 475 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 476 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 477 478 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 479 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 480 481 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 482 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 483 484 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 485 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 486 487 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 488 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 489 490 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 491 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 492 493 /* SCB Vector Table Offset Register Definitions */ 494 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 495 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 496 497 /* SCB Application Interrupt and Reset Control Register Definitions */ 498 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 499 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 500 501 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 502 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 503 504 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 505 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 506 507 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 508 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 509 510 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 511 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 512 513 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 514 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 515 516 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 517 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 518 519 /* SCB System Control Register Definitions */ 520 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 521 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 522 523 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 524 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 525 526 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 527 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 528 529 /* SCB Configuration Control Register Definitions */ 530 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 531 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 532 533 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 534 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 535 536 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 537 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 538 539 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 540 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 541 542 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 543 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 544 545 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 546 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 547 548 /* SCB System Handler Control and State Register Definitions */ 549 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 550 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 551 552 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 553 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 554 555 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 556 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 557 558 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 559 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 560 561 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 562 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 563 564 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 565 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 566 567 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 568 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 569 570 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 571 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 572 573 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 574 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 575 576 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 577 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 578 579 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 580 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 581 582 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 583 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 584 585 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 586 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 587 588 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 589 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 590 591 /* SCB Configurable Fault Status Register Definitions */ 592 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 593 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 594 595 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 596 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 597 598 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 599 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 600 601 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 602 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 603 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 604 605 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 606 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 607 608 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 609 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 610 611 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 612 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 613 614 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 615 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 616 617 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 618 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 619 620 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 621 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 622 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 623 624 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 625 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 626 627 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 628 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 629 630 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 631 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 632 633 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 634 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 635 636 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 637 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 638 639 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 640 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 641 642 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 643 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 644 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 645 646 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 647 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 648 649 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 650 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 651 652 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 653 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 654 655 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 656 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 657 658 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 659 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 660 661 /* SCB Hard Fault Status Register Definitions */ 662 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 663 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 664 665 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 666 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 667 668 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 669 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 670 671 /* SCB Debug Fault Status Register Definitions */ 672 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 673 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 674 675 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 676 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 677 678 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 679 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 680 681 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 682 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 683 684 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 685 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 686 687 /*@} end of group CMSIS_SCB */ 688 689 /** 690 \ingroup CMSIS_core_register 691 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 692 \brief Type definitions for the System Control and ID Register not in the SCB 693 @{ 694 */ 695 696 /** 697 \brief Structure type to access the System Control and ID Register not in the SCB. 698 */ 699 typedef struct { 700 uint32_t RESERVED0[1U]; 701 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 702 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 703 } SCnSCB_Type; 704 705 /* Interrupt Controller Type Register Definitions */ 706 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 707 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 708 709 /* Auxiliary Control Register Definitions */ 710 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ 711 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ 712 713 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ 714 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ 715 716 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 717 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 718 719 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ 720 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 721 722 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 723 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 724 725 /*@} end of group CMSIS_SCnotSCB */ 726 727 /** 728 \ingroup CMSIS_core_register 729 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 730 \brief Type definitions for the System Timer Registers. 731 @{ 732 */ 733 734 /** 735 \brief Structure type to access the System Timer (SysTick). 736 */ 737 typedef struct { 738 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 739 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 740 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 741 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 742 } SysTick_Type; 743 744 /* SysTick Control / Status Register Definitions */ 745 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 746 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 747 748 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 749 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 750 751 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 752 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 753 754 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 755 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 756 757 /* SysTick Reload Register Definitions */ 758 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 759 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 760 761 /* SysTick Current Register Definitions */ 762 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 763 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 764 765 /* SysTick Calibration Register Definitions */ 766 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 767 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 768 769 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 770 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 771 772 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 773 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 774 775 /*@} end of group CMSIS_SysTick */ 776 777 /** 778 \ingroup CMSIS_core_register 779 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 780 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 781 @{ 782 */ 783 784 /** 785 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 786 */ 787 typedef struct { 788 __OM union 789 { 790 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 791 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 792 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 793 } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 794 uint32_t RESERVED0[864U]; 795 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 796 uint32_t RESERVED1[15U]; 797 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 798 uint32_t RESERVED2[15U]; 799 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 800 uint32_t RESERVED3[29U]; 801 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 802 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 803 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 804 uint32_t RESERVED4[43U]; 805 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 806 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 807 uint32_t RESERVED5[6U]; 808 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 809 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 810 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 811 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 812 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 813 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 814 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 815 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 816 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 817 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 818 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 819 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 820 } ITM_Type; 821 822 /* ITM Trace Privilege Register Definitions */ 823 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 824 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 825 826 /* ITM Trace Control Register Definitions */ 827 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 828 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 829 830 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 831 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 832 833 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 834 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 835 836 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 837 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 838 839 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 840 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 841 842 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 843 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 844 845 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 846 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 847 848 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 849 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 850 851 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 852 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 853 854 /* ITM Integration Write Register Definitions */ 855 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 856 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 857 858 /* ITM Integration Read Register Definitions */ 859 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 860 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 861 862 /* ITM Integration Mode Control Register Definitions */ 863 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 864 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 865 866 /* ITM Lock Status Register Definitions */ 867 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 868 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 869 870 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 871 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 872 873 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 874 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 875 876 /*@}*//* end of group CMSIS_ITM */ 877 878 /** 879 \ingroup CMSIS_core_register 880 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 881 \brief Type definitions for the Data Watchpoint and Trace (DWT) 882 @{ 883 */ 884 885 /** 886 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 887 */ 888 typedef struct { 889 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 890 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 891 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 892 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 893 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 894 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 895 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 896 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 897 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 898 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 899 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 900 uint32_t RESERVED0[1U]; 901 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 902 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 903 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 904 uint32_t RESERVED1[1U]; 905 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 906 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 907 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 908 uint32_t RESERVED2[1U]; 909 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 910 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 911 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 912 } DWT_Type; 913 914 /* DWT Control Register Definitions */ 915 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 916 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 917 918 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 919 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 920 921 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 922 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 923 924 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 925 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 926 927 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 928 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 929 930 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 931 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 932 933 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 934 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 935 936 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 937 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 938 939 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 940 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 941 942 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 943 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 944 945 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 946 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 947 948 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 949 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 950 951 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 952 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 953 954 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 955 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 956 957 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 958 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 959 960 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 961 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 962 963 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 964 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 965 966 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 967 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 968 969 /* DWT CPI Count Register Definitions */ 970 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 971 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 972 973 /* DWT Exception Overhead Count Register Definitions */ 974 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 975 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 976 977 /* DWT Sleep Count Register Definitions */ 978 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 979 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 980 981 /* DWT LSU Count Register Definitions */ 982 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 983 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 984 985 /* DWT Folded-instruction Count Register Definitions */ 986 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 987 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 988 989 /* DWT Comparator Mask Register Definitions */ 990 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 991 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 992 993 /* DWT Comparator Function Register Definitions */ 994 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 995 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 996 997 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 998 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 999 1000 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 1001 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 1002 1003 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 1004 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 1005 1006 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 1007 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 1008 1009 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 1010 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 1011 1012 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 1013 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 1014 1015 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 1016 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 1017 1018 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 1019 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 1020 1021 /*@}*//* end of group CMSIS_DWT */ 1022 1023 /** 1024 \ingroup CMSIS_core_register 1025 \defgroup CMSIS_TPI Trace Port Interface (TPI) 1026 \brief Type definitions for the Trace Port Interface (TPI) 1027 @{ 1028 */ 1029 1030 /** 1031 \brief Structure type to access the Trace Port Interface Register (TPI). 1032 */ 1033 typedef struct { 1034 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 1035 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 1036 uint32_t RESERVED0[2U]; 1037 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 1038 uint32_t RESERVED1[55U]; 1039 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 1040 uint32_t RESERVED2[131U]; 1041 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 1042 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 1043 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 1044 uint32_t RESERVED3[759U]; 1045 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1046 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1047 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1048 uint32_t RESERVED4[1U]; 1049 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1050 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1051 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1052 uint32_t RESERVED5[39U]; 1053 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1054 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1055 uint32_t RESERVED7[8U]; 1056 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1057 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1058 } TPI_Type; 1059 1060 /* TPI Asynchronous Clock Prescaler Register Definitions */ 1061 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 1062 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 1063 1064 /* TPI Selected Pin Protocol Register Definitions */ 1065 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 1066 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 1067 1068 /* TPI Formatter and Flush Status Register Definitions */ 1069 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 1070 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 1071 1072 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 1073 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 1074 1075 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 1076 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 1077 1078 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 1079 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 1080 1081 /* TPI Formatter and Flush Control Register Definitions */ 1082 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 1083 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 1084 1085 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 1086 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 1087 1088 /* TPI TRIGGER Register Definitions */ 1089 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 1090 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 1091 1092 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1093 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 1094 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 1095 1096 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 1097 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 1098 1099 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 1100 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 1101 1102 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 1103 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 1104 1105 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 1106 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 1107 1108 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 1109 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 1110 1111 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 1112 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 1113 1114 /* TPI ITATBCTR2 Register Definitions */ 1115 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ 1116 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ 1117 1118 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ 1119 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ 1120 1121 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1122 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 1123 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 1124 1125 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 1126 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 1127 1128 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 1129 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 1130 1131 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 1132 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 1133 1134 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 1135 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 1136 1137 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 1138 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 1139 1140 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 1141 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 1142 1143 /* TPI ITATBCTR0 Register Definitions */ 1144 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ 1145 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ 1146 1147 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ 1148 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ 1149 1150 /* TPI Integration Mode Control Register Definitions */ 1151 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 1152 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 1153 1154 /* TPI DEVID Register Definitions */ 1155 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 1156 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1157 1158 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 1159 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1160 1161 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 1162 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1163 1164 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 1165 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 1166 1167 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 1168 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 1169 1170 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 1171 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 1172 1173 /* TPI DEVTYPE Register Definitions */ 1174 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 1175 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 1176 1177 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 1178 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1179 1180 /*@}*//* end of group CMSIS_TPI */ 1181 1182 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1183 /** 1184 \ingroup CMSIS_core_register 1185 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1186 \brief Type definitions for the Memory Protection Unit (MPU) 1187 @{ 1188 */ 1189 1190 /** 1191 \brief Structure type to access the Memory Protection Unit (MPU). 1192 */ 1193 typedef struct 1194 { 1195 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1196 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1197 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1198 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 1199 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 1200 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 1201 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 1202 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 1203 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 1204 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 1205 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 1206 } MPU_Type; 1207 1208 #define MPU_TYPE_RALIASES 4U 1209 1210 /* MPU Type Register Definitions */ 1211 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 1212 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 1213 1214 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 1215 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 1216 1217 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 1218 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 1219 1220 /* MPU Control Register Definitions */ 1221 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 1222 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 1223 1224 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 1225 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 1226 1227 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 1228 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 1229 1230 /* MPU Region Number Register Definitions */ 1231 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 1232 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 1233 1234 /* MPU Region Base Address Register Definitions */ 1235 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1236 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1237 1238 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1239 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1240 1241 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1242 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 1243 1244 /* MPU Region Attribute and Size Register Definitions */ 1245 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1246 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1247 1248 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1249 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1250 1251 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1252 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1253 1254 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1255 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1256 1257 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 1258 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 1259 1260 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 1261 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 1262 1263 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 1264 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 1265 1266 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 1267 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 1268 1269 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 1270 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 1271 1272 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 1273 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 1274 1275 /*@} end of group CMSIS_MPU */ 1276 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 1277 1278 /** 1279 \ingroup CMSIS_core_register 1280 \defgroup CMSIS_FPU Floating Point Unit (FPU) 1281 \brief Type definitions for the Floating Point Unit (FPU) 1282 @{ 1283 */ 1284 1285 /** 1286 \brief Structure type to access the Floating Point Unit (FPU). 1287 */ 1288 typedef struct { 1289 uint32_t RESERVED0[1U]; 1290 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 1291 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 1292 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 1293 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 1294 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 1295 } FPU_Type; 1296 1297 /* Floating-Point Context Control Register Definitions */ 1298 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1299 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1300 1301 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1302 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1303 1304 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 1305 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 1306 1307 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 1308 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 1309 1310 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 1311 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 1312 1313 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 1314 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 1315 1316 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 1317 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 1318 1319 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 1320 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 1321 1322 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 1323 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 1324 1325 /* Floating-Point Context Address Register Definitions */ 1326 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 1327 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 1328 1329 /* Floating-Point Default Status Control Register Definitions */ 1330 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 1331 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 1332 1333 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 1334 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 1335 1336 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 1337 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 1338 1339 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 1340 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 1341 1342 /* Media and FP Feature Register 0 Definitions */ 1343 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 1344 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 1345 1346 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 1347 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 1348 1349 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 1350 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 1351 1352 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 1353 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 1354 1355 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 1356 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 1357 1358 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 1359 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 1360 1361 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 1362 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 1363 1364 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 1365 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 1366 1367 /* Media and FP Feature Register 1 Definitions */ 1368 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 1369 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 1370 1371 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1372 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1373 1374 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1375 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1376 1377 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1378 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 1379 1380 /*@} end of group CMSIS_FPU */ 1381 1382 /** 1383 \ingroup CMSIS_core_register 1384 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1385 \brief Type definitions for the Core Debug Registers 1386 @{ 1387 */ 1388 1389 /** 1390 \brief Structure type to access the Core Debug Register (CoreDebug). 1391 */ 1392 typedef struct { 1393 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1394 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1395 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1396 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1397 } CoreDebug_Type; 1398 1399 /* Debug Halting Control and Status Register Definitions */ 1400 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 1401 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1402 1403 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1404 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1405 1406 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1407 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1408 1409 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1410 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1411 1412 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 1413 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1414 1415 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 1416 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1417 1418 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 1419 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1420 1421 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 1422 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 1423 1424 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1425 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1426 1427 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 1428 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1429 1430 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 1431 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1432 1433 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1434 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1435 1436 /* Debug Core Register Selector Register Definitions */ 1437 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 1438 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1439 1440 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 1441 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 1442 1443 /* Debug Exception and Monitor Control Register Definitions */ 1444 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 1445 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 1446 1447 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 1448 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 1449 1450 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 1451 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 1452 1453 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 1454 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 1455 1456 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 1457 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 1458 1459 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1460 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1461 1462 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 1463 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 1464 1465 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 1466 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 1467 1468 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 1469 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 1470 1471 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 1472 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 1473 1474 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 1475 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 1476 1477 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 1478 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 1479 1480 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1481 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1482 1483 /*@} end of group CMSIS_CoreDebug */ 1484 1485 /** 1486 \ingroup CMSIS_core_register 1487 \defgroup CMSIS_core_bitfield Core register bit field macros 1488 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1489 @{ 1490 */ 1491 1492 /** 1493 \brief Mask and shift a bit field value for use in a register bit range. 1494 \param[in] field Name of the register bit field. 1495 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1496 \return Masked and shifted value. 1497 */ 1498 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1499 1500 /** 1501 \brief Mask and shift a register value to extract a bit filed value. 1502 \param[in] field Name of the register bit field. 1503 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1504 \return Masked and shifted bit field value. 1505 */ 1506 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1507 1508 /*@} end of group CMSIS_core_bitfield */ 1509 1510 /** 1511 \ingroup CMSIS_core_register 1512 \defgroup CMSIS_core_base Core Definitions 1513 \brief Definitions for base addresses, unions, and structures. 1514 @{ 1515 */ 1516 1517 /* Memory mapping of Core Hardware */ 1518 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1519 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1520 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1521 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1522 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1523 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1524 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1525 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1526 1527 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 1528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1531 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 1532 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1533 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1534 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 1535 1536 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1537 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1538 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1539 #endif 1540 1541 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1542 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1543 1544 /*@} */ 1545 1546 /******************************************************************************* 1547 * Hardware Abstraction Layer 1548 Core Function Interface contains: 1549 - Core NVIC Functions 1550 - Core SysTick Functions 1551 - Core Debug Functions 1552 - Core Register Access Functions 1553 ******************************************************************************/ 1554 /** 1555 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1556 */ 1557 1558 /* ########################## NVIC functions #################################### */ 1559 /** 1560 \ingroup CMSIS_Core_FunctionInterface 1561 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1562 \brief Functions that manage interrupts and exceptions via the NVIC. 1563 @{ 1564 */ 1565 1566 #ifdef CMSIS_NVIC_VIRTUAL 1567 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1568 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1569 #endif 1570 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1571 #else 1572 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1573 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1574 #define NVIC_EnableIRQ __NVIC_EnableIRQ 1575 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1576 #define NVIC_DisableIRQ __NVIC_DisableIRQ 1577 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1578 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1579 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1580 #define NVIC_GetActive __NVIC_GetActive 1581 #define NVIC_SetPriority __NVIC_SetPriority 1582 #define NVIC_GetPriority __NVIC_GetPriority 1583 #define NVIC_SystemReset __NVIC_SystemReset 1584 #endif /* CMSIS_NVIC_VIRTUAL */ 1585 1586 #ifdef CMSIS_VECTAB_VIRTUAL 1587 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1588 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1589 #endif 1590 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1591 #else 1592 #define NVIC_SetVector __NVIC_SetVector 1593 #define NVIC_GetVector __NVIC_GetVector 1594 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1595 1596 #define NVIC_USER_IRQ_OFFSET 16 1597 1598 /* The following EXC_RETURN values are saved the LR on exception entry */ 1599 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 1600 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 1601 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 1602 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ 1603 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ 1604 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ 1605 1606 /** 1607 \brief Set Priority Grouping 1608 \details Sets the priority grouping field using the required unlock sequence. 1609 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1610 Only values from 0..7 are used. 1611 In case of a conflict between priority grouping and available 1612 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1613 \param [in] PriorityGroup Priority grouping field. 1614 */ 1615 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1616 { 1617 uint32_t reg_value; 1618 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1619 1620 reg_value = SCB->AIRCR; /* read old register configuration */ 1621 reg_value &= ~((uint32_t) (SCB_AIRCR_VECTKEY_Msk 1622 | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 1623 reg_value = (reg_value | ((uint32_t) 0x5FAUL << SCB_AIRCR_VECTKEY_Pos) 1624 | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */ 1625 SCB->AIRCR = reg_value; 1626 } 1627 1628 /** 1629 \brief Get Priority Grouping 1630 \details Reads the priority grouping field from the NVIC Interrupt Controller. 1631 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1632 */ 1633 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1634 { 1635 return ((uint32_t) ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) 1636 >> SCB_AIRCR_PRIGROUP_Pos)); 1637 } 1638 1639 /** 1640 \brief Enable Interrupt 1641 \details Enables a device specific interrupt in the NVIC interrupt controller. 1642 \param [in] IRQn Device specific interrupt number. 1643 \note IRQn must not be negative. 1644 */ 1645 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1646 { 1647 if ((int32_t) (IRQn) >= 0) { 1648 NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1649 << (((uint32_t) IRQn) & 0x1FUL)); 1650 } 1651 } 1652 1653 /** 1654 \brief Get Interrupt Enable status 1655 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1656 \param [in] IRQn Device specific interrupt number. 1657 \return 0 Interrupt is not enabled. 1658 \return 1 Interrupt is enabled. 1659 \note IRQn must not be negative. 1660 */ 1661 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1662 { 1663 if ((int32_t) (IRQn) >= 0) { 1664 return ((uint32_t) ( 1665 ((NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] 1666 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1667 1UL : 0UL)); 1668 } else { 1669 return (0U); 1670 } 1671 } 1672 1673 /** 1674 \brief Disable Interrupt 1675 \details Disables a device specific interrupt in the NVIC interrupt controller. 1676 \param [in] IRQn Device specific interrupt number. 1677 \note IRQn must not be negative. 1678 */ 1679 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1680 { 1681 if ((int32_t) (IRQn) >= 0) { 1682 NVIC->ICER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1683 << (((uint32_t) IRQn) & 0x1FUL)); 1684 __DSB(); 1685 __ISB(); 1686 } 1687 } 1688 1689 /** 1690 \brief Get Pending Interrupt 1691 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 1692 \param [in] IRQn Device specific interrupt number. 1693 \return 0 Interrupt status is not pending. 1694 \return 1 Interrupt status is pending. 1695 \note IRQn must not be negative. 1696 */ 1697 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1698 { 1699 if ((int32_t) (IRQn) >= 0) { 1700 return ((uint32_t) ( 1701 ((NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] 1702 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1703 1UL : 0UL)); 1704 } else { 1705 return (0U); 1706 } 1707 } 1708 1709 /** 1710 \brief Set Pending Interrupt 1711 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1712 \param [in] IRQn Device specific interrupt number. 1713 \note IRQn must not be negative. 1714 */ 1715 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1716 { 1717 if ((int32_t) (IRQn) >= 0) { 1718 NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1719 << (((uint32_t) IRQn) & 0x1FUL)); 1720 } 1721 } 1722 1723 /** 1724 \brief Clear Pending Interrupt 1725 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1726 \param [in] IRQn Device specific interrupt number. 1727 \note IRQn must not be negative. 1728 */ 1729 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1730 { 1731 if ((int32_t) (IRQn) >= 0) { 1732 NVIC->ICPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1733 << (((uint32_t) IRQn) & 0x1FUL)); 1734 } 1735 } 1736 1737 /** 1738 \brief Get Active Interrupt 1739 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 1740 \param [in] IRQn Device specific interrupt number. 1741 \return 0 Interrupt status is not active. 1742 \return 1 Interrupt status is active. 1743 \note IRQn must not be negative. 1744 */ 1745 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1746 { 1747 if ((int32_t) (IRQn) >= 0) { 1748 return ((uint32_t) ( 1749 ((NVIC->IABR[(((uint32_t) IRQn) >> 5UL)] 1750 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1751 1UL : 0UL)); 1752 } else { 1753 return (0U); 1754 } 1755 } 1756 1757 /** 1758 \brief Set Interrupt Priority 1759 \details Sets the priority of a device specific interrupt or a processor exception. 1760 The interrupt number can be positive to specify a device specific interrupt, 1761 or negative to specify a processor exception. 1762 \param [in] IRQn Interrupt number. 1763 \param [in] priority Priority to set. 1764 \note The priority cannot be set for every processor exception. 1765 */ 1766 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1767 { 1768 if ((int32_t) (IRQn) >= 0) { 1769 NVIC->IP[((uint32_t) IRQn)] = (uint8_t) ((priority 1770 << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL); 1771 } else { 1772 SCB->SHP[(((uint32_t) IRQn) & 0xFUL) - 4UL] = (uint8_t) ((priority 1773 << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL); 1774 } 1775 } 1776 1777 /** 1778 \brief Get Interrupt Priority 1779 \details Reads the priority of a device specific interrupt or a processor exception. 1780 The interrupt number can be positive to specify a device specific interrupt, 1781 or negative to specify a processor exception. 1782 \param [in] IRQn Interrupt number. 1783 \return Interrupt Priority. 1784 Value is aligned automatically to the implemented priority bits of the microcontroller. 1785 */ 1786 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1787 { 1788 1789 if ((int32_t) (IRQn) >= 0) { 1790 return (((uint32_t) NVIC->IP[((uint32_t) IRQn)] 1791 >> (8U - __NVIC_PRIO_BITS))); 1792 } else { 1793 return (((uint32_t) SCB->SHP[(((uint32_t) IRQn) & 0xFUL) - 4UL] 1794 >> (8U - __NVIC_PRIO_BITS))); 1795 } 1796 } 1797 1798 /** 1799 \brief Encode Priority 1800 \details Encodes the priority for an interrupt with the given priority group, 1801 preemptive priority value, and subpriority value. 1802 In case of a conflict between priority grouping and available 1803 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1804 \param [in] PriorityGroup Used priority group. 1805 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1806 \param [in] SubPriority Subpriority value (starting from 0). 1807 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1808 */ 1809 __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, 1810 uint32_t PreemptPriority, uint32_t SubPriority) 1811 { 1812 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1813 uint32_t PreemptPriorityBits; 1814 uint32_t SubPriorityBits; 1815 1816 PreemptPriorityBits = 1817 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 1818 (uint32_t) (__NVIC_PRIO_BITS) : 1819 (uint32_t) (7UL - PriorityGroupTmp); 1820 SubPriorityBits = 1821 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) 1822 < (uint32_t) 7UL) ? 1823 (uint32_t) 0UL : 1824 (uint32_t) ((PriorityGroupTmp - 7UL) 1825 + (uint32_t) (__NVIC_PRIO_BITS)); 1826 1827 return (((PreemptPriority 1828 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL)) 1829 << SubPriorityBits) 1830 | ((SubPriority & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL)))); 1831 } 1832 1833 /** 1834 \brief Decode Priority 1835 \details Decodes an interrupt priority value with a given priority group to 1836 preemptive priority value and subpriority value. 1837 In case of a conflict between priority grouping and available 1838 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1839 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1840 \param [in] PriorityGroup Used priority group. 1841 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1842 \param [out] pSubPriority Subpriority value (starting from 0). 1843 */ 1844 __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, 1845 uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 1846 uint32_t *const pSubPriority) 1847 { 1848 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1849 uint32_t PreemptPriorityBits; 1850 uint32_t SubPriorityBits; 1851 1852 PreemptPriorityBits = 1853 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 1854 (uint32_t) (__NVIC_PRIO_BITS) : 1855 (uint32_t) (7UL - PriorityGroupTmp); 1856 SubPriorityBits = 1857 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) 1858 < (uint32_t) 7UL) ? 1859 (uint32_t) 0UL : 1860 (uint32_t) ((PriorityGroupTmp - 7UL) 1861 + (uint32_t) (__NVIC_PRIO_BITS)); 1862 1863 *pPreemptPriority = (Priority >> SubPriorityBits) 1864 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL); 1865 *pSubPriority = (Priority) 1866 & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL); 1867 } 1868 1869 /** 1870 \brief Set Interrupt Vector 1871 \details Sets an interrupt vector in SRAM based interrupt vector table. 1872 The interrupt number can be positive to specify a device specific interrupt, 1873 or negative to specify a processor exception. 1874 VTOR must been relocated to SRAM before. 1875 \param [in] IRQn Interrupt number 1876 \param [in] vector Address of interrupt handler function 1877 */ 1878 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 1879 { 1880 uint32_t *vectors = (uint32_t*) SCB->VTOR; 1881 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 1882 } 1883 1884 /** 1885 \brief Get Interrupt Vector 1886 \details Reads an interrupt vector from interrupt vector table. 1887 The interrupt number can be positive to specify a device specific interrupt, 1888 or negative to specify a processor exception. 1889 \param [in] IRQn Interrupt number. 1890 \return Address of interrupt handler function 1891 */ 1892 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 1893 { 1894 uint32_t *vectors = (uint32_t*) SCB->VTOR; 1895 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 1896 } 1897 1898 /** 1899 \brief System Reset 1900 \details Initiates a system reset request to reset the MCU. 1901 */ 1902 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 1903 { 1904 __DSB(); /* Ensure all outstanding memory accesses included 1905 buffered write are completed before reset */ 1906 SCB->AIRCR = (uint32_t) ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) 1907 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 1908 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 1909 __DSB(); /* Ensure completion of memory access */ 1910 1911 for (;;) /* wait until reset */ 1912 { 1913 __NOP(); 1914 } 1915 } 1916 1917 /*@} end of CMSIS_Core_NVICFunctions */ 1918 1919 /* ########################## MPU functions #################################### */ 1920 1921 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1922 1923 #include "mpu_armv7.h" 1924 1925 #endif 1926 1927 /* ########################## FPU functions #################################### */ 1928 /** 1929 \ingroup CMSIS_Core_FunctionInterface 1930 \defgroup CMSIS_Core_FpuFunctions FPU Functions 1931 \brief Function that provides FPU type. 1932 @{ 1933 */ 1934 1935 /** 1936 \brief get FPU type 1937 \details returns the FPU type 1938 \returns 1939 - \b 0: No FPU 1940 - \b 1: Single precision FPU 1941 - \b 2: Double + Single precision FPU 1942 */ 1943 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 1944 { 1945 uint32_t mvfr0; 1946 1947 mvfr0 = FPU->MVFR0; 1948 if ((mvfr0 1949 & (FPU_MVFR0_Single_precision_Msk 1950 | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { 1951 return 1U; /* Single precision FPU */ 1952 } else { 1953 return 0U; /* No FPU */ 1954 } 1955 } 1956 1957 /*@} end of CMSIS_Core_FpuFunctions */ 1958 1959 /* ################################## SysTick function ############################################ */ 1960 /** 1961 \ingroup CMSIS_Core_FunctionInterface 1962 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 1963 \brief Functions that configure the System. 1964 @{ 1965 */ 1966 1967 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 1968 1969 /** 1970 \brief System Tick Configuration 1971 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 1972 Counter is in free running mode to generate periodic interrupts. 1973 \param [in] ticks Number of ticks between two interrupts. 1974 \return 0 Function succeeded. 1975 \return 1 Function failed. 1976 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1977 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 1978 must contain a vendor-specific implementation of this function. 1979 */ 1980 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 1981 { 1982 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1983 { 1984 return (1UL); /* Reload value impossible */ 1985 } 1986 1987 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1988 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1989 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 1990 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1991 SysTick_CTRL_TICKINT_Msk | 1992 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1993 return (0UL); /* Function successful */ 1994 } 1995 1996 #endif 1997 1998 /*@} end of CMSIS_Core_SysTickFunctions */ 1999 2000 /* ##################################### Debug In/Output function ########################################### */ 2001 /** 2002 \ingroup CMSIS_Core_FunctionInterface 2003 \defgroup CMSIS_core_DebugFunctions ITM Functions 2004 \brief Functions that access the ITM debug interface. 2005 @{ 2006 */ 2007 2008 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 2009 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 2010 2011 /** 2012 \brief ITM Send Character 2013 \details Transmits a character via the ITM channel 0, and 2014 \li Just returns when no debugger is connected that has booked the output. 2015 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 2016 \param [in] ch Character to transmit. 2017 \returns Character to transmit. 2018 */ 2019 __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) 2020 { 2021 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 2022 ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ 2023 { 2024 while (ITM->PORT[0U].u32 == 0UL) { 2025 __NOP(); 2026 } 2027 ITM->PORT[0U].u8 = (uint8_t) ch; 2028 } 2029 return (ch); 2030 } 2031 2032 /** 2033 \brief ITM Receive Character 2034 \details Inputs a character via the external variable \ref ITM_RxBuffer. 2035 \return Received character. 2036 \return -1 No character pending. 2037 */ 2038 __STATIC_INLINE int32_t ITM_ReceiveChar(void) 2039 { 2040 int32_t ch = -1; /* no character available */ 2041 2042 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 2043 ch = ITM_RxBuffer; 2044 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 2045 } 2046 2047 return (ch); 2048 } 2049 2050 /** 2051 \brief ITM Check Character 2052 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 2053 \return 0 No character available. 2054 \return 1 Character available. 2055 */ 2056 __STATIC_INLINE int32_t ITM_CheckChar(void) 2057 { 2058 2059 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 2060 return (0); /* no character available */ 2061 } else { 2062 return (1); /* character available */ 2063 } 2064 } 2065 2066 /*@} end of CMSIS_core_DebugFunctions */ 2067 2068 #ifdef __cplusplus 2069 } 2070 #endif 2071 2072 #endif /* __CORE_CM4_H_DEPENDANT */ 2073 2074 #endif /* __CMSIS_GENERIC */