Drivers/CMSIS/Include/core_cm1.h (42572B)
1 /**************************************************************************//** 2 * @file core_cm1.h 3 * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File 4 * @version V1.0.0 5 * @date 23. July 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_CM1_H_GENERIC 32 #define __CORE_CM1_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup Cortex_M1 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS CM1 definitions */ 65 #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ 68 __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_M (1U) /*!< Cortex-M Core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 This core does not support an FPU at all 74 */ 75 #define __FPU_USED 0U 76 77 #if defined ( __CC_ARM ) 78 #if defined __TARGET_FPU_VFP 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 80 #endif 81 82 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 83 #if defined __ARM_PCS_VFP 84 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 85 #endif 86 87 #elif defined ( __GNUC__ ) 88 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 90 #endif 91 92 #elif defined ( __ICCARM__ ) 93 #if defined __ARMVFP__ 94 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 95 #endif 96 97 #elif defined ( __TI_ARM__ ) 98 #if defined __TI_VFP_SUPPORT__ 99 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 100 #endif 101 102 #elif defined ( __TASKING__ ) 103 #if defined __FPU_VFP__ 104 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 105 #endif 106 107 #elif defined ( __CSMC__ ) 108 #if ( __CSMC__ & 0x400U) 109 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 110 #endif 111 112 #endif 113 114 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 115 116 #ifdef __cplusplus 117 } 118 #endif 119 120 #endif /* __CORE_CM1_H_GENERIC */ 121 122 #ifndef __CMSIS_GENERIC 123 124 #ifndef __CORE_CM1_H_DEPENDANT 125 #define __CORE_CM1_H_DEPENDANT 126 127 #ifdef __cplusplus 128 extern "C" { 129 #endif 130 131 /* check device defines and use defaults */ 132 #if defined __CHECK_DEVICE_DEFINES 133 #ifndef __CM1_REV 134 #define __CM1_REV 0x0100U 135 #warning "__CM1_REV not defined in device header file; using default!" 136 #endif 137 138 #ifndef __NVIC_PRIO_BITS 139 #define __NVIC_PRIO_BITS 2U 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 141 #endif 142 143 #ifndef __Vendor_SysTickConfig 144 #define __Vendor_SysTickConfig 0U 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 146 #endif 147 #endif 148 149 /* IO definitions (access restrictions to peripheral registers) */ 150 /** 151 \defgroup CMSIS_glob_defs CMSIS Global Defines 152 153 <strong>IO Type Qualifiers</strong> are used 154 \li to specify the access to peripheral variables. 155 \li for automatic generation of peripheral register debug information. 156 */ 157 #ifdef __cplusplus 158 #define __I volatile /*!< Defines 'read only' permissions */ 159 #else 160 #define __I volatile const /*!< Defines 'read only' permissions */ 161 #endif 162 #define __O volatile /*!< Defines 'write only' permissions */ 163 #define __IO volatile /*!< Defines 'read / write' permissions */ 164 165 /* following defines should be used for structure members */ 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 167 #define __OM volatile /*! Defines 'write only' structure member permissions */ 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 169 170 /*@} end of group Cortex_M1 */ 171 172 /******************************************************************************* 173 * Register Abstraction 174 Core Register contain: 175 - Core Register 176 - Core NVIC Register 177 - Core SCB Register 178 - Core SysTick Register 179 ******************************************************************************/ 180 /** 181 \defgroup CMSIS_core_register Defines and Type Definitions 182 \brief Type definitions and defines for Cortex-M processor based devices. 183 */ 184 185 /** 186 \ingroup CMSIS_core_register 187 \defgroup CMSIS_CORE Status and Control Registers 188 \brief Core Register type definitions. 189 @{ 190 */ 191 192 /** 193 \brief Union type to access the Application Program Status Register (APSR). 194 */ 195 typedef union { 196 struct { 197 uint32_t _reserved0 :28; /*!< bit: 0..27 Reserved */ 198 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 199 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 200 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 201 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 202 } b; /*!< Structure used for bit access */ 203 uint32_t w; /*!< Type used for word access */ 204 } APSR_Type; 205 206 /* APSR Register Definitions */ 207 #define APSR_N_Pos 31U /*!< APSR: N Position */ 208 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 209 210 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 211 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 212 213 #define APSR_C_Pos 29U /*!< APSR: C Position */ 214 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 215 216 #define APSR_V_Pos 28U /*!< APSR: V Position */ 217 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 218 219 /** 220 \brief Union type to access the Interrupt Program Status Register (IPSR). 221 */ 222 typedef union { 223 struct { 224 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 225 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 226 } b; /*!< Structure used for bit access */ 227 uint32_t w; /*!< Type used for word access */ 228 } IPSR_Type; 229 230 /* IPSR Register Definitions */ 231 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 232 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 233 234 /** 235 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 236 */ 237 typedef union { 238 struct { 239 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 240 uint32_t _reserved0 :15; /*!< bit: 9..23 Reserved */ 241 uint32_t T :1; /*!< bit: 24 Thumb bit (read 0) */ 242 uint32_t _reserved1 :3; /*!< bit: 25..27 Reserved */ 243 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 244 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 245 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 246 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 247 } b; /*!< Structure used for bit access */ 248 uint32_t w; /*!< Type used for word access */ 249 } xPSR_Type; 250 251 /* xPSR Register Definitions */ 252 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 253 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 254 255 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 256 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 257 258 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 259 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 260 261 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 262 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 263 264 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 265 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 266 267 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 268 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 269 270 /** 271 \brief Union type to access the Control Registers (CONTROL). 272 */ 273 typedef union { 274 struct { 275 uint32_t _reserved0 :1; /*!< bit: 0 Reserved */ 276 uint32_t SPSEL :1; /*!< bit: 1 Stack to be used */ 277 uint32_t _reserved1 :30; /*!< bit: 2..31 Reserved */ 278 } b; /*!< Structure used for bit access */ 279 uint32_t w; /*!< Type used for word access */ 280 } CONTROL_Type; 281 282 /* CONTROL Register Definitions */ 283 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 284 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 285 286 /*@} end of group CMSIS_CORE */ 287 288 /** 289 \ingroup CMSIS_core_register 290 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 291 \brief Type definitions for the NVIC Registers 292 @{ 293 */ 294 295 /** 296 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 297 */ 298 typedef struct { 299 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 300 uint32_t RESERVED0[31U]; 301 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 302 uint32_t RSERVED1[31U]; 303 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 304 uint32_t RESERVED2[31U]; 305 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 306 uint32_t RESERVED3[31U]; 307 uint32_t RESERVED4[64U]; 308 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 309 } NVIC_Type; 310 311 /*@} end of group CMSIS_NVIC */ 312 313 /** 314 \ingroup CMSIS_core_register 315 \defgroup CMSIS_SCB System Control Block (SCB) 316 \brief Type definitions for the System Control Block Registers 317 @{ 318 */ 319 320 /** 321 \brief Structure type to access the System Control Block (SCB). 322 */ 323 typedef struct { 324 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 325 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 326 uint32_t RESERVED0; 327 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 328 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 329 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 330 uint32_t RESERVED1; 331 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 332 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 333 } SCB_Type; 334 335 /* SCB CPUID Register Definitions */ 336 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 337 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 338 339 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 340 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 341 342 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 343 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 344 345 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 346 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 347 348 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 349 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 350 351 /* SCB Interrupt Control State Register Definitions */ 352 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 353 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 354 355 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 356 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 357 358 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 359 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 360 361 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 362 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 363 364 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 365 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 366 367 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 368 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 369 370 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 371 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 372 373 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 374 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 375 376 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 377 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 378 379 /* SCB Application Interrupt and Reset Control Register Definitions */ 380 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 381 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 382 383 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 384 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 385 386 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 387 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 388 389 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 390 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 391 392 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 393 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 394 395 /* SCB System Control Register Definitions */ 396 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 397 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 398 399 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 400 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 401 402 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 403 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 404 405 /* SCB Configuration Control Register Definitions */ 406 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 407 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 408 409 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 410 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 411 412 /* SCB System Handler Control and State Register Definitions */ 413 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 414 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 415 416 /*@} end of group CMSIS_SCB */ 417 418 /** 419 \ingroup CMSIS_core_register 420 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 421 \brief Type definitions for the System Control and ID Register not in the SCB 422 @{ 423 */ 424 425 /** 426 \brief Structure type to access the System Control and ID Register not in the SCB. 427 */ 428 typedef struct { 429 uint32_t RESERVED0[2U]; 430 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 431 } SCnSCB_Type; 432 433 /* Auxiliary Control Register Definitions */ 434 #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ 435 #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ 436 437 #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ 438 #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ 439 440 /*@} end of group CMSIS_SCnotSCB */ 441 442 /** 443 \ingroup CMSIS_core_register 444 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 445 \brief Type definitions for the System Timer Registers. 446 @{ 447 */ 448 449 /** 450 \brief Structure type to access the System Timer (SysTick). 451 */ 452 typedef struct { 453 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 454 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 455 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 456 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 457 } SysTick_Type; 458 459 /* SysTick Control / Status Register Definitions */ 460 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 461 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 462 463 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 464 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 465 466 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 467 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 468 469 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 470 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 471 472 /* SysTick Reload Register Definitions */ 473 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 474 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 475 476 /* SysTick Current Register Definitions */ 477 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 478 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 479 480 /* SysTick Calibration Register Definitions */ 481 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 482 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 483 484 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 485 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 486 487 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 488 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 489 490 /*@} end of group CMSIS_SysTick */ 491 492 /** 493 \ingroup CMSIS_core_register 494 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 495 \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 496 Therefore they are not covered by the Cortex-M1 header file. 497 @{ 498 */ 499 /*@} end of group CMSIS_CoreDebug */ 500 501 /** 502 \ingroup CMSIS_core_register 503 \defgroup CMSIS_core_bitfield Core register bit field macros 504 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 505 @{ 506 */ 507 508 /** 509 \brief Mask and shift a bit field value for use in a register bit range. 510 \param[in] field Name of the register bit field. 511 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 512 \return Masked and shifted value. 513 */ 514 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 515 516 /** 517 \brief Mask and shift a register value to extract a bit filed value. 518 \param[in] field Name of the register bit field. 519 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 520 \return Masked and shifted bit field value. 521 */ 522 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 523 524 /*@} end of group CMSIS_core_bitfield */ 525 526 /** 527 \ingroup CMSIS_core_register 528 \defgroup CMSIS_core_base Core Definitions 529 \brief Definitions for base addresses, unions, and structures. 530 @{ 531 */ 532 533 /* Memory mapping of Core Hardware */ 534 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 535 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 536 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 537 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 538 539 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 540 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 541 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 542 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 543 544 /*@} */ 545 546 /******************************************************************************* 547 * Hardware Abstraction Layer 548 Core Function Interface contains: 549 - Core NVIC Functions 550 - Core SysTick Functions 551 - Core Register Access Functions 552 ******************************************************************************/ 553 /** 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 555 */ 556 557 /* ########################## NVIC functions #################################### */ 558 /** 559 \ingroup CMSIS_Core_FunctionInterface 560 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 561 \brief Functions that manage interrupts and exceptions via the NVIC. 562 @{ 563 */ 564 565 #ifdef CMSIS_NVIC_VIRTUAL 566 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 567 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 568 #endif 569 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 570 #else 571 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 572 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 573 #define NVIC_EnableIRQ __NVIC_EnableIRQ 574 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 575 #define NVIC_DisableIRQ __NVIC_DisableIRQ 576 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 577 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 578 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 579 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ 580 #define NVIC_SetPriority __NVIC_SetPriority 581 #define NVIC_GetPriority __NVIC_GetPriority 582 #define NVIC_SystemReset __NVIC_SystemReset 583 #endif /* CMSIS_NVIC_VIRTUAL */ 584 585 #ifdef CMSIS_VECTAB_VIRTUAL 586 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 587 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 588 #endif 589 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 590 #else 591 #define NVIC_SetVector __NVIC_SetVector 592 #define NVIC_GetVector __NVIC_GetVector 593 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 594 595 #define NVIC_USER_IRQ_OFFSET 16 596 597 /* The following EXC_RETURN values are saved the LR on exception entry */ 598 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 599 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 600 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 601 602 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 603 /* The following MACROS handle generation of the register offset and byte masks */ 604 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 605 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 606 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 607 608 #define __NVIC_SetPriorityGrouping(X) (void)(X) 609 #define __NVIC_GetPriorityGrouping() (0U) 610 611 /** 612 \brief Enable Interrupt 613 \details Enables a device specific interrupt in the NVIC interrupt controller. 614 \param [in] IRQn Device specific interrupt number. 615 \note IRQn must not be negative. 616 */ 617 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 618 { 619 if ((int32_t) (IRQn) >= 0) { 620 NVIC->ISER[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 621 } 622 } 623 624 /** 625 \brief Get Interrupt Enable status 626 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 627 \param [in] IRQn Device specific interrupt number. 628 \return 0 Interrupt is not enabled. 629 \return 1 Interrupt is enabled. 630 \note IRQn must not be negative. 631 */ 632 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 633 { 634 if ((int32_t) (IRQn) >= 0) { 635 return ((uint32_t) ( 636 ((NVIC->ISER[0U] & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 637 1UL : 0UL)); 638 } else { 639 return (0U); 640 } 641 } 642 643 /** 644 \brief Disable Interrupt 645 \details Disables a device specific interrupt in the NVIC interrupt controller. 646 \param [in] IRQn Device specific interrupt number. 647 \note IRQn must not be negative. 648 */ 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 650 { 651 if ((int32_t) (IRQn) >= 0) { 652 NVIC->ICER[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 653 __DSB(); 654 __ISB(); 655 } 656 } 657 658 /** 659 \brief Get Pending Interrupt 660 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 661 \param [in] IRQn Device specific interrupt number. 662 \return 0 Interrupt status is not pending. 663 \return 1 Interrupt status is pending. 664 \note IRQn must not be negative. 665 */ 666 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 667 { 668 if ((int32_t) (IRQn) >= 0) { 669 return ((uint32_t) ( 670 ((NVIC->ISPR[0U] & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 671 1UL : 0UL)); 672 } else { 673 return (0U); 674 } 675 } 676 677 /** 678 \brief Set Pending Interrupt 679 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 680 \param [in] IRQn Device specific interrupt number. 681 \note IRQn must not be negative. 682 */ 683 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 684 { 685 if ((int32_t) (IRQn) >= 0) { 686 NVIC->ISPR[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 687 } 688 } 689 690 /** 691 \brief Clear Pending Interrupt 692 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 693 \param [in] IRQn Device specific interrupt number. 694 \note IRQn must not be negative. 695 */ 696 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 697 { 698 if ((int32_t) (IRQn) >= 0) { 699 NVIC->ICPR[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 700 } 701 } 702 703 /** 704 \brief Set Interrupt Priority 705 \details Sets the priority of a device specific interrupt or a processor exception. 706 The interrupt number can be positive to specify a device specific interrupt, 707 or negative to specify a processor exception. 708 \param [in] IRQn Interrupt number. 709 \param [in] priority Priority to set. 710 \note The priority cannot be set for every processor exception. 711 */ 712 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 713 { 714 if ((int32_t) (IRQn) >= 0) { 715 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t) (NVIC->IP[_IP_IDX(IRQn)] 716 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 717 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 718 << _BIT_SHIFT(IRQn))); 719 } else { 720 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t) (SCB->SHP[_SHP_IDX(IRQn)] 721 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 722 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 723 << _BIT_SHIFT(IRQn))); 724 } 725 } 726 727 /** 728 \brief Get Interrupt Priority 729 \details Reads the priority of a device specific interrupt or a processor exception. 730 The interrupt number can be positive to specify a device specific interrupt, 731 or negative to specify a processor exception. 732 \param [in] IRQn Interrupt number. 733 \return Interrupt Priority. 734 Value is aligned automatically to the implemented priority bits of the microcontroller. 735 */ 736 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 737 { 738 739 if ((int32_t) (IRQn) >= 0) { 740 return ((uint32_t) (((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 741 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 742 } else { 743 return ((uint32_t) (((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 744 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 745 } 746 } 747 748 /** 749 \brief Encode Priority 750 \details Encodes the priority for an interrupt with the given priority group, 751 preemptive priority value, and subpriority value. 752 In case of a conflict between priority grouping and available 753 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 754 \param [in] PriorityGroup Used priority group. 755 \param [in] PreemptPriority Preemptive priority value (starting from 0). 756 \param [in] SubPriority Subpriority value (starting from 0). 757 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 758 */ 759 __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, 760 uint32_t PreemptPriority, uint32_t SubPriority) 761 { 762 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 763 uint32_t PreemptPriorityBits; 764 uint32_t SubPriorityBits; 765 766 PreemptPriorityBits = 767 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 768 (uint32_t) (__NVIC_PRIO_BITS) : 769 (uint32_t) (7UL - PriorityGroupTmp); 770 SubPriorityBits = 771 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) < (uint32_t) 7UL) ? 772 (uint32_t) 0UL : 773 (uint32_t) ((PriorityGroupTmp - 7UL) 774 + (uint32_t) (__NVIC_PRIO_BITS)); 775 776 return (((PreemptPriority 777 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL)) 778 << SubPriorityBits) 779 | ((SubPriority & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL)))); 780 } 781 782 /** 783 \brief Decode Priority 784 \details Decodes an interrupt priority value with a given priority group to 785 preemptive priority value and subpriority value. 786 In case of a conflict between priority grouping and available 787 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 788 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 789 \param [in] PriorityGroup Used priority group. 790 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 791 \param [out] pSubPriority Subpriority value (starting from 0). 792 */ 793 __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, 794 uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 795 uint32_t *const pSubPriority) 796 { 797 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 798 uint32_t PreemptPriorityBits; 799 uint32_t SubPriorityBits; 800 801 PreemptPriorityBits = 802 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 803 (uint32_t) (__NVIC_PRIO_BITS) : 804 (uint32_t) (7UL - PriorityGroupTmp); 805 SubPriorityBits = 806 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) < (uint32_t) 7UL) ? 807 (uint32_t) 0UL : 808 (uint32_t) ((PriorityGroupTmp - 7UL) 809 + (uint32_t) (__NVIC_PRIO_BITS)); 810 811 *pPreemptPriority = (Priority >> SubPriorityBits) 812 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL); 813 *pSubPriority = (Priority) & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL); 814 } 815 816 /** 817 \brief Set Interrupt Vector 818 \details Sets an interrupt vector in SRAM based interrupt vector table. 819 The interrupt number can be positive to specify a device specific interrupt, 820 or negative to specify a processor exception. 821 Address 0 must be mapped to SRAM. 822 \param [in] IRQn Interrupt number 823 \param [in] vector Address of interrupt handler function 824 */ 825 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 826 { 827 uint32_t *vectors = (uint32_t*) 0x0U; 828 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 829 } 830 831 /** 832 \brief Get Interrupt Vector 833 \details Reads an interrupt vector from interrupt vector table. 834 The interrupt number can be positive to specify a device specific interrupt, 835 or negative to specify a processor exception. 836 \param [in] IRQn Interrupt number. 837 \return Address of interrupt handler function 838 */ 839 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 840 { 841 uint32_t *vectors = (uint32_t*) 0x0U; 842 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 843 } 844 845 /** 846 \brief System Reset 847 \details Initiates a system reset request to reset the MCU. 848 */ 849 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 850 { 851 __DSB(); /* Ensure all outstanding memory accesses included 852 buffered write are completed before reset */ 853 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 854 SCB_AIRCR_SYSRESETREQ_Msk); 855 __DSB(); /* Ensure completion of memory access */ 856 857 for (;;) /* wait until reset */ 858 { 859 __NOP(); 860 } 861 } 862 863 /*@} end of CMSIS_Core_NVICFunctions */ 864 865 /* ########################## FPU functions #################################### */ 866 /** 867 \ingroup CMSIS_Core_FunctionInterface 868 \defgroup CMSIS_Core_FpuFunctions FPU Functions 869 \brief Function that provides FPU type. 870 @{ 871 */ 872 873 /** 874 \brief get FPU type 875 \details returns the FPU type 876 \returns 877 - \b 0: No FPU 878 - \b 1: Single precision FPU 879 - \b 2: Double + Single precision FPU 880 */ 881 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 882 { 883 return 0U; /* No FPU */ 884 } 885 886 /*@} end of CMSIS_Core_FpuFunctions */ 887 888 /* ################################## SysTick function ############################################ */ 889 /** 890 \ingroup CMSIS_Core_FunctionInterface 891 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 892 \brief Functions that configure the System. 893 @{ 894 */ 895 896 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 897 898 /** 899 \brief System Tick Configuration 900 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 901 Counter is in free running mode to generate periodic interrupts. 902 \param [in] ticks Number of ticks between two interrupts. 903 \return 0 Function succeeded. 904 \return 1 Function failed. 905 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 906 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 907 must contain a vendor-specific implementation of this function. 908 */ 909 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 910 { 911 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 912 { 913 return (1UL); /* Reload value impossible */ 914 } 915 916 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 917 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 918 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 919 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 920 SysTick_CTRL_TICKINT_Msk | 921 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 922 return (0UL); /* Function successful */ 923 } 924 925 #endif 926 927 /*@} end of CMSIS_Core_SysTickFunctions */ 928 929 #ifdef __cplusplus 930 } 931 #endif 932 933 #endif /* __CORE_CM1_H_DEPENDANT */ 934 935 #endif /* __CMSIS_GENERIC */