Drivers/CMSIS/Include/core_cm0.h (41351B)
1 /**************************************************************************//** 2 * @file core_cm0.h 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File 4 * @version V5.0.5 5 * @date 28. May 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_CM0_H_GENERIC 32 #define __CORE_CM0_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup Cortex_M0 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS CM0 definitions */ 65 #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ 68 __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_M (0U) /*!< Cortex-M Core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 This core does not support an FPU at all 74 */ 75 #define __FPU_USED 0U 76 77 #if defined ( __CC_ARM ) 78 #if defined __TARGET_FPU_VFP 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 80 #endif 81 82 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 83 #if defined __ARM_PCS_VFP 84 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 85 #endif 86 87 #elif defined ( __GNUC__ ) 88 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 90 #endif 91 92 #elif defined ( __ICCARM__ ) 93 #if defined __ARMVFP__ 94 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 95 #endif 96 97 #elif defined ( __TI_ARM__ ) 98 #if defined __TI_VFP_SUPPORT__ 99 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 100 #endif 101 102 #elif defined ( __TASKING__ ) 103 #if defined __FPU_VFP__ 104 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 105 #endif 106 107 #elif defined ( __CSMC__ ) 108 #if ( __CSMC__ & 0x400U) 109 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 110 #endif 111 112 #endif 113 114 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 115 116 #ifdef __cplusplus 117 } 118 #endif 119 120 #endif /* __CORE_CM0_H_GENERIC */ 121 122 #ifndef __CMSIS_GENERIC 123 124 #ifndef __CORE_CM0_H_DEPENDANT 125 #define __CORE_CM0_H_DEPENDANT 126 127 #ifdef __cplusplus 128 extern "C" { 129 #endif 130 131 /* check device defines and use defaults */ 132 #if defined __CHECK_DEVICE_DEFINES 133 #ifndef __CM0_REV 134 #define __CM0_REV 0x0000U 135 #warning "__CM0_REV not defined in device header file; using default!" 136 #endif 137 138 #ifndef __NVIC_PRIO_BITS 139 #define __NVIC_PRIO_BITS 2U 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 141 #endif 142 143 #ifndef __Vendor_SysTickConfig 144 #define __Vendor_SysTickConfig 0U 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 146 #endif 147 #endif 148 149 /* IO definitions (access restrictions to peripheral registers) */ 150 /** 151 \defgroup CMSIS_glob_defs CMSIS Global Defines 152 153 <strong>IO Type Qualifiers</strong> are used 154 \li to specify the access to peripheral variables. 155 \li for automatic generation of peripheral register debug information. 156 */ 157 #ifdef __cplusplus 158 #define __I volatile /*!< Defines 'read only' permissions */ 159 #else 160 #define __I volatile const /*!< Defines 'read only' permissions */ 161 #endif 162 #define __O volatile /*!< Defines 'write only' permissions */ 163 #define __IO volatile /*!< Defines 'read / write' permissions */ 164 165 /* following defines should be used for structure members */ 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 167 #define __OM volatile /*! Defines 'write only' structure member permissions */ 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 169 170 /*@} end of group Cortex_M0 */ 171 172 /******************************************************************************* 173 * Register Abstraction 174 Core Register contain: 175 - Core Register 176 - Core NVIC Register 177 - Core SCB Register 178 - Core SysTick Register 179 ******************************************************************************/ 180 /** 181 \defgroup CMSIS_core_register Defines and Type Definitions 182 \brief Type definitions and defines for Cortex-M processor based devices. 183 */ 184 185 /** 186 \ingroup CMSIS_core_register 187 \defgroup CMSIS_CORE Status and Control Registers 188 \brief Core Register type definitions. 189 @{ 190 */ 191 192 /** 193 \brief Union type to access the Application Program Status Register (APSR). 194 */ 195 typedef union { 196 struct { 197 uint32_t _reserved0 :28; /*!< bit: 0..27 Reserved */ 198 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 199 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 200 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 201 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 202 } b; /*!< Structure used for bit access */ 203 uint32_t w; /*!< Type used for word access */ 204 } APSR_Type; 205 206 /* APSR Register Definitions */ 207 #define APSR_N_Pos 31U /*!< APSR: N Position */ 208 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 209 210 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 211 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 212 213 #define APSR_C_Pos 29U /*!< APSR: C Position */ 214 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 215 216 #define APSR_V_Pos 28U /*!< APSR: V Position */ 217 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 218 219 /** 220 \brief Union type to access the Interrupt Program Status Register (IPSR). 221 */ 222 typedef union { 223 struct { 224 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 225 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 226 } b; /*!< Structure used for bit access */ 227 uint32_t w; /*!< Type used for word access */ 228 } IPSR_Type; 229 230 /* IPSR Register Definitions */ 231 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 232 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 233 234 /** 235 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 236 */ 237 typedef union { 238 struct { 239 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 240 uint32_t _reserved0 :15; /*!< bit: 9..23 Reserved */ 241 uint32_t T :1; /*!< bit: 24 Thumb bit (read 0) */ 242 uint32_t _reserved1 :3; /*!< bit: 25..27 Reserved */ 243 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 244 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 245 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 246 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 247 } b; /*!< Structure used for bit access */ 248 uint32_t w; /*!< Type used for word access */ 249 } xPSR_Type; 250 251 /* xPSR Register Definitions */ 252 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 253 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 254 255 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 256 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 257 258 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 259 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 260 261 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 262 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 263 264 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 265 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 266 267 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 268 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 269 270 /** 271 \brief Union type to access the Control Registers (CONTROL). 272 */ 273 typedef union { 274 struct { 275 uint32_t _reserved0 :1; /*!< bit: 0 Reserved */ 276 uint32_t SPSEL :1; /*!< bit: 1 Stack to be used */ 277 uint32_t _reserved1 :30; /*!< bit: 2..31 Reserved */ 278 } b; /*!< Structure used for bit access */ 279 uint32_t w; /*!< Type used for word access */ 280 } CONTROL_Type; 281 282 /* CONTROL Register Definitions */ 283 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 284 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 285 286 /*@} end of group CMSIS_CORE */ 287 288 /** 289 \ingroup CMSIS_core_register 290 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 291 \brief Type definitions for the NVIC Registers 292 @{ 293 */ 294 295 /** 296 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 297 */ 298 typedef struct { 299 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 300 uint32_t RESERVED0[31U]; 301 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 302 uint32_t RSERVED1[31U]; 303 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 304 uint32_t RESERVED2[31U]; 305 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 306 uint32_t RESERVED3[31U]; 307 uint32_t RESERVED4[64U]; 308 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 309 } NVIC_Type; 310 311 /*@} end of group CMSIS_NVIC */ 312 313 /** 314 \ingroup CMSIS_core_register 315 \defgroup CMSIS_SCB System Control Block (SCB) 316 \brief Type definitions for the System Control Block Registers 317 @{ 318 */ 319 320 /** 321 \brief Structure type to access the System Control Block (SCB). 322 */ 323 typedef struct { 324 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 325 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 326 uint32_t RESERVED0; 327 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 328 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 329 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 330 uint32_t RESERVED1; 331 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 332 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 333 } SCB_Type; 334 335 /* SCB CPUID Register Definitions */ 336 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 337 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 338 339 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 340 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 341 342 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 343 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 344 345 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 346 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 347 348 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 349 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 350 351 /* SCB Interrupt Control State Register Definitions */ 352 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 353 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 354 355 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 356 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 357 358 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 359 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 360 361 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 362 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 363 364 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 365 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 366 367 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 368 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 369 370 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 371 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 372 373 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 374 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 375 376 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 377 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 378 379 /* SCB Application Interrupt and Reset Control Register Definitions */ 380 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 381 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 382 383 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 384 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 385 386 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 387 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 388 389 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 390 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 391 392 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 393 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 394 395 /* SCB System Control Register Definitions */ 396 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 397 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 398 399 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 400 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 401 402 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 403 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 404 405 /* SCB Configuration Control Register Definitions */ 406 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 407 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 408 409 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 410 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 411 412 /* SCB System Handler Control and State Register Definitions */ 413 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 414 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 415 416 /*@} end of group CMSIS_SCB */ 417 418 /** 419 \ingroup CMSIS_core_register 420 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 421 \brief Type definitions for the System Timer Registers. 422 @{ 423 */ 424 425 /** 426 \brief Structure type to access the System Timer (SysTick). 427 */ 428 typedef struct { 429 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 430 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 431 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 432 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 433 } SysTick_Type; 434 435 /* SysTick Control / Status Register Definitions */ 436 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 437 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 438 439 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 440 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 441 442 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 443 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 444 445 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 446 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 447 448 /* SysTick Reload Register Definitions */ 449 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 450 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 451 452 /* SysTick Current Register Definitions */ 453 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 454 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 455 456 /* SysTick Calibration Register Definitions */ 457 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 458 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 459 460 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 461 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 462 463 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 464 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 465 466 /*@} end of group CMSIS_SysTick */ 467 468 /** 469 \ingroup CMSIS_core_register 470 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 471 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 472 Therefore they are not covered by the Cortex-M0 header file. 473 @{ 474 */ 475 /*@} end of group CMSIS_CoreDebug */ 476 477 /** 478 \ingroup CMSIS_core_register 479 \defgroup CMSIS_core_bitfield Core register bit field macros 480 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 481 @{ 482 */ 483 484 /** 485 \brief Mask and shift a bit field value for use in a register bit range. 486 \param[in] field Name of the register bit field. 487 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 488 \return Masked and shifted value. 489 */ 490 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 491 492 /** 493 \brief Mask and shift a register value to extract a bit filed value. 494 \param[in] field Name of the register bit field. 495 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 496 \return Masked and shifted bit field value. 497 */ 498 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 499 500 /*@} end of group CMSIS_core_bitfield */ 501 502 /** 503 \ingroup CMSIS_core_register 504 \defgroup CMSIS_core_base Core Definitions 505 \brief Definitions for base addresses, unions, and structures. 506 @{ 507 */ 508 509 /* Memory mapping of Core Hardware */ 510 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 511 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 512 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 513 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 514 515 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 516 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 517 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 518 519 /*@} */ 520 521 /******************************************************************************* 522 * Hardware Abstraction Layer 523 Core Function Interface contains: 524 - Core NVIC Functions 525 - Core SysTick Functions 526 - Core Register Access Functions 527 ******************************************************************************/ 528 /** 529 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 530 */ 531 532 /* ########################## NVIC functions #################################### */ 533 /** 534 \ingroup CMSIS_Core_FunctionInterface 535 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 536 \brief Functions that manage interrupts and exceptions via the NVIC. 537 @{ 538 */ 539 540 #ifdef CMSIS_NVIC_VIRTUAL 541 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 542 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 543 #endif 544 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 545 #else 546 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 547 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 548 #define NVIC_EnableIRQ __NVIC_EnableIRQ 549 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 550 #define NVIC_DisableIRQ __NVIC_DisableIRQ 551 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 552 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 553 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 554 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ 555 #define NVIC_SetPriority __NVIC_SetPriority 556 #define NVIC_GetPriority __NVIC_GetPriority 557 #define NVIC_SystemReset __NVIC_SystemReset 558 #endif /* CMSIS_NVIC_VIRTUAL */ 559 560 #ifdef CMSIS_VECTAB_VIRTUAL 561 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 562 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 563 #endif 564 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 565 #else 566 #define NVIC_SetVector __NVIC_SetVector 567 #define NVIC_GetVector __NVIC_GetVector 568 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 569 570 #define NVIC_USER_IRQ_OFFSET 16 571 572 /* The following EXC_RETURN values are saved the LR on exception entry */ 573 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 574 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 575 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 576 577 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 578 /* The following MACROS handle generation of the register offset and byte masks */ 579 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 580 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 581 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 582 583 #define __NVIC_SetPriorityGrouping(X) (void)(X) 584 #define __NVIC_GetPriorityGrouping() (0U) 585 586 /** 587 \brief Enable Interrupt 588 \details Enables a device specific interrupt in the NVIC interrupt controller. 589 \param [in] IRQn Device specific interrupt number. 590 \note IRQn must not be negative. 591 */ 592 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 593 { 594 if ((int32_t) (IRQn) >= 0) { 595 NVIC->ISER[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 596 } 597 } 598 599 /** 600 \brief Get Interrupt Enable status 601 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 602 \param [in] IRQn Device specific interrupt number. 603 \return 0 Interrupt is not enabled. 604 \return 1 Interrupt is enabled. 605 \note IRQn must not be negative. 606 */ 607 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 608 { 609 if ((int32_t) (IRQn) >= 0) { 610 return ((uint32_t) ( 611 ((NVIC->ISER[0U] & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 612 1UL : 0UL)); 613 } else { 614 return (0U); 615 } 616 } 617 618 /** 619 \brief Disable Interrupt 620 \details Disables a device specific interrupt in the NVIC interrupt controller. 621 \param [in] IRQn Device specific interrupt number. 622 \note IRQn must not be negative. 623 */ 624 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 625 { 626 if ((int32_t) (IRQn) >= 0) { 627 NVIC->ICER[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 628 __DSB(); 629 __ISB(); 630 } 631 } 632 633 /** 634 \brief Get Pending Interrupt 635 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 636 \param [in] IRQn Device specific interrupt number. 637 \return 0 Interrupt status is not pending. 638 \return 1 Interrupt status is pending. 639 \note IRQn must not be negative. 640 */ 641 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 642 { 643 if ((int32_t) (IRQn) >= 0) { 644 return ((uint32_t) ( 645 ((NVIC->ISPR[0U] & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 646 1UL : 0UL)); 647 } else { 648 return (0U); 649 } 650 } 651 652 /** 653 \brief Set Pending Interrupt 654 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 655 \param [in] IRQn Device specific interrupt number. 656 \note IRQn must not be negative. 657 */ 658 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 659 { 660 if ((int32_t) (IRQn) >= 0) { 661 NVIC->ISPR[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 662 } 663 } 664 665 /** 666 \brief Clear Pending Interrupt 667 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 668 \param [in] IRQn Device specific interrupt number. 669 \note IRQn must not be negative. 670 */ 671 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 672 { 673 if ((int32_t) (IRQn) >= 0) { 674 NVIC->ICPR[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 675 } 676 } 677 678 /** 679 \brief Set Interrupt Priority 680 \details Sets the priority of a device specific interrupt or a processor exception. 681 The interrupt number can be positive to specify a device specific interrupt, 682 or negative to specify a processor exception. 683 \param [in] IRQn Interrupt number. 684 \param [in] priority Priority to set. 685 \note The priority cannot be set for every processor exception. 686 */ 687 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 688 { 689 if ((int32_t) (IRQn) >= 0) { 690 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t) (NVIC->IP[_IP_IDX(IRQn)] 691 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 692 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 693 << _BIT_SHIFT(IRQn))); 694 } else { 695 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t) (SCB->SHP[_SHP_IDX(IRQn)] 696 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 697 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 698 << _BIT_SHIFT(IRQn))); 699 } 700 } 701 702 /** 703 \brief Get Interrupt Priority 704 \details Reads the priority of a device specific interrupt or a processor exception. 705 The interrupt number can be positive to specify a device specific interrupt, 706 or negative to specify a processor exception. 707 \param [in] IRQn Interrupt number. 708 \return Interrupt Priority. 709 Value is aligned automatically to the implemented priority bits of the microcontroller. 710 */ 711 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 712 { 713 714 if ((int32_t) (IRQn) >= 0) { 715 return ((uint32_t) (((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 716 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 717 } else { 718 return ((uint32_t) (((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 719 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 720 } 721 } 722 723 /** 724 \brief Encode Priority 725 \details Encodes the priority for an interrupt with the given priority group, 726 preemptive priority value, and subpriority value. 727 In case of a conflict between priority grouping and available 728 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 729 \param [in] PriorityGroup Used priority group. 730 \param [in] PreemptPriority Preemptive priority value (starting from 0). 731 \param [in] SubPriority Subpriority value (starting from 0). 732 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 733 */ 734 __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, 735 uint32_t PreemptPriority, uint32_t SubPriority) 736 { 737 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 738 uint32_t PreemptPriorityBits; 739 uint32_t SubPriorityBits; 740 741 PreemptPriorityBits = 742 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 743 (uint32_t) (__NVIC_PRIO_BITS) : 744 (uint32_t) (7UL - PriorityGroupTmp); 745 SubPriorityBits = 746 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) < (uint32_t) 7UL) ? 747 (uint32_t) 0UL : 748 (uint32_t) ((PriorityGroupTmp - 7UL) 749 + (uint32_t) (__NVIC_PRIO_BITS)); 750 751 return (((PreemptPriority 752 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL)) 753 << SubPriorityBits) 754 | ((SubPriority & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL)))); 755 } 756 757 /** 758 \brief Decode Priority 759 \details Decodes an interrupt priority value with a given priority group to 760 preemptive priority value and subpriority value. 761 In case of a conflict between priority grouping and available 762 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 763 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 764 \param [in] PriorityGroup Used priority group. 765 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 766 \param [out] pSubPriority Subpriority value (starting from 0). 767 */ 768 __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, 769 uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 770 uint32_t *const pSubPriority) 771 { 772 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 773 uint32_t PreemptPriorityBits; 774 uint32_t SubPriorityBits; 775 776 PreemptPriorityBits = 777 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 778 (uint32_t) (__NVIC_PRIO_BITS) : 779 (uint32_t) (7UL - PriorityGroupTmp); 780 SubPriorityBits = 781 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) < (uint32_t) 7UL) ? 782 (uint32_t) 0UL : 783 (uint32_t) ((PriorityGroupTmp - 7UL) 784 + (uint32_t) (__NVIC_PRIO_BITS)); 785 786 *pPreemptPriority = (Priority >> SubPriorityBits) 787 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL); 788 *pSubPriority = (Priority) & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL); 789 } 790 791 /** 792 \brief Set Interrupt Vector 793 \details Sets an interrupt vector in SRAM based interrupt vector table. 794 The interrupt number can be positive to specify a device specific interrupt, 795 or negative to specify a processor exception. 796 Address 0 must be mapped to SRAM. 797 \param [in] IRQn Interrupt number 798 \param [in] vector Address of interrupt handler function 799 */ 800 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 801 { 802 uint32_t *vectors = (uint32_t*) 0x0U; 803 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 804 } 805 806 /** 807 \brief Get Interrupt Vector 808 \details Reads an interrupt vector from interrupt vector table. 809 The interrupt number can be positive to specify a device specific interrupt, 810 or negative to specify a processor exception. 811 \param [in] IRQn Interrupt number. 812 \return Address of interrupt handler function 813 */ 814 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 815 { 816 uint32_t *vectors = (uint32_t*) 0x0U; 817 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 818 } 819 820 /** 821 \brief System Reset 822 \details Initiates a system reset request to reset the MCU. 823 */ 824 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 825 { 826 __DSB(); /* Ensure all outstanding memory accesses included 827 buffered write are completed before reset */ 828 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 829 SCB_AIRCR_SYSRESETREQ_Msk); 830 __DSB(); /* Ensure completion of memory access */ 831 832 for (;;) /* wait until reset */ 833 { 834 __NOP(); 835 } 836 } 837 838 /*@} end of CMSIS_Core_NVICFunctions */ 839 840 /* ########################## FPU functions #################################### */ 841 /** 842 \ingroup CMSIS_Core_FunctionInterface 843 \defgroup CMSIS_Core_FpuFunctions FPU Functions 844 \brief Function that provides FPU type. 845 @{ 846 */ 847 848 /** 849 \brief get FPU type 850 \details returns the FPU type 851 \returns 852 - \b 0: No FPU 853 - \b 1: Single precision FPU 854 - \b 2: Double + Single precision FPU 855 */ 856 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 857 { 858 return 0U; /* No FPU */ 859 } 860 861 /*@} end of CMSIS_Core_FpuFunctions */ 862 863 /* ################################## SysTick function ############################################ */ 864 /** 865 \ingroup CMSIS_Core_FunctionInterface 866 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 867 \brief Functions that configure the System. 868 @{ 869 */ 870 871 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 872 873 /** 874 \brief System Tick Configuration 875 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 876 Counter is in free running mode to generate periodic interrupts. 877 \param [in] ticks Number of ticks between two interrupts. 878 \return 0 Function succeeded. 879 \return 1 Function failed. 880 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 881 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 882 must contain a vendor-specific implementation of this function. 883 */ 884 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 885 { 886 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 887 { 888 return (1UL); /* Reload value impossible */ 889 } 890 891 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 892 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 893 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 894 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 895 SysTick_CTRL_TICKINT_Msk | 896 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 897 return (0UL); /* Function successful */ 898 } 899 900 #endif 901 902 /*@} end of CMSIS_Core_SysTickFunctions */ 903 904 #ifdef __cplusplus 905 } 906 #endif 907 908 #endif /* __CORE_CM0_H_DEPENDANT */ 909 910 #endif /* __CMSIS_GENERIC */