Drivers/CMSIS/Include/core_armv8mml.h (168893B)
1 /**************************************************************************//** 2 * @file core_armv8mml.h 3 * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File 4 * @version V5.0.7 5 * @date 06. July 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_ARMV8MML_H_GENERIC 32 #define __CORE_ARMV8MML_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup Cortex_ARMv8MML 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS Armv8MML definitions */ 65 #define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ 68 __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_M (81U) /*!< Cortex-M Core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 74 */ 75 #if defined ( __CC_ARM ) 76 #if defined __TARGET_FPU_VFP 77 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 78 #define __FPU_USED 1U 79 #else 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 81 #define __FPU_USED 0U 82 #endif 83 #else 84 #define __FPU_USED 0U 85 #endif 86 87 #if defined(__ARM_FEATURE_DSP) 88 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 89 #define __DSP_USED 1U 90 #else 91 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 92 #define __DSP_USED 0U 93 #endif 94 #else 95 #define __DSP_USED 0U 96 #endif 97 98 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 99 #if defined __ARM_PCS_VFP 100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 101 #define __FPU_USED 1U 102 #else 103 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 104 #define __FPU_USED 0U 105 #endif 106 #else 107 #define __FPU_USED 0U 108 #endif 109 110 #if defined(__ARM_FEATURE_DSP) 111 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 112 #define __DSP_USED 1U 113 #else 114 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 115 #define __DSP_USED 0U 116 #endif 117 #else 118 #define __DSP_USED 0U 119 #endif 120 121 #elif defined ( __GNUC__ ) 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 123 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 124 #define __FPU_USED 1U 125 #else 126 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 127 #define __FPU_USED 0U 128 #endif 129 #else 130 #define __FPU_USED 0U 131 #endif 132 133 #if defined(__ARM_FEATURE_DSP) 134 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 135 #define __DSP_USED 1U 136 #else 137 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 138 #define __DSP_USED 0U 139 #endif 140 #else 141 #define __DSP_USED 0U 142 #endif 143 144 #elif defined ( __ICCARM__ ) 145 #if defined __ARMVFP__ 146 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 147 #define __FPU_USED 1U 148 #else 149 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 150 #define __FPU_USED 0U 151 #endif 152 #else 153 #define __FPU_USED 0U 154 #endif 155 156 #if defined(__ARM_FEATURE_DSP) 157 #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) 158 #define __DSP_USED 1U 159 #else 160 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" 161 #define __DSP_USED 0U 162 #endif 163 #else 164 #define __DSP_USED 0U 165 #endif 166 167 #elif defined ( __TI_ARM__ ) 168 #if defined __TI_VFP_SUPPORT__ 169 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 170 #define __FPU_USED 1U 171 #else 172 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 173 #define __FPU_USED 0U 174 #endif 175 #else 176 #define __FPU_USED 0U 177 #endif 178 179 #elif defined ( __TASKING__ ) 180 #if defined __FPU_VFP__ 181 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 182 #define __FPU_USED 1U 183 #else 184 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 185 #define __FPU_USED 0U 186 #endif 187 #else 188 #define __FPU_USED 0U 189 #endif 190 191 #elif defined ( __CSMC__ ) 192 #if ( __CSMC__ & 0x400U) 193 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 194 #define __FPU_USED 1U 195 #else 196 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 197 #define __FPU_USED 0U 198 #endif 199 #else 200 #define __FPU_USED 0U 201 #endif 202 203 #endif 204 205 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 206 207 #ifdef __cplusplus 208 } 209 #endif 210 211 #endif /* __CORE_ARMV8MML_H_GENERIC */ 212 213 #ifndef __CMSIS_GENERIC 214 215 #ifndef __CORE_ARMV8MML_H_DEPENDANT 216 #define __CORE_ARMV8MML_H_DEPENDANT 217 218 #ifdef __cplusplus 219 extern "C" { 220 #endif 221 222 /* check device defines and use defaults */ 223 #if defined __CHECK_DEVICE_DEFINES 224 #ifndef __ARMv8MML_REV 225 #define __ARMv8MML_REV 0x0000U 226 #warning "__ARMv8MML_REV not defined in device header file; using default!" 227 #endif 228 229 #ifndef __FPU_PRESENT 230 #define __FPU_PRESENT 0U 231 #warning "__FPU_PRESENT not defined in device header file; using default!" 232 #endif 233 234 #ifndef __MPU_PRESENT 235 #define __MPU_PRESENT 0U 236 #warning "__MPU_PRESENT not defined in device header file; using default!" 237 #endif 238 239 #ifndef __SAUREGION_PRESENT 240 #define __SAUREGION_PRESENT 0U 241 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 242 #endif 243 244 #ifndef __DSP_PRESENT 245 #define __DSP_PRESENT 0U 246 #warning "__DSP_PRESENT not defined in device header file; using default!" 247 #endif 248 249 #ifndef __NVIC_PRIO_BITS 250 #define __NVIC_PRIO_BITS 3U 251 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 252 #endif 253 254 #ifndef __Vendor_SysTickConfig 255 #define __Vendor_SysTickConfig 0U 256 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 257 #endif 258 #endif 259 260 /* IO definitions (access restrictions to peripheral registers) */ 261 /** 262 \defgroup CMSIS_glob_defs CMSIS Global Defines 263 264 <strong>IO Type Qualifiers</strong> are used 265 \li to specify the access to peripheral variables. 266 \li for automatic generation of peripheral register debug information. 267 */ 268 #ifdef __cplusplus 269 #define __I volatile /*!< Defines 'read only' permissions */ 270 #else 271 #define __I volatile const /*!< Defines 'read only' permissions */ 272 #endif 273 #define __O volatile /*!< Defines 'write only' permissions */ 274 #define __IO volatile /*!< Defines 'read / write' permissions */ 275 276 /* following defines should be used for structure members */ 277 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 278 #define __OM volatile /*! Defines 'write only' structure member permissions */ 279 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 280 281 /*@} end of group ARMv8MML */ 282 283 /******************************************************************************* 284 * Register Abstraction 285 Core Register contain: 286 - Core Register 287 - Core NVIC Register 288 - Core SCB Register 289 - Core SysTick Register 290 - Core Debug Register 291 - Core MPU Register 292 - Core SAU Register 293 - Core FPU Register 294 ******************************************************************************/ 295 /** 296 \defgroup CMSIS_core_register Defines and Type Definitions 297 \brief Type definitions and defines for Cortex-M processor based devices. 298 */ 299 300 /** 301 \ingroup CMSIS_core_register 302 \defgroup CMSIS_CORE Status and Control Registers 303 \brief Core Register type definitions. 304 @{ 305 */ 306 307 /** 308 \brief Union type to access the Application Program Status Register (APSR). 309 */ 310 typedef union { 311 struct { 312 uint32_t _reserved0 :16; /*!< bit: 0..15 Reserved */ 313 uint32_t GE :4; /*!< bit: 16..19 Greater than or Equal flags */ 314 uint32_t _reserved1 :7; /*!< bit: 20..26 Reserved */ 315 uint32_t Q :1; /*!< bit: 27 Saturation condition flag */ 316 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 317 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 318 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 319 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 320 } b; /*!< Structure used for bit access */ 321 uint32_t w; /*!< Type used for word access */ 322 } APSR_Type; 323 324 /* APSR Register Definitions */ 325 #define APSR_N_Pos 31U /*!< APSR: N Position */ 326 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 327 328 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 329 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 330 331 #define APSR_C_Pos 29U /*!< APSR: C Position */ 332 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 333 334 #define APSR_V_Pos 28U /*!< APSR: V Position */ 335 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 336 337 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 338 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 339 340 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 341 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 342 343 /** 344 \brief Union type to access the Interrupt Program Status Register (IPSR). 345 */ 346 typedef union { 347 struct { 348 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 349 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 350 } b; /*!< Structure used for bit access */ 351 uint32_t w; /*!< Type used for word access */ 352 } IPSR_Type; 353 354 /* IPSR Register Definitions */ 355 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 356 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 357 358 /** 359 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 360 */ 361 typedef union { 362 struct { 363 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 364 uint32_t _reserved0 :7; /*!< bit: 9..15 Reserved */ 365 uint32_t GE :4; /*!< bit: 16..19 Greater than or Equal flags */ 366 uint32_t _reserved1 :4; /*!< bit: 20..23 Reserved */ 367 uint32_t T :1; /*!< bit: 24 Thumb bit (read 0) */ 368 uint32_t IT :2; /*!< bit: 25..26 saved IT state (read 0) */ 369 uint32_t Q :1; /*!< bit: 27 Saturation condition flag */ 370 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 371 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 372 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 373 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 374 } b; /*!< Structure used for bit access */ 375 uint32_t w; /*!< Type used for word access */ 376 } xPSR_Type; 377 378 /* xPSR Register Definitions */ 379 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 380 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 381 382 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 383 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 384 385 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 386 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 387 388 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 389 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 390 391 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 392 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 393 394 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ 395 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ 396 397 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 398 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 399 400 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 401 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 402 403 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 404 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 405 406 /** 407 \brief Union type to access the Control Registers (CONTROL). 408 */ 409 typedef union { 410 struct { 411 uint32_t nPRIV :1; /*!< bit: 0 Execution privilege in Thread mode */ 412 uint32_t SPSEL :1; /*!< bit: 1 Stack-pointer select */ 413 uint32_t FPCA :1; /*!< bit: 2 Floating-point context active */ 414 uint32_t SFPA :1; /*!< bit: 3 Secure floating-point active */ 415 uint32_t _reserved1 :28; /*!< bit: 4..31 Reserved */ 416 } b; /*!< Structure used for bit access */ 417 uint32_t w; /*!< Type used for word access */ 418 } CONTROL_Type; 419 420 /* CONTROL Register Definitions */ 421 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ 422 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ 423 424 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 425 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 426 427 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 428 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 429 430 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 431 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 432 433 /*@} end of group CMSIS_CORE */ 434 435 /** 436 \ingroup CMSIS_core_register 437 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 438 \brief Type definitions for the NVIC Registers 439 @{ 440 */ 441 442 /** 443 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 444 */ 445 typedef struct { 446 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 447 uint32_t RESERVED0[16U]; 448 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 449 uint32_t RSERVED1[16U]; 450 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 451 uint32_t RESERVED2[16U]; 452 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 453 uint32_t RESERVED3[16U]; 454 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 455 uint32_t RESERVED4[16U]; 456 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 457 uint32_t RESERVED5[16U]; 458 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 459 uint32_t RESERVED6[580U]; 460 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 461 } NVIC_Type; 462 463 /* Software Triggered Interrupt Register Definitions */ 464 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 465 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 466 467 /*@} end of group CMSIS_NVIC */ 468 469 /** 470 \ingroup CMSIS_core_register 471 \defgroup CMSIS_SCB System Control Block (SCB) 472 \brief Type definitions for the System Control Block Registers 473 @{ 474 */ 475 476 /** 477 \brief Structure type to access the System Control Block (SCB). 478 */ 479 typedef struct { 480 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 481 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 482 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 483 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 484 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 485 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 486 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 487 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 488 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 489 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 490 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 491 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 492 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 493 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 494 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 495 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 496 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 497 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 498 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 499 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 500 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 501 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 502 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 503 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 504 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ 505 uint32_t RESERVED3[92U]; 506 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 507 uint32_t RESERVED4[15U]; 508 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 509 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 510 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ 511 uint32_t RESERVED5[1U]; 512 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 513 uint32_t RESERVED6[1U]; 514 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 515 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 516 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 517 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 518 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 519 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 520 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 521 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 522 uint32_t RESERVED7[6U]; 523 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ 524 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ 525 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 526 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 527 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 528 uint32_t RESERVED8[1U]; 529 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ 530 } SCB_Type; 531 532 /* SCB CPUID Register Definitions */ 533 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 534 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 535 536 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 537 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 538 539 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 540 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 541 542 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 543 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 544 545 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 546 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 547 548 /* SCB Interrupt Control State Register Definitions */ 549 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 550 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 551 552 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 553 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 554 555 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 556 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 557 558 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 559 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 560 561 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 562 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 563 564 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 565 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 566 567 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 568 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 569 570 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 571 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 572 573 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 574 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 575 576 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 577 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 578 579 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 580 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 581 582 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 583 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 584 585 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 586 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 587 588 /* SCB Vector Table Offset Register Definitions */ 589 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 590 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 591 592 /* SCB Application Interrupt and Reset Control Register Definitions */ 593 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 594 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 595 596 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 597 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 598 599 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 600 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 601 602 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 603 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 604 605 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 606 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 607 608 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 609 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 610 611 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 612 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 613 614 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 615 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 616 617 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 618 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 619 620 /* SCB System Control Register Definitions */ 621 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 622 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 623 624 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 625 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 626 627 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 628 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 629 630 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 631 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 632 633 /* SCB Configuration Control Register Definitions */ 634 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 635 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 636 637 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 638 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 639 640 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 641 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 642 643 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 644 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 645 646 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 647 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 648 649 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 650 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 651 652 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 653 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 654 655 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 656 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 657 658 /* SCB System Handler Control and State Register Definitions */ 659 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 660 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 661 662 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ 663 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ 664 665 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ 666 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ 667 668 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 669 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 670 671 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 672 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 673 674 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 675 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 676 677 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 678 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 679 680 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 681 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 682 683 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 684 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 685 686 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 687 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 688 689 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 690 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 691 692 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 693 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 694 695 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 696 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 697 698 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 699 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 700 701 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 702 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 703 704 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ 705 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ 706 707 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 708 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 709 710 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 711 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 712 713 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 714 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 715 716 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 717 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 718 719 /* SCB Configurable Fault Status Register Definitions */ 720 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 721 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 722 723 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 724 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 725 726 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 727 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 728 729 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 730 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 731 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 732 733 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 734 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 735 736 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 737 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 738 739 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 740 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 741 742 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 743 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 744 745 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 746 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 747 748 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 749 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 750 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 751 752 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 753 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 754 755 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 756 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 757 758 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 759 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 760 761 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 762 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 763 764 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 765 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 766 767 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 768 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 769 770 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 771 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 772 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 773 774 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 775 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 776 777 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ 778 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ 779 780 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 781 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 782 783 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 784 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 785 786 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 787 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 788 789 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 790 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 791 792 /* SCB Hard Fault Status Register Definitions */ 793 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 794 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 795 796 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 797 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 798 799 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 800 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 801 802 /* SCB Debug Fault Status Register Definitions */ 803 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 804 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 805 806 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 807 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 808 809 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 810 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 811 812 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 813 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 814 815 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 816 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 817 818 /* SCB Non-Secure Access Control Register Definitions */ 819 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ 820 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ 821 822 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ 823 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ 824 825 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ 826 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ 827 828 /* SCB Cache Level ID Register Definitions */ 829 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ 830 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 831 832 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ 833 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ 834 835 /* SCB Cache Type Register Definitions */ 836 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ 837 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 838 839 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ 840 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 841 842 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ 843 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 844 845 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ 846 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 847 848 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ 849 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 850 851 /* SCB Cache Size ID Register Definitions */ 852 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 853 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 854 855 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 856 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 857 858 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 859 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 860 861 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 862 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 863 864 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ 865 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 866 867 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ 868 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 869 870 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ 871 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 872 873 /* SCB Cache Size Selection Register Definitions */ 874 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ 875 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 876 877 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ 878 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 879 880 /* SCB Software Triggered Interrupt Register Definitions */ 881 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ 882 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 883 884 /* SCB D-Cache Invalidate by Set-way Register Definitions */ 885 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ 886 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ 887 888 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ 889 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ 890 891 /* SCB D-Cache Clean by Set-way Register Definitions */ 892 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ 893 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ 894 895 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ 896 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ 897 898 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 899 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ 900 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ 901 902 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ 903 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ 904 905 /* Instruction Tightly-Coupled Memory Control Register Definitions */ 906 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ 907 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ 908 909 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ 910 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ 911 912 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ 913 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ 914 915 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ 916 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ 917 918 /* Data Tightly-Coupled Memory Control Register Definitions */ 919 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ 920 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ 921 922 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ 923 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ 924 925 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ 926 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ 927 928 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ 929 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ 930 931 /* AHBP Control Register Definitions */ 932 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ 933 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ 934 935 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ 936 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ 937 938 /* L1 Cache Control Register Definitions */ 939 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ 940 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ 941 942 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ 943 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ 944 945 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ 946 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ 947 948 /* AHBS Control Register Definitions */ 949 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ 950 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ 951 952 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ 953 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ 954 955 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ 956 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ 957 958 /* Auxiliary Bus Fault Status Register Definitions */ 959 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ 960 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ 961 962 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ 963 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ 964 965 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ 966 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ 967 968 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ 969 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ 970 971 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ 972 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ 973 974 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ 975 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ 976 977 /*@} end of group CMSIS_SCB */ 978 979 /** 980 \ingroup CMSIS_core_register 981 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 982 \brief Type definitions for the System Control and ID Register not in the SCB 983 @{ 984 */ 985 986 /** 987 \brief Structure type to access the System Control and ID Register not in the SCB. 988 */ 989 typedef struct { 990 uint32_t RESERVED0[1U]; 991 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 992 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 993 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ 994 } SCnSCB_Type; 995 996 /* Interrupt Controller Type Register Definitions */ 997 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 998 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 999 1000 /*@} end of group CMSIS_SCnotSCB */ 1001 1002 /** 1003 \ingroup CMSIS_core_register 1004 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 1005 \brief Type definitions for the System Timer Registers. 1006 @{ 1007 */ 1008 1009 /** 1010 \brief Structure type to access the System Timer (SysTick). 1011 */ 1012 typedef struct { 1013 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 1014 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 1015 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 1016 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 1017 } SysTick_Type; 1018 1019 /* SysTick Control / Status Register Definitions */ 1020 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 1021 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 1022 1023 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 1024 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 1025 1026 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 1027 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 1028 1029 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 1030 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 1031 1032 /* SysTick Reload Register Definitions */ 1033 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 1034 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 1035 1036 /* SysTick Current Register Definitions */ 1037 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 1038 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 1039 1040 /* SysTick Calibration Register Definitions */ 1041 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 1042 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 1043 1044 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 1045 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 1046 1047 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 1048 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 1049 1050 /*@} end of group CMSIS_SysTick */ 1051 1052 /** 1053 \ingroup CMSIS_core_register 1054 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 1055 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 1056 @{ 1057 */ 1058 1059 /** 1060 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 1061 */ 1062 typedef struct { 1063 __OM union 1064 { 1065 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 1066 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 1067 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 1068 } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 1069 uint32_t RESERVED0[864U]; 1070 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 1071 uint32_t RESERVED1[15U]; 1072 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 1073 uint32_t RESERVED2[15U]; 1074 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 1075 uint32_t RESERVED3[29U]; 1076 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 1077 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 1078 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 1079 uint32_t RESERVED4[43U]; 1080 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 1081 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 1082 uint32_t RESERVED5[1U]; 1083 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ 1084 uint32_t RESERVED6[4U]; 1085 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 1086 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 1087 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 1088 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 1089 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 1090 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 1091 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 1092 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 1093 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 1094 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 1095 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 1096 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 1097 } ITM_Type; 1098 1099 /* ITM Stimulus Port Register Definitions */ 1100 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ 1101 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ 1102 1103 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ 1104 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ 1105 1106 /* ITM Trace Privilege Register Definitions */ 1107 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1108 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 1109 1110 /* ITM Trace Control Register Definitions */ 1111 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 1112 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 1113 1114 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ 1115 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ 1116 1117 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 1118 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 1119 1120 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ 1121 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ 1122 1123 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ 1124 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ 1125 1126 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 1127 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 1128 1129 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 1130 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 1131 1132 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 1133 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 1134 1135 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 1136 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 1137 1138 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 1139 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 1140 1141 /* ITM Integration Write Register Definitions */ 1142 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 1143 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 1144 1145 /* ITM Integration Read Register Definitions */ 1146 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 1147 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 1148 1149 /* ITM Integration Mode Control Register Definitions */ 1150 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 1151 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 1152 1153 /* ITM Lock Status Register Definitions */ 1154 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 1155 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 1156 1157 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 1158 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 1159 1160 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 1161 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 1162 1163 /*@}*//* end of group CMSIS_ITM */ 1164 1165 /** 1166 \ingroup CMSIS_core_register 1167 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 1168 \brief Type definitions for the Data Watchpoint and Trace (DWT) 1169 @{ 1170 */ 1171 1172 /** 1173 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 1174 */ 1175 typedef struct { 1176 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 1177 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 1178 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 1179 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 1180 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 1181 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 1182 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 1183 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 1184 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 1185 uint32_t RESERVED1[1U]; 1186 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 1187 uint32_t RESERVED2[1U]; 1188 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 1189 uint32_t RESERVED3[1U]; 1190 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 1191 uint32_t RESERVED4[1U]; 1192 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 1193 uint32_t RESERVED5[1U]; 1194 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 1195 uint32_t RESERVED6[1U]; 1196 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 1197 uint32_t RESERVED7[1U]; 1198 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 1199 uint32_t RESERVED8[1U]; 1200 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 1201 uint32_t RESERVED9[1U]; 1202 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 1203 uint32_t RESERVED10[1U]; 1204 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 1205 uint32_t RESERVED11[1U]; 1206 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 1207 uint32_t RESERVED12[1U]; 1208 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 1209 uint32_t RESERVED13[1U]; 1210 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 1211 uint32_t RESERVED14[1U]; 1212 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 1213 uint32_t RESERVED15[1U]; 1214 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 1215 uint32_t RESERVED16[1U]; 1216 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 1217 uint32_t RESERVED17[1U]; 1218 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 1219 uint32_t RESERVED18[1U]; 1220 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 1221 uint32_t RESERVED19[1U]; 1222 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 1223 uint32_t RESERVED20[1U]; 1224 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 1225 uint32_t RESERVED21[1U]; 1226 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 1227 uint32_t RESERVED22[1U]; 1228 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 1229 uint32_t RESERVED23[1U]; 1230 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 1231 uint32_t RESERVED24[1U]; 1232 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 1233 uint32_t RESERVED25[1U]; 1234 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 1235 uint32_t RESERVED26[1U]; 1236 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 1237 uint32_t RESERVED27[1U]; 1238 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 1239 uint32_t RESERVED28[1U]; 1240 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 1241 uint32_t RESERVED29[1U]; 1242 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 1243 uint32_t RESERVED30[1U]; 1244 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 1245 uint32_t RESERVED31[1U]; 1246 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 1247 uint32_t RESERVED32[934U]; 1248 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 1249 uint32_t RESERVED33[1U]; 1250 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ 1251 } DWT_Type; 1252 1253 /* DWT Control Register Definitions */ 1254 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 1255 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 1256 1257 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 1258 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 1259 1260 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 1261 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 1262 1263 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 1264 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 1265 1266 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 1267 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 1268 1269 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ 1270 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ 1271 1272 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 1273 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 1274 1275 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 1276 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 1277 1278 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 1279 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 1280 1281 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 1282 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 1283 1284 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 1285 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 1286 1287 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 1288 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 1289 1290 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 1291 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 1292 1293 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 1294 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 1295 1296 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 1297 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 1298 1299 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 1300 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 1301 1302 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 1303 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 1304 1305 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 1306 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 1307 1308 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 1309 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 1310 1311 /* DWT CPI Count Register Definitions */ 1312 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 1313 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 1314 1315 /* DWT Exception Overhead Count Register Definitions */ 1316 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 1317 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 1318 1319 /* DWT Sleep Count Register Definitions */ 1320 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 1321 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 1322 1323 /* DWT LSU Count Register Definitions */ 1324 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 1325 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 1326 1327 /* DWT Folded-instruction Count Register Definitions */ 1328 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 1329 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 1330 1331 /* DWT Comparator Function Register Definitions */ 1332 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 1333 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 1334 1335 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 1336 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 1337 1338 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 1339 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 1340 1341 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 1342 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 1343 1344 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 1345 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 1346 1347 /*@}*//* end of group CMSIS_DWT */ 1348 1349 /** 1350 \ingroup CMSIS_core_register 1351 \defgroup CMSIS_TPI Trace Port Interface (TPI) 1352 \brief Type definitions for the Trace Port Interface (TPI) 1353 @{ 1354 */ 1355 1356 /** 1357 \brief Structure type to access the Trace Port Interface Register (TPI). 1358 */ 1359 typedef struct { 1360 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ 1361 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ 1362 uint32_t RESERVED0[2U]; 1363 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 1364 uint32_t RESERVED1[55U]; 1365 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 1366 uint32_t RESERVED2[131U]; 1367 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 1368 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 1369 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 1370 uint32_t RESERVED3[809U]; 1371 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ 1372 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ 1373 uint32_t RESERVED4[4U]; 1374 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ 1375 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ 1376 } TPI_Type; 1377 1378 /* TPI Asynchronous Clock Prescaler Register Definitions */ 1379 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ 1380 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ 1381 1382 /* TPI Selected Pin Protocol Register Definitions */ 1383 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 1384 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 1385 1386 /* TPI Formatter and Flush Status Register Definitions */ 1387 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 1388 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 1389 1390 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 1391 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 1392 1393 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 1394 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 1395 1396 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 1397 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 1398 1399 /* TPI Formatter and Flush Control Register Definitions */ 1400 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 1401 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 1402 1403 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 1404 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 1405 1406 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 1407 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 1408 1409 /* TPI Periodic Synchronization Control Register Definitions */ 1410 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ 1411 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ 1412 1413 /* TPI Software Lock Status Register Definitions */ 1414 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ 1415 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ 1416 1417 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ 1418 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ 1419 1420 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ 1421 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ 1422 1423 /* TPI DEVID Register Definitions */ 1424 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 1425 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1426 1427 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 1428 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1429 1430 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 1431 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1432 1433 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ 1434 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ 1435 1436 /* TPI DEVTYPE Register Definitions */ 1437 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 1438 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 1439 1440 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 1441 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1442 1443 /*@}*//* end of group CMSIS_TPI */ 1444 1445 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1446 /** 1447 \ingroup CMSIS_core_register 1448 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1449 \brief Type definitions for the Memory Protection Unit (MPU) 1450 @{ 1451 */ 1452 1453 /** 1454 \brief Structure type to access the Memory Protection Unit (MPU). 1455 */ 1456 typedef struct 1457 { 1458 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1459 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1460 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 1461 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 1462 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 1463 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ 1464 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ 1465 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ 1466 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ 1467 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ 1468 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ 1469 uint32_t RESERVED0[1]; 1470 union { 1471 __IOM uint32_t MAIR[2]; 1472 struct { 1473 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 1474 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 1475 }; 1476 }; 1477 } MPU_Type; 1478 1479 #define MPU_TYPE_RALIASES 4U 1480 1481 /* MPU Type Register Definitions */ 1482 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 1483 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 1484 1485 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 1486 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 1487 1488 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 1489 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 1490 1491 /* MPU Control Register Definitions */ 1492 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 1493 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 1494 1495 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 1496 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 1497 1498 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 1499 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 1500 1501 /* MPU Region Number Register Definitions */ 1502 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 1503 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 1504 1505 /* MPU Region Base Address Register Definitions */ 1506 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 1507 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 1508 1509 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 1510 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 1511 1512 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 1513 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 1514 1515 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 1516 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 1517 1518 /* MPU Region Limit Address Register Definitions */ 1519 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 1520 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 1521 1522 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 1523 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 1524 1525 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ 1526 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ 1527 1528 /* MPU Memory Attribute Indirection Register 0 Definitions */ 1529 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 1530 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 1531 1532 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 1533 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 1534 1535 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 1536 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 1537 1538 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 1539 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 1540 1541 /* MPU Memory Attribute Indirection Register 1 Definitions */ 1542 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 1543 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 1544 1545 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 1546 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 1547 1548 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 1549 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 1550 1551 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 1552 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 1553 1554 /*@} end of group CMSIS_MPU */ 1555 #endif 1556 1557 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1558 /** 1559 \ingroup CMSIS_core_register 1560 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 1561 \brief Type definitions for the Security Attribution Unit (SAU) 1562 @{ 1563 */ 1564 1565 /** 1566 \brief Structure type to access the Security Attribution Unit (SAU). 1567 */ 1568 typedef struct 1569 { 1570 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 1571 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 1572 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 1573 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 1574 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 1575 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 1576 #else 1577 uint32_t RESERVED0[3]; 1578 #endif 1579 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ 1580 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ 1581 } SAU_Type; 1582 1583 /* SAU Control Register Definitions */ 1584 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 1585 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 1586 1587 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 1588 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 1589 1590 /* SAU Type Register Definitions */ 1591 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 1592 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 1593 1594 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 1595 /* SAU Region Number Register Definitions */ 1596 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 1597 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 1598 1599 /* SAU Region Base Address Register Definitions */ 1600 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 1601 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 1602 1603 /* SAU Region Limit Address Register Definitions */ 1604 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 1605 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 1606 1607 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 1608 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 1609 1610 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 1611 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 1612 1613 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 1614 1615 /* Secure Fault Status Register Definitions */ 1616 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ 1617 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ 1618 1619 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ 1620 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ 1621 1622 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ 1623 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ 1624 1625 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ 1626 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ 1627 1628 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ 1629 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ 1630 1631 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ 1632 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ 1633 1634 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ 1635 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ 1636 1637 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ 1638 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ 1639 1640 /*@} end of group CMSIS_SAU */ 1641 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1642 1643 /** 1644 \ingroup CMSIS_core_register 1645 \defgroup CMSIS_FPU Floating Point Unit (FPU) 1646 \brief Type definitions for the Floating Point Unit (FPU) 1647 @{ 1648 */ 1649 1650 /** 1651 \brief Structure type to access the Floating Point Unit (FPU). 1652 */ 1653 typedef struct { 1654 uint32_t RESERVED0[1U]; 1655 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 1656 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 1657 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 1658 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 1659 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 1660 } FPU_Type; 1661 1662 /* Floating-Point Context Control Register Definitions */ 1663 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1664 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1665 1666 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1667 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1668 1669 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ 1670 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ 1671 1672 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ 1673 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ 1674 1675 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ 1676 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ 1677 1678 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ 1679 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ 1680 1681 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ 1682 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ 1683 1684 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ 1685 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ 1686 1687 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 1688 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 1689 1690 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ 1691 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ 1692 1693 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 1694 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 1695 1696 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 1697 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 1698 1699 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 1700 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 1701 1702 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 1703 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 1704 1705 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ 1706 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ 1707 1708 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 1709 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 1710 1711 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 1712 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 1713 1714 /* Floating-Point Context Address Register Definitions */ 1715 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 1716 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 1717 1718 /* Floating-Point Default Status Control Register Definitions */ 1719 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 1720 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 1721 1722 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 1723 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 1724 1725 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 1726 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 1727 1728 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 1729 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 1730 1731 /* Media and FP Feature Register 0 Definitions */ 1732 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 1733 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 1734 1735 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 1736 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 1737 1738 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 1739 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 1740 1741 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 1742 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 1743 1744 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 1745 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 1746 1747 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 1748 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 1749 1750 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 1751 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 1752 1753 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 1754 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 1755 1756 /* Media and FP Feature Register 1 Definitions */ 1757 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 1758 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 1759 1760 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1761 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1762 1763 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1764 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1765 1766 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1767 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 1768 1769 /*@} end of group CMSIS_FPU */ 1770 1771 /** 1772 \ingroup CMSIS_core_register 1773 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1774 \brief Type definitions for the Core Debug Registers 1775 @{ 1776 */ 1777 1778 /** 1779 \brief Structure type to access the Core Debug Register (CoreDebug). 1780 */ 1781 typedef struct { 1782 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1783 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1784 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1785 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1786 uint32_t RESERVED4[1U]; 1787 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 1788 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 1789 } CoreDebug_Type; 1790 1791 /* Debug Halting Control and Status Register Definitions */ 1792 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 1793 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1794 1795 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 1796 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 1797 1798 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1799 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1800 1801 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1802 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1803 1804 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1805 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1806 1807 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 1808 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1809 1810 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 1811 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1812 1813 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 1814 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1815 1816 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 1817 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 1818 1819 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1820 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1821 1822 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 1823 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1824 1825 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 1826 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1827 1828 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1829 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1830 1831 /* Debug Core Register Selector Register Definitions */ 1832 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 1833 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1834 1835 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 1836 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 1837 1838 /* Debug Exception and Monitor Control Register Definitions */ 1839 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 1840 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 1841 1842 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 1843 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 1844 1845 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 1846 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 1847 1848 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 1849 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 1850 1851 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 1852 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 1853 1854 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1855 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1856 1857 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 1858 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 1859 1860 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 1861 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 1862 1863 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 1864 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 1865 1866 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 1867 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 1868 1869 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 1870 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 1871 1872 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 1873 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 1874 1875 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1876 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1877 1878 /* Debug Authentication Control Register Definitions */ 1879 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 1880 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 1881 1882 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 1883 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 1884 1885 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 1886 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 1887 1888 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 1889 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 1890 1891 /* Debug Security Control and Status Register Definitions */ 1892 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 1893 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 1894 1895 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 1896 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 1897 1898 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 1899 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 1900 1901 /*@} end of group CMSIS_CoreDebug */ 1902 1903 /** 1904 \ingroup CMSIS_core_register 1905 \defgroup CMSIS_core_bitfield Core register bit field macros 1906 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1907 @{ 1908 */ 1909 1910 /** 1911 \brief Mask and shift a bit field value for use in a register bit range. 1912 \param[in] field Name of the register bit field. 1913 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1914 \return Masked and shifted value. 1915 */ 1916 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1917 1918 /** 1919 \brief Mask and shift a register value to extract a bit filed value. 1920 \param[in] field Name of the register bit field. 1921 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1922 \return Masked and shifted bit field value. 1923 */ 1924 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1925 1926 /*@} end of group CMSIS_core_bitfield */ 1927 1928 /** 1929 \ingroup CMSIS_core_register 1930 \defgroup CMSIS_core_base Core Definitions 1931 \brief Definitions for base addresses, unions, and structures. 1932 @{ 1933 */ 1934 1935 /* Memory mapping of Core Hardware */ 1936 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1937 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1938 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1939 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1940 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1941 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1942 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1943 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1944 1945 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 1946 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1947 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1948 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1949 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 1950 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1951 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1952 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 1953 1954 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1955 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1956 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1957 #endif 1958 1959 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1960 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 1961 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 1962 #endif 1963 1964 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1965 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1966 1967 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1968 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 1969 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 1970 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 1971 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 1972 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 1973 1974 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ 1975 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 1976 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 1977 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 1978 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 1979 1980 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1981 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 1982 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 1983 #endif 1984 1985 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ 1986 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ 1987 1988 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1989 /*@} */ 1990 1991 /******************************************************************************* 1992 * Hardware Abstraction Layer 1993 Core Function Interface contains: 1994 - Core NVIC Functions 1995 - Core SysTick Functions 1996 - Core Debug Functions 1997 - Core Register Access Functions 1998 ******************************************************************************/ 1999 /** 2000 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 2001 */ 2002 2003 /* ########################## NVIC functions #################################### */ 2004 /** 2005 \ingroup CMSIS_Core_FunctionInterface 2006 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 2007 \brief Functions that manage interrupts and exceptions via the NVIC. 2008 @{ 2009 */ 2010 2011 #ifdef CMSIS_NVIC_VIRTUAL 2012 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 2013 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 2014 #endif 2015 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 2016 #else 2017 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 2018 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 2019 #define NVIC_EnableIRQ __NVIC_EnableIRQ 2020 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 2021 #define NVIC_DisableIRQ __NVIC_DisableIRQ 2022 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 2023 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 2024 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 2025 #define NVIC_GetActive __NVIC_GetActive 2026 #define NVIC_SetPriority __NVIC_SetPriority 2027 #define NVIC_GetPriority __NVIC_GetPriority 2028 #define NVIC_SystemReset __NVIC_SystemReset 2029 #endif /* CMSIS_NVIC_VIRTUAL */ 2030 2031 #ifdef CMSIS_VECTAB_VIRTUAL 2032 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 2033 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 2034 #endif 2035 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 2036 #else 2037 #define NVIC_SetVector __NVIC_SetVector 2038 #define NVIC_GetVector __NVIC_GetVector 2039 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 2040 2041 #define NVIC_USER_IRQ_OFFSET 16 2042 2043 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 2044 2045 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 2046 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 2047 2048 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 2049 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 2050 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 2051 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 2052 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 2053 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 2054 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ 2055 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 2056 2057 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 2058 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 2059 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 2060 #else 2061 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 2062 #endif 2063 2064 /** 2065 \brief Set Priority Grouping 2066 \details Sets the priority grouping field using the required unlock sequence. 2067 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 2068 Only values from 0..7 are used. 2069 In case of a conflict between priority grouping and available 2070 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 2071 \param [in] PriorityGroup Priority grouping field. 2072 */ 2073 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 2074 { 2075 uint32_t reg_value; 2076 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 2077 2078 reg_value = SCB->AIRCR; /* read old register configuration */ 2079 reg_value &= ~((uint32_t) (SCB_AIRCR_VECTKEY_Msk 2080 | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 2081 reg_value = (reg_value | ((uint32_t) 0x5FAUL << SCB_AIRCR_VECTKEY_Pos) 2082 | (PriorityGroupTmp << 8U)); /* Insert write key and priorty group */ 2083 SCB->AIRCR = reg_value; 2084 } 2085 2086 /** 2087 \brief Get Priority Grouping 2088 \details Reads the priority grouping field from the NVIC Interrupt Controller. 2089 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 2090 */ 2091 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 2092 { 2093 return ((uint32_t) ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) 2094 >> SCB_AIRCR_PRIGROUP_Pos)); 2095 } 2096 2097 /** 2098 \brief Enable Interrupt 2099 \details Enables a device specific interrupt in the NVIC interrupt controller. 2100 \param [in] IRQn Device specific interrupt number. 2101 \note IRQn must not be negative. 2102 */ 2103 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 2104 { 2105 if ((int32_t) (IRQn) >= 0) { 2106 NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 2107 << (((uint32_t) IRQn) & 0x1FUL)); 2108 } 2109 } 2110 2111 /** 2112 \brief Get Interrupt Enable status 2113 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 2114 \param [in] IRQn Device specific interrupt number. 2115 \return 0 Interrupt is not enabled. 2116 \return 1 Interrupt is enabled. 2117 \note IRQn must not be negative. 2118 */ 2119 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 2120 { 2121 if ((int32_t) (IRQn) >= 0) { 2122 return ((uint32_t) ( 2123 ((NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] 2124 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 2125 1UL : 0UL)); 2126 } else { 2127 return (0U); 2128 } 2129 } 2130 2131 /** 2132 \brief Disable Interrupt 2133 \details Disables a device specific interrupt in the NVIC interrupt controller. 2134 \param [in] IRQn Device specific interrupt number. 2135 \note IRQn must not be negative. 2136 */ 2137 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 2138 { 2139 if ((int32_t) (IRQn) >= 0) { 2140 NVIC->ICER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 2141 << (((uint32_t) IRQn) & 0x1FUL)); 2142 __DSB(); 2143 __ISB(); 2144 } 2145 } 2146 2147 /** 2148 \brief Get Pending Interrupt 2149 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 2150 \param [in] IRQn Device specific interrupt number. 2151 \return 0 Interrupt status is not pending. 2152 \return 1 Interrupt status is pending. 2153 \note IRQn must not be negative. 2154 */ 2155 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 2156 { 2157 if ((int32_t) (IRQn) >= 0) { 2158 return ((uint32_t) ( 2159 ((NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] 2160 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 2161 1UL : 0UL)); 2162 } else { 2163 return (0U); 2164 } 2165 } 2166 2167 /** 2168 \brief Set Pending Interrupt 2169 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 2170 \param [in] IRQn Device specific interrupt number. 2171 \note IRQn must not be negative. 2172 */ 2173 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 2174 { 2175 if ((int32_t) (IRQn) >= 0) { 2176 NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 2177 << (((uint32_t) IRQn) & 0x1FUL)); 2178 } 2179 } 2180 2181 /** 2182 \brief Clear Pending Interrupt 2183 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 2184 \param [in] IRQn Device specific interrupt number. 2185 \note IRQn must not be negative. 2186 */ 2187 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 2188 { 2189 if ((int32_t) (IRQn) >= 0) { 2190 NVIC->ICPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 2191 << (((uint32_t) IRQn) & 0x1FUL)); 2192 } 2193 } 2194 2195 /** 2196 \brief Get Active Interrupt 2197 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 2198 \param [in] IRQn Device specific interrupt number. 2199 \return 0 Interrupt status is not active. 2200 \return 1 Interrupt status is active. 2201 \note IRQn must not be negative. 2202 */ 2203 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 2204 { 2205 if ((int32_t) (IRQn) >= 0) { 2206 return ((uint32_t) ( 2207 ((NVIC->IABR[(((uint32_t) IRQn) >> 5UL)] 2208 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 2209 1UL : 0UL)); 2210 } else { 2211 return (0U); 2212 } 2213 } 2214 2215 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2216 /** 2217 \brief Get Interrupt Target State 2218 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 2219 \param [in] IRQn Device specific interrupt number. 2220 \return 0 if interrupt is assigned to Secure 2221 \return 1 if interrupt is assigned to Non Secure 2222 \note IRQn must not be negative. 2223 */ 2224 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 2225 { 2226 if ((int32_t)(IRQn) >= 0) 2227 { 2228 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 2229 } 2230 else 2231 { 2232 return(0U); 2233 } 2234 } 2235 2236 /** 2237 \brief Set Interrupt Target State 2238 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 2239 \param [in] IRQn Device specific interrupt number. 2240 \return 0 if interrupt is assigned to Secure 2241 1 if interrupt is assigned to Non Secure 2242 \note IRQn must not be negative. 2243 */ 2244 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 2245 { 2246 if ((int32_t)(IRQn) >= 0) 2247 { 2248 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 2249 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 2250 } 2251 else 2252 { 2253 return(0U); 2254 } 2255 } 2256 2257 /** 2258 \brief Clear Interrupt Target State 2259 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 2260 \param [in] IRQn Device specific interrupt number. 2261 \return 0 if interrupt is assigned to Secure 2262 1 if interrupt is assigned to Non Secure 2263 \note IRQn must not be negative. 2264 */ 2265 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 2266 { 2267 if ((int32_t)(IRQn) >= 0) 2268 { 2269 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 2270 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 2271 } 2272 else 2273 { 2274 return(0U); 2275 } 2276 } 2277 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 2278 2279 /** 2280 \brief Set Interrupt Priority 2281 \details Sets the priority of a device specific interrupt or a processor exception. 2282 The interrupt number can be positive to specify a device specific interrupt, 2283 or negative to specify a processor exception. 2284 \param [in] IRQn Interrupt number. 2285 \param [in] priority Priority to set. 2286 \note The priority cannot be set for every processor exception. 2287 */ 2288 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 2289 { 2290 if ((int32_t) (IRQn) >= 0) { 2291 NVIC->IPR[((uint32_t) IRQn)] = (uint8_t) ((priority 2292 << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL); 2293 } else { 2294 SCB->SHPR[(((uint32_t) IRQn) & 0xFUL) - 4UL] = (uint8_t) ((priority 2295 << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL); 2296 } 2297 } 2298 2299 /** 2300 \brief Get Interrupt Priority 2301 \details Reads the priority of a device specific interrupt or a processor exception. 2302 The interrupt number can be positive to specify a device specific interrupt, 2303 or negative to specify a processor exception. 2304 \param [in] IRQn Interrupt number. 2305 \return Interrupt Priority. 2306 Value is aligned automatically to the implemented priority bits of the microcontroller. 2307 */ 2308 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 2309 { 2310 2311 if ((int32_t) (IRQn) >= 0) { 2312 return (((uint32_t) NVIC->IPR[((uint32_t) IRQn)] 2313 >> (8U - __NVIC_PRIO_BITS))); 2314 } else { 2315 return (((uint32_t) SCB->SHPR[(((uint32_t) IRQn) & 0xFUL) - 4UL] 2316 >> (8U - __NVIC_PRIO_BITS))); 2317 } 2318 } 2319 2320 /** 2321 \brief Encode Priority 2322 \details Encodes the priority for an interrupt with the given priority group, 2323 preemptive priority value, and subpriority value. 2324 In case of a conflict between priority grouping and available 2325 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 2326 \param [in] PriorityGroup Used priority group. 2327 \param [in] PreemptPriority Preemptive priority value (starting from 0). 2328 \param [in] SubPriority Subpriority value (starting from 0). 2329 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 2330 */ 2331 __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, 2332 uint32_t PreemptPriority, uint32_t SubPriority) 2333 { 2334 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 2335 uint32_t PreemptPriorityBits; 2336 uint32_t SubPriorityBits; 2337 2338 PreemptPriorityBits = 2339 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 2340 (uint32_t) (__NVIC_PRIO_BITS) : 2341 (uint32_t) (7UL - PriorityGroupTmp); 2342 SubPriorityBits = 2343 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) 2344 < (uint32_t) 7UL) ? 2345 (uint32_t) 0UL : 2346 (uint32_t) ((PriorityGroupTmp - 7UL) 2347 + (uint32_t) (__NVIC_PRIO_BITS)); 2348 2349 return (((PreemptPriority 2350 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL)) 2351 << SubPriorityBits) 2352 | ((SubPriority & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL)))); 2353 } 2354 2355 /** 2356 \brief Decode Priority 2357 \details Decodes an interrupt priority value with a given priority group to 2358 preemptive priority value and subpriority value. 2359 In case of a conflict between priority grouping and available 2360 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 2361 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 2362 \param [in] PriorityGroup Used priority group. 2363 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 2364 \param [out] pSubPriority Subpriority value (starting from 0). 2365 */ 2366 __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, 2367 uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 2368 uint32_t *const pSubPriority) 2369 { 2370 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 2371 uint32_t PreemptPriorityBits; 2372 uint32_t SubPriorityBits; 2373 2374 PreemptPriorityBits = 2375 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 2376 (uint32_t) (__NVIC_PRIO_BITS) : 2377 (uint32_t) (7UL - PriorityGroupTmp); 2378 SubPriorityBits = 2379 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) 2380 < (uint32_t) 7UL) ? 2381 (uint32_t) 0UL : 2382 (uint32_t) ((PriorityGroupTmp - 7UL) 2383 + (uint32_t) (__NVIC_PRIO_BITS)); 2384 2385 *pPreemptPriority = (Priority >> SubPriorityBits) 2386 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL); 2387 *pSubPriority = (Priority) 2388 & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL); 2389 } 2390 2391 /** 2392 \brief Set Interrupt Vector 2393 \details Sets an interrupt vector in SRAM based interrupt vector table. 2394 The interrupt number can be positive to specify a device specific interrupt, 2395 or negative to specify a processor exception. 2396 VTOR must been relocated to SRAM before. 2397 \param [in] IRQn Interrupt number 2398 \param [in] vector Address of interrupt handler function 2399 */ 2400 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 2401 { 2402 uint32_t *vectors = (uint32_t*) SCB->VTOR; 2403 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 2404 } 2405 2406 /** 2407 \brief Get Interrupt Vector 2408 \details Reads an interrupt vector from interrupt vector table. 2409 The interrupt number can be positive to specify a device specific interrupt, 2410 or negative to specify a processor exception. 2411 \param [in] IRQn Interrupt number. 2412 \return Address of interrupt handler function 2413 */ 2414 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 2415 { 2416 uint32_t *vectors = (uint32_t*) SCB->VTOR; 2417 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 2418 } 2419 2420 /** 2421 \brief System Reset 2422 \details Initiates a system reset request to reset the MCU. 2423 */ 2424 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 2425 { 2426 __DSB(); /* Ensure all outstanding memory accesses included 2427 buffered write are completed before reset */ 2428 SCB->AIRCR = (uint32_t) ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) 2429 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 2430 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 2431 __DSB(); /* Ensure completion of memory access */ 2432 2433 for (;;) /* wait until reset */ 2434 { 2435 __NOP(); 2436 } 2437 } 2438 2439 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2440 /** 2441 \brief Set Priority Grouping (non-secure) 2442 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. 2443 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 2444 Only values from 0..7 are used. 2445 In case of a conflict between priority grouping and available 2446 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 2447 \param [in] PriorityGroup Priority grouping field. 2448 */ 2449 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) 2450 { 2451 uint32_t reg_value; 2452 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 2453 2454 reg_value = SCB_NS->AIRCR; /* read old register configuration */ 2455 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 2456 reg_value = (reg_value | 2457 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 2458 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 2459 SCB_NS->AIRCR = reg_value; 2460 } 2461 2462 /** 2463 \brief Get Priority Grouping (non-secure) 2464 \details Reads the priority grouping field from the non-secure NVIC when in secure state. 2465 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 2466 */ 2467 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) 2468 { 2469 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 2470 } 2471 2472 /** 2473 \brief Enable Interrupt (non-secure) 2474 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 2475 \param [in] IRQn Device specific interrupt number. 2476 \note IRQn must not be negative. 2477 */ 2478 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 2479 { 2480 if ((int32_t)(IRQn) >= 0) 2481 { 2482 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 2483 } 2484 } 2485 2486 /** 2487 \brief Get Interrupt Enable status (non-secure) 2488 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 2489 \param [in] IRQn Device specific interrupt number. 2490 \return 0 Interrupt is not enabled. 2491 \return 1 Interrupt is enabled. 2492 \note IRQn must not be negative. 2493 */ 2494 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 2495 { 2496 if ((int32_t)(IRQn) >= 0) 2497 { 2498 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 2499 } 2500 else 2501 { 2502 return(0U); 2503 } 2504 } 2505 2506 /** 2507 \brief Disable Interrupt (non-secure) 2508 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 2509 \param [in] IRQn Device specific interrupt number. 2510 \note IRQn must not be negative. 2511 */ 2512 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 2513 { 2514 if ((int32_t)(IRQn) >= 0) 2515 { 2516 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 2517 } 2518 } 2519 2520 /** 2521 \brief Get Pending Interrupt (non-secure) 2522 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 2523 \param [in] IRQn Device specific interrupt number. 2524 \return 0 Interrupt status is not pending. 2525 \return 1 Interrupt status is pending. 2526 \note IRQn must not be negative. 2527 */ 2528 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 2529 { 2530 if ((int32_t)(IRQn) >= 0) 2531 { 2532 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 2533 } 2534 else 2535 { 2536 return(0U); 2537 } 2538 } 2539 2540 /** 2541 \brief Set Pending Interrupt (non-secure) 2542 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 2543 \param [in] IRQn Device specific interrupt number. 2544 \note IRQn must not be negative. 2545 */ 2546 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 2547 { 2548 if ((int32_t)(IRQn) >= 0) 2549 { 2550 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 2551 } 2552 } 2553 2554 /** 2555 \brief Clear Pending Interrupt (non-secure) 2556 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 2557 \param [in] IRQn Device specific interrupt number. 2558 \note IRQn must not be negative. 2559 */ 2560 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 2561 { 2562 if ((int32_t)(IRQn) >= 0) 2563 { 2564 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 2565 } 2566 } 2567 2568 /** 2569 \brief Get Active Interrupt (non-secure) 2570 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 2571 \param [in] IRQn Device specific interrupt number. 2572 \return 0 Interrupt status is not active. 2573 \return 1 Interrupt status is active. 2574 \note IRQn must not be negative. 2575 */ 2576 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 2577 { 2578 if ((int32_t)(IRQn) >= 0) 2579 { 2580 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 2581 } 2582 else 2583 { 2584 return(0U); 2585 } 2586 } 2587 2588 /** 2589 \brief Set Interrupt Priority (non-secure) 2590 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 2591 The interrupt number can be positive to specify a device specific interrupt, 2592 or negative to specify a processor exception. 2593 \param [in] IRQn Interrupt number. 2594 \param [in] priority Priority to set. 2595 \note The priority cannot be set for every non-secure processor exception. 2596 */ 2597 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 2598 { 2599 if ((int32_t)(IRQn) >= 0) 2600 { 2601 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 2602 } 2603 else 2604 { 2605 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 2606 } 2607 } 2608 2609 /** 2610 \brief Get Interrupt Priority (non-secure) 2611 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 2612 The interrupt number can be positive to specify a device specific interrupt, 2613 or negative to specify a processor exception. 2614 \param [in] IRQn Interrupt number. 2615 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 2616 */ 2617 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 2618 { 2619 2620 if ((int32_t)(IRQn) >= 0) 2621 { 2622 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 2623 } 2624 else 2625 { 2626 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 2627 } 2628 } 2629 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 2630 2631 /*@} end of CMSIS_Core_NVICFunctions */ 2632 2633 /* ########################## MPU functions #################################### */ 2634 2635 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 2636 2637 #include "mpu_armv8.h" 2638 2639 #endif 2640 2641 /* ########################## FPU functions #################################### */ 2642 /** 2643 \ingroup CMSIS_Core_FunctionInterface 2644 \defgroup CMSIS_Core_FpuFunctions FPU Functions 2645 \brief Function that provides FPU type. 2646 @{ 2647 */ 2648 2649 /** 2650 \brief get FPU type 2651 \details returns the FPU type 2652 \returns 2653 - \b 0: No FPU 2654 - \b 1: Single precision FPU 2655 - \b 2: Double + Single precision FPU 2656 */ 2657 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 2658 { 2659 uint32_t mvfr0; 2660 2661 mvfr0 = FPU->MVFR0; 2662 if ((mvfr0 2663 & (FPU_MVFR0_Single_precision_Msk 2664 | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { 2665 return 2U; /* Double + Single precision FPU */ 2666 } else if ((mvfr0 2667 & (FPU_MVFR0_Single_precision_Msk 2668 | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { 2669 return 1U; /* Single precision FPU */ 2670 } else { 2671 return 0U; /* No FPU */ 2672 } 2673 } 2674 2675 /*@} end of CMSIS_Core_FpuFunctions */ 2676 2677 /* ########################## SAU functions #################################### */ 2678 /** 2679 \ingroup CMSIS_Core_FunctionInterface 2680 \defgroup CMSIS_Core_SAUFunctions SAU Functions 2681 \brief Functions that configure the SAU. 2682 @{ 2683 */ 2684 2685 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2686 2687 /** 2688 \brief Enable SAU 2689 \details Enables the Security Attribution Unit (SAU). 2690 */ 2691 __STATIC_INLINE void TZ_SAU_Enable(void) 2692 { 2693 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 2694 } 2695 2696 2697 2698 /** 2699 \brief Disable SAU 2700 \details Disables the Security Attribution Unit (SAU). 2701 */ 2702 __STATIC_INLINE void TZ_SAU_Disable(void) 2703 { 2704 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 2705 } 2706 2707 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 2708 2709 /*@} end of CMSIS_Core_SAUFunctions */ 2710 2711 /* ################################## SysTick function ############################################ */ 2712 /** 2713 \ingroup CMSIS_Core_FunctionInterface 2714 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 2715 \brief Functions that configure the System. 2716 @{ 2717 */ 2718 2719 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 2720 2721 /** 2722 \brief System Tick Configuration 2723 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 2724 Counter is in free running mode to generate periodic interrupts. 2725 \param [in] ticks Number of ticks between two interrupts. 2726 \return 0 Function succeeded. 2727 \return 1 Function failed. 2728 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 2729 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 2730 must contain a vendor-specific implementation of this function. 2731 */ 2732 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 2733 { 2734 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 2735 { 2736 return (1UL); /* Reload value impossible */ 2737 } 2738 2739 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 2740 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 2741 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 2742 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 2743 SysTick_CTRL_TICKINT_Msk | 2744 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 2745 return (0UL); /* Function successful */ 2746 } 2747 2748 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 2749 /** 2750 \brief System Tick Configuration (non-secure) 2751 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 2752 Counter is in free running mode to generate periodic interrupts. 2753 \param [in] ticks Number of ticks between two interrupts. 2754 \return 0 Function succeeded. 2755 \return 1 Function failed. 2756 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 2757 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 2758 must contain a vendor-specific implementation of this function. 2759 2760 */ 2761 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 2762 { 2763 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 2764 { 2765 return (1UL); /* Reload value impossible */ 2766 } 2767 2768 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 2769 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 2770 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 2771 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 2772 SysTick_CTRL_TICKINT_Msk | 2773 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 2774 return (0UL); /* Function successful */ 2775 } 2776 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 2777 2778 #endif 2779 2780 /*@} end of CMSIS_Core_SysTickFunctions */ 2781 2782 /* ##################################### Debug In/Output function ########################################### */ 2783 /** 2784 \ingroup CMSIS_Core_FunctionInterface 2785 \defgroup CMSIS_core_DebugFunctions ITM Functions 2786 \brief Functions that access the ITM debug interface. 2787 @{ 2788 */ 2789 2790 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 2791 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 2792 2793 /** 2794 \brief ITM Send Character 2795 \details Transmits a character via the ITM channel 0, and 2796 \li Just returns when no debugger is connected that has booked the output. 2797 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 2798 \param [in] ch Character to transmit. 2799 \returns Character to transmit. 2800 */ 2801 __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) 2802 { 2803 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 2804 ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ 2805 { 2806 while (ITM->PORT[0U].u32 == 0UL) { 2807 __NOP(); 2808 } 2809 ITM->PORT[0U].u8 = (uint8_t) ch; 2810 } 2811 return (ch); 2812 } 2813 2814 /** 2815 \brief ITM Receive Character 2816 \details Inputs a character via the external variable \ref ITM_RxBuffer. 2817 \return Received character. 2818 \return -1 No character pending. 2819 */ 2820 __STATIC_INLINE int32_t ITM_ReceiveChar(void) 2821 { 2822 int32_t ch = -1; /* no character available */ 2823 2824 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 2825 ch = ITM_RxBuffer; 2826 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 2827 } 2828 2829 return (ch); 2830 } 2831 2832 /** 2833 \brief ITM Check Character 2834 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 2835 \return 0 No character available. 2836 \return 1 Character available. 2837 */ 2838 __STATIC_INLINE int32_t ITM_CheckChar(void) 2839 { 2840 2841 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 2842 return (0); /* no character available */ 2843 } else { 2844 return (1); /* character available */ 2845 } 2846 } 2847 2848 /*@} end of CMSIS_core_DebugFunctions */ 2849 2850 #ifdef __cplusplus 2851 } 2852 #endif 2853 2854 #endif /* __CORE_ARMV8MML_H_DEPENDANT */ 2855 2856 #endif /* __CMSIS_GENERIC */