Drivers/CMSIS/Include/cmsis_armclang.h (56124B)
1 /**************************************************************************//** 2 * @file cmsis_armclang.h 3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file 4 * @version V5.0.4 5 * @date 10. January 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 /*lint -esym(9058, IRQn)*//* disable MISRA 2012 Rule 2.4 for IRQn */ 26 27 #ifndef __CMSIS_ARMCLANG_H 28 #define __CMSIS_ARMCLANG_H 29 30 #pragma clang system_header /* treat file as system include file */ 31 32 #ifndef __ARM_COMPAT_H 33 #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */ 34 #endif 35 36 /* CMSIS compiler specific defines */ 37 #ifndef __ASM 38 #define __ASM __asm 39 #endif 40 #ifndef __INLINE 41 #define __INLINE __inline 42 #endif 43 #ifndef __STATIC_INLINE 44 #define __STATIC_INLINE static __inline 45 #endif 46 #ifndef __STATIC_FORCEINLINE 47 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline 48 #endif 49 #ifndef __NO_RETURN 50 #define __NO_RETURN __attribute__((__noreturn__)) 51 #endif 52 #ifndef __USED 53 #define __USED __attribute__((used)) 54 #endif 55 #ifndef __WEAK 56 #define __WEAK __attribute__((weak)) 57 #endif 58 #ifndef __PACKED 59 #define __PACKED __attribute__((packed, aligned(1))) 60 #endif 61 #ifndef __PACKED_STRUCT 62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 63 #endif 64 #ifndef __PACKED_UNION 65 #define __PACKED_UNION union __attribute__((packed, aligned(1))) 66 #endif 67 #ifndef __UNALIGNED_UINT32 /* deprecated */ 68 #pragma clang diagnostic push 69 #pragma clang diagnostic ignored "-Wpacked" 70 /*lint -esym(9058, T_UINT32)*//* disable MISRA 2012 Rule 2.4 for T_UINT32 */ 71 struct __attribute__((packed)) T_UINT32 { 72 uint32_t v; 73 }; 74 #pragma clang diagnostic pop 75 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 76 #endif 77 #ifndef __UNALIGNED_UINT16_WRITE 78 #pragma clang diagnostic push 79 #pragma clang diagnostic ignored "-Wpacked" 80 /*lint -esym(9058, T_UINT16_WRITE)*//* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ 81 __PACKED_STRUCT T_UINT16_WRITE { 82 uint16_t v; 83 }; 84 #pragma clang diagnostic pop 85 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 86 #endif 87 #ifndef __UNALIGNED_UINT16_READ 88 #pragma clang diagnostic push 89 #pragma clang diagnostic ignored "-Wpacked" 90 /*lint -esym(9058, T_UINT16_READ)*//* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ 91 __PACKED_STRUCT T_UINT16_READ { 92 uint16_t v; 93 }; 94 #pragma clang diagnostic pop 95 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 96 #endif 97 #ifndef __UNALIGNED_UINT32_WRITE 98 #pragma clang diagnostic push 99 #pragma clang diagnostic ignored "-Wpacked" 100 /*lint -esym(9058, T_UINT32_WRITE)*//* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ 101 __PACKED_STRUCT T_UINT32_WRITE { 102 uint32_t v; 103 }; 104 #pragma clang diagnostic pop 105 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 106 #endif 107 #ifndef __UNALIGNED_UINT32_READ 108 #pragma clang diagnostic push 109 #pragma clang diagnostic ignored "-Wpacked" 110 /*lint -esym(9058, T_UINT32_READ)*//* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ 111 __PACKED_STRUCT T_UINT32_READ { 112 uint32_t v; 113 }; 114 #pragma clang diagnostic pop 115 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 116 #endif 117 #ifndef __ALIGNED 118 #define __ALIGNED(x) __attribute__((aligned(x))) 119 #endif 120 #ifndef __RESTRICT 121 #define __RESTRICT __restrict 122 #endif 123 124 /* ########################### Core Function Access ########################### */ 125 /** \ingroup CMSIS_Core_FunctionInterface 126 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 127 @{ 128 */ 129 130 /** 131 \brief Enable IRQ Interrupts 132 \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 133 Can only be executed in Privileged modes. 134 */ 135 /* intrinsic void __enable_irq(); see arm_compat.h */ 136 137 /** 138 \brief Disable IRQ Interrupts 139 \details Disables IRQ interrupts by setting the I-bit in the CPSR. 140 Can only be executed in Privileged modes. 141 */ 142 /* intrinsic void __disable_irq(); see arm_compat.h */ 143 144 /** 145 \brief Get Control Register 146 \details Returns the content of the Control Register. 147 \return Control Register value 148 */ 149 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 150 { 151 uint32_t result; 152 153 __ASM volatile ("MRS %0, control" : "=r" (result) ); 154 return (result); 155 } 156 157 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 158 /** 159 \brief Get Control Register (non-secure) 160 \details Returns the content of the non-secure Control Register when in secure mode. 161 \return non-secure Control Register value 162 */ 163 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 164 { 165 uint32_t result; 166 167 __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 168 return(result); 169 } 170 #endif 171 172 /** 173 \brief Set Control Register 174 \details Writes the given value to the Control Register. 175 \param [in] control Control Register value to set 176 */ 177 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 178 { 179 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 180 } 181 182 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 183 /** 184 \brief Set Control Register (non-secure) 185 \details Writes the given value to the non-secure Control Register when in secure state. 186 \param [in] control Control Register value to set 187 */ 188 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 189 { 190 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 191 } 192 #endif 193 194 /** 195 \brief Get IPSR Register 196 \details Returns the content of the IPSR Register. 197 \return IPSR Register value 198 */ 199 __STATIC_FORCEINLINE uint32_t __get_IPSR(void) 200 { 201 uint32_t result; 202 203 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 204 return (result); 205 } 206 207 /** 208 \brief Get APSR Register 209 \details Returns the content of the APSR Register. 210 \return APSR Register value 211 */ 212 __STATIC_FORCEINLINE uint32_t __get_APSR(void) 213 { 214 uint32_t result; 215 216 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 217 return (result); 218 } 219 220 /** 221 \brief Get xPSR Register 222 \details Returns the content of the xPSR Register. 223 \return xPSR Register value 224 */ 225 __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 226 { 227 uint32_t result; 228 229 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 230 return (result); 231 } 232 233 /** 234 \brief Get Process Stack Pointer 235 \details Returns the current value of the Process Stack Pointer (PSP). 236 \return PSP Register value 237 */ 238 __STATIC_FORCEINLINE uint32_t __get_PSP(void) 239 { 240 uint32_t result; 241 242 __ASM volatile ("MRS %0, psp" : "=r" (result) ); 243 return (result); 244 } 245 246 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 247 /** 248 \brief Get Process Stack Pointer (non-secure) 249 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. 250 \return PSP Register value 251 */ 252 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) 253 { 254 uint32_t result; 255 256 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 257 return(result); 258 } 259 #endif 260 261 /** 262 \brief Set Process Stack Pointer 263 \details Assigns the given value to the Process Stack Pointer (PSP). 264 \param [in] topOfProcStack Process Stack Pointer value to set 265 */ 266 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 267 { 268 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 269 } 270 271 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 272 /** 273 \brief Set Process Stack Pointer (non-secure) 274 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. 275 \param [in] topOfProcStack Process Stack Pointer value to set 276 */ 277 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 278 { 279 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 280 } 281 #endif 282 283 /** 284 \brief Get Main Stack Pointer 285 \details Returns the current value of the Main Stack Pointer (MSP). 286 \return MSP Register value 287 */ 288 __STATIC_FORCEINLINE uint32_t __get_MSP(void) 289 { 290 uint32_t result; 291 292 __ASM volatile ("MRS %0, msp" : "=r" (result) ); 293 return (result); 294 } 295 296 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 297 /** 298 \brief Get Main Stack Pointer (non-secure) 299 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. 300 \return MSP Register value 301 */ 302 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 303 { 304 uint32_t result; 305 306 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 307 return(result); 308 } 309 #endif 310 311 /** 312 \brief Set Main Stack Pointer 313 \details Assigns the given value to the Main Stack Pointer (MSP). 314 \param [in] topOfMainStack Main Stack Pointer value to set 315 */ 316 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 317 { 318 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 319 } 320 321 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 322 /** 323 \brief Set Main Stack Pointer (non-secure) 324 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 325 \param [in] topOfMainStack Main Stack Pointer value to set 326 */ 327 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 328 { 329 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 330 } 331 #endif 332 333 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 334 /** 335 \brief Get Stack Pointer (non-secure) 336 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 337 \return SP Register value 338 */ 339 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 340 { 341 uint32_t result; 342 343 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 344 return(result); 345 } 346 347 /** 348 \brief Set Stack Pointer (non-secure) 349 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 350 \param [in] topOfStack Stack Pointer value to set 351 */ 352 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 353 { 354 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 355 } 356 #endif 357 358 /** 359 \brief Get Priority Mask 360 \details Returns the current state of the priority mask bit from the Priority Mask Register. 361 \return Priority Mask value 362 */ 363 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 364 { 365 uint32_t result; 366 367 __ASM volatile ("MRS %0, primask" : "=r" (result) ); 368 return (result); 369 } 370 371 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 372 /** 373 \brief Get Priority Mask (non-secure) 374 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. 375 \return Priority Mask value 376 */ 377 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 378 { 379 uint32_t result; 380 381 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); 382 return(result); 383 } 384 #endif 385 386 /** 387 \brief Set Priority Mask 388 \details Assigns the given value to the Priority Mask Register. 389 \param [in] priMask Priority Mask 390 */ 391 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 392 { 393 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 394 } 395 396 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 397 /** 398 \brief Set Priority Mask (non-secure) 399 \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 400 \param [in] priMask Priority Mask 401 */ 402 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 403 { 404 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 405 } 406 #endif 407 408 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 409 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 410 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 411 /** 412 \brief Enable FIQ 413 \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 414 Can only be executed in Privileged modes. 415 */ 416 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */ 417 418 /** 419 \brief Disable FIQ 420 \details Disables FIQ interrupts by setting the F-bit in the CPSR. 421 Can only be executed in Privileged modes. 422 */ 423 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */ 424 425 /** 426 \brief Get Base Priority 427 \details Returns the current value of the Base Priority register. 428 \return Base Priority register value 429 */ 430 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 431 { 432 uint32_t result; 433 434 __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 435 return (result); 436 } 437 438 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 439 /** 440 \brief Get Base Priority (non-secure) 441 \details Returns the current value of the non-secure Base Priority register when in secure state. 442 \return Base Priority register value 443 */ 444 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 445 { 446 uint32_t result; 447 448 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 449 return(result); 450 } 451 #endif 452 453 /** 454 \brief Set Base Priority 455 \details Assigns the given value to the Base Priority register. 456 \param [in] basePri Base Priority value to set 457 */ 458 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 459 { 460 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 461 } 462 463 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 464 /** 465 \brief Set Base Priority (non-secure) 466 \details Assigns the given value to the non-secure Base Priority register when in secure state. 467 \param [in] basePri Base Priority value to set 468 */ 469 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 470 { 471 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 472 } 473 #endif 474 475 /** 476 \brief Set Base Priority with condition 477 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, 478 or the new value increases the BASEPRI priority level. 479 \param [in] basePri Base Priority value to set 480 */ 481 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 482 { 483 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 484 } 485 486 /** 487 \brief Get Fault Mask 488 \details Returns the current value of the Fault Mask register. 489 \return Fault Mask register value 490 */ 491 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 492 { 493 uint32_t result; 494 495 __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 496 return (result); 497 } 498 499 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 500 /** 501 \brief Get Fault Mask (non-secure) 502 \details Returns the current value of the non-secure Fault Mask register when in secure state. 503 \return Fault Mask register value 504 */ 505 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 506 { 507 uint32_t result; 508 509 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 510 return(result); 511 } 512 #endif 513 514 /** 515 \brief Set Fault Mask 516 \details Assigns the given value to the Fault Mask register. 517 \param [in] faultMask Fault Mask value to set 518 */ 519 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 520 { 521 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 522 } 523 524 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 525 /** 526 \brief Set Fault Mask (non-secure) 527 \details Assigns the given value to the non-secure Fault Mask register when in secure state. 528 \param [in] faultMask Fault Mask value to set 529 */ 530 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 531 { 532 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 533 } 534 #endif 535 536 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 537 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 538 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 539 540 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 541 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 542 543 /** 544 \brief Get Process Stack Pointer Limit 545 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 546 Stack Pointer Limit register hence zero is returned always in non-secure 547 mode. 548 549 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 550 \return PSPLIM Register value 551 */ 552 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 553 { 554 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 555 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 556 // without main extensions, the non-secure PSPLIM is RAZ/WI 557 return 0U; 558 #else 559 uint32_t result; 560 __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 561 return result; 562 #endif 563 } 564 565 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 566 /** 567 \brief Get Process Stack Pointer Limit (non-secure) 568 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 569 Stack Pointer Limit register hence zero is returned always in non-secure 570 mode. 571 572 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. 573 \return PSPLIM Register value 574 */ 575 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 576 { 577 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 578 // without main extensions, the non-secure PSPLIM is RAZ/WI 579 return 0U; 580 #else 581 uint32_t result; 582 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 583 return result; 584 #endif 585 } 586 #endif 587 588 /** 589 \brief Set Process Stack Pointer Limit 590 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 591 Stack Pointer Limit register hence the write is silently ignored in non-secure 592 mode. 593 594 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 595 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 596 */ 597 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 598 { 599 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 600 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 601 // without main extensions, the non-secure PSPLIM is RAZ/WI 602 (void)ProcStackPtrLimit; 603 #else 604 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 605 #endif 606 } 607 608 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 609 /** 610 \brief Set Process Stack Pointer (non-secure) 611 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 612 Stack Pointer Limit register hence the write is silently ignored in non-secure 613 mode. 614 615 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. 616 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 617 */ 618 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 619 { 620 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 621 // without main extensions, the non-secure PSPLIM is RAZ/WI 622 (void)ProcStackPtrLimit; 623 #else 624 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 625 #endif 626 } 627 #endif 628 629 /** 630 \brief Get Main Stack Pointer Limit 631 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 632 Stack Pointer Limit register hence zero is returned always. 633 634 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 635 \return MSPLIM Register value 636 */ 637 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 638 { 639 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641 // without main extensions, the non-secure MSPLIM is RAZ/WI 642 return 0U; 643 #else 644 uint32_t result; 645 __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 646 return result; 647 #endif 648 } 649 650 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 651 /** 652 \brief Get Main Stack Pointer Limit (non-secure) 653 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 654 Stack Pointer Limit register hence zero is returned always. 655 656 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. 657 \return MSPLIM Register value 658 */ 659 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 660 { 661 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 662 // without main extensions, the non-secure MSPLIM is RAZ/WI 663 return 0U; 664 #else 665 uint32_t result; 666 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 667 return result; 668 #endif 669 } 670 #endif 671 672 /** 673 \brief Set Main Stack Pointer Limit 674 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 675 Stack Pointer Limit register hence the write is silently ignored. 676 677 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 678 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 679 */ 680 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 681 { 682 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 683 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 684 // without main extensions, the non-secure MSPLIM is RAZ/WI 685 (void)MainStackPtrLimit; 686 #else 687 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 688 #endif 689 } 690 691 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 692 /** 693 \brief Set Main Stack Pointer Limit (non-secure) 694 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 695 Stack Pointer Limit register hence the write is silently ignored. 696 697 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. 698 \param [in] MainStackPtrLimit Main Stack Pointer value to set 699 */ 700 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 701 { 702 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 703 // without main extensions, the non-secure MSPLIM is RAZ/WI 704 (void)MainStackPtrLimit; 705 #else 706 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 707 #endif 708 } 709 #endif 710 711 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 712 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 713 714 /** 715 \brief Get FPSCR 716 \details Returns the current value of the Floating Point Status/Control register. 717 \return Floating Point Status/Control register value 718 */ 719 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 720 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 721 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr 722 #else 723 #define __get_FPSCR() ((uint32_t)0U) 724 #endif 725 726 /** 727 \brief Set FPSCR 728 \details Assigns the given value to the Floating Point Status/Control register. 729 \param [in] fpscr Floating Point Status/Control value to set 730 */ 731 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 732 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 733 #define __set_FPSCR __builtin_arm_set_fpscr 734 #else 735 #define __set_FPSCR(x) ((void)(x)) 736 #endif 737 738 /*@} end of CMSIS_Core_RegAccFunctions */ 739 740 /* ########################## Core Instruction Access ######################### */ 741 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 742 Access to dedicated instructions 743 @{ 744 */ 745 746 /* Define macros for porting to both thumb1 and thumb2. 747 * For thumb1, use low register (r0-r7), specified by constraint "l" 748 * Otherwise, use general registers, specified by constraint "r" */ 749 #if defined (__thumb__) && !defined (__thumb2__) 750 #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 751 #define __CMSIS_GCC_USE_REG(r) "l" (r) 752 #else 753 #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 754 #define __CMSIS_GCC_USE_REG(r) "r" (r) 755 #endif 756 757 /** 758 \brief No Operation 759 \details No Operation does nothing. This instruction can be used for code alignment purposes. 760 */ 761 #define __NOP __builtin_arm_nop 762 763 /** 764 \brief Wait For Interrupt 765 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. 766 */ 767 #define __WFI __builtin_arm_wfi 768 769 /** 770 \brief Wait For Event 771 \details Wait For Event is a hint instruction that permits the processor to enter 772 a low-power state until one of a number of events occurs. 773 */ 774 #define __WFE __builtin_arm_wfe 775 776 /** 777 \brief Send Event 778 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 779 */ 780 #define __SEV __builtin_arm_sev 781 782 /** 783 \brief Instruction Synchronization Barrier 784 \details Instruction Synchronization Barrier flushes the pipeline in the processor, 785 so that all instructions following the ISB are fetched from cache or memory, 786 after the instruction has been completed. 787 */ 788 #define __ISB() __builtin_arm_isb(0xF); 789 790 /** 791 \brief Data Synchronization Barrier 792 \details Acts as a special kind of Data Memory Barrier. 793 It completes when all explicit memory accesses before this instruction complete. 794 */ 795 #define __DSB() __builtin_arm_dsb(0xF); 796 797 /** 798 \brief Data Memory Barrier 799 \details Ensures the apparent order of the explicit memory operations before 800 and after the instruction, without ensuring their completion. 801 */ 802 #define __DMB() __builtin_arm_dmb(0xF); 803 804 /** 805 \brief Reverse byte order (32 bit) 806 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. 807 \param [in] value Value to reverse 808 \return Reversed value 809 */ 810 #define __REV(value) __builtin_bswap32(value) 811 812 /** 813 \brief Reverse byte order (16 bit) 814 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. 815 \param [in] value Value to reverse 816 \return Reversed value 817 */ 818 #define __REV16(value) __ROR(__REV(value), 16) 819 820 /** 821 \brief Reverse byte order (16 bit) 822 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. 823 \param [in] value Value to reverse 824 \return Reversed value 825 */ 826 #define __REVSH(value) (int16_t)__builtin_bswap16(value) 827 828 /** 829 \brief Rotate Right in unsigned value (32 bit) 830 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 831 \param [in] op1 Value to rotate 832 \param [in] op2 Number of Bits to rotate 833 \return Rotated value 834 */ 835 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 836 { 837 op2 %= 32U; 838 if (op2 == 0U) { 839 return op1; 840 } 841 return (op1 >> op2) | (op1 << (32U - op2)); 842 } 843 844 /** 845 \brief Breakpoint 846 \details Causes the processor to enter Debug state. 847 Debug tools can use this to investigate system state when the instruction at a particular address is reached. 848 \param [in] value is ignored by the processor. 849 If required, a debugger can use it to store additional information about the breakpoint. 850 */ 851 #define __BKPT(value) __ASM volatile ("bkpt "#value) 852 853 /** 854 \brief Reverse bit order of value 855 \details Reverses the bit order of the given value. 856 \param [in] value Value to reverse 857 \return Reversed value 858 */ 859 #define __RBIT __builtin_arm_rbit 860 861 /** 862 \brief Count leading zeros 863 \details Counts the number of leading zeros of a data value. 864 \param [in] value Value to count the leading zeros 865 \return number of leading zeros in value 866 */ 867 #define __CLZ (uint8_t)__builtin_clz 868 869 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 870 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 871 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 872 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 873 /** 874 \brief LDR Exclusive (8 bit) 875 \details Executes a exclusive LDR instruction for 8 bit value. 876 \param [in] ptr Pointer to data 877 \return value of type uint8_t at (*ptr) 878 */ 879 #define __LDREXB (uint8_t)__builtin_arm_ldrex 880 881 /** 882 \brief LDR Exclusive (16 bit) 883 \details Executes a exclusive LDR instruction for 16 bit values. 884 \param [in] ptr Pointer to data 885 \return value of type uint16_t at (*ptr) 886 */ 887 #define __LDREXH (uint16_t)__builtin_arm_ldrex 888 889 /** 890 \brief LDR Exclusive (32 bit) 891 \details Executes a exclusive LDR instruction for 32 bit values. 892 \param [in] ptr Pointer to data 893 \return value of type uint32_t at (*ptr) 894 */ 895 #define __LDREXW (uint32_t)__builtin_arm_ldrex 896 897 /** 898 \brief STR Exclusive (8 bit) 899 \details Executes a exclusive STR instruction for 8 bit values. 900 \param [in] value Value to store 901 \param [in] ptr Pointer to location 902 \return 0 Function succeeded 903 \return 1 Function failed 904 */ 905 #define __STREXB (uint32_t)__builtin_arm_strex 906 907 /** 908 \brief STR Exclusive (16 bit) 909 \details Executes a exclusive STR instruction for 16 bit values. 910 \param [in] value Value to store 911 \param [in] ptr Pointer to location 912 \return 0 Function succeeded 913 \return 1 Function failed 914 */ 915 #define __STREXH (uint32_t)__builtin_arm_strex 916 917 /** 918 \brief STR Exclusive (32 bit) 919 \details Executes a exclusive STR instruction for 32 bit values. 920 \param [in] value Value to store 921 \param [in] ptr Pointer to location 922 \return 0 Function succeeded 923 \return 1 Function failed 924 */ 925 #define __STREXW (uint32_t)__builtin_arm_strex 926 927 /** 928 \brief Remove the exclusive lock 929 \details Removes the exclusive lock which is created by LDREX. 930 */ 931 #define __CLREX __builtin_arm_clrex 932 933 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 934 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 935 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 936 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 937 938 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 939 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 940 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 941 942 /** 943 \brief Signed Saturate 944 \details Saturates a signed value. 945 \param [in] value Value to be saturated 946 \param [in] sat Bit position to saturate to (1..32) 947 \return Saturated value 948 */ 949 #define __SSAT __builtin_arm_ssat 950 951 /** 952 \brief Unsigned Saturate 953 \details Saturates an unsigned value. 954 \param [in] value Value to be saturated 955 \param [in] sat Bit position to saturate to (0..31) 956 \return Saturated value 957 */ 958 #define __USAT __builtin_arm_usat 959 960 /** 961 \brief Rotate Right with Extend (32 bit) 962 \details Moves each bit of a bitstring right by one bit. 963 The carry input is shifted in at the left end of the bitstring. 964 \param [in] value Value to rotate 965 \return Rotated value 966 */ 967 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) 968 { 969 uint32_t result; 970 971 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 972 return (result); 973 } 974 975 /** 976 \brief LDRT Unprivileged (8 bit) 977 \details Executes a Unprivileged LDRT instruction for 8 bit value. 978 \param [in] ptr Pointer to data 979 \return value of type uint8_t at (*ptr) 980 */ 981 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) 982 { 983 uint32_t result; 984 985 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); 986 return ((uint8_t) result); /* Add explicit type cast here */ 987 } 988 989 /** 990 \brief LDRT Unprivileged (16 bit) 991 \details Executes a Unprivileged LDRT instruction for 16 bit values. 992 \param [in] ptr Pointer to data 993 \return value of type uint16_t at (*ptr) 994 */ 995 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) 996 { 997 uint32_t result; 998 999 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 1000 return ((uint16_t) result); /* Add explicit type cast here */ 1001 } 1002 1003 /** 1004 \brief LDRT Unprivileged (32 bit) 1005 \details Executes a Unprivileged LDRT instruction for 32 bit values. 1006 \param [in] ptr Pointer to data 1007 \return value of type uint32_t at (*ptr) 1008 */ 1009 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) 1010 { 1011 uint32_t result; 1012 1013 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 1014 return (result); 1015 } 1016 1017 /** 1018 \brief STRT Unprivileged (8 bit) 1019 \details Executes a Unprivileged STRT instruction for 8 bit values. 1020 \param [in] value Value to store 1021 \param [in] ptr Pointer to location 1022 */ 1023 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) 1024 { 1025 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 1026 } 1027 1028 /** 1029 \brief STRT Unprivileged (16 bit) 1030 \details Executes a Unprivileged STRT instruction for 16 bit values. 1031 \param [in] value Value to store 1032 \param [in] ptr Pointer to location 1033 */ 1034 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) 1035 { 1036 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 1037 } 1038 1039 /** 1040 \brief STRT Unprivileged (32 bit) 1041 \details Executes a Unprivileged STRT instruction for 32 bit values. 1042 \param [in] value Value to store 1043 \param [in] ptr Pointer to location 1044 */ 1045 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) 1046 { 1047 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); 1048 } 1049 1050 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1051 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1052 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 1053 1054 /** 1055 \brief Signed Saturate 1056 \details Saturates a signed value. 1057 \param [in] value Value to be saturated 1058 \param [in] sat Bit position to saturate to (1..32) 1059 \return Saturated value 1060 */ 1061 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) 1062 { 1063 if ((sat >= 1U) && (sat <= 32U)) 1064 { 1065 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 1066 const int32_t min = -1 - max ; 1067 if (val > max) 1068 { 1069 return max; 1070 } 1071 else if (val < min) 1072 { 1073 return min; 1074 } 1075 } 1076 return val; 1077 } 1078 1079 /** 1080 \brief Unsigned Saturate 1081 \details Saturates an unsigned value. 1082 \param [in] value Value to be saturated 1083 \param [in] sat Bit position to saturate to (0..31) 1084 \return Saturated value 1085 */ 1086 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) 1087 { 1088 if (sat <= 31U) 1089 { 1090 const uint32_t max = ((1U << sat) - 1U); 1091 if (val > (int32_t)max) 1092 { 1093 return max; 1094 } 1095 else if (val < 0) 1096 { 1097 return 0U; 1098 } 1099 } 1100 return (uint32_t)val; 1101 } 1102 1103 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 1104 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 1105 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 1106 1107 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1108 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 1109 /** 1110 \brief Load-Acquire (8 bit) 1111 \details Executes a LDAB instruction for 8 bit value. 1112 \param [in] ptr Pointer to data 1113 \return value of type uint8_t at (*ptr) 1114 */ 1115 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) 1116 { 1117 uint32_t result; 1118 1119 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); 1120 return ((uint8_t) result); 1121 } 1122 1123 1124 /** 1125 \brief Load-Acquire (16 bit) 1126 \details Executes a LDAH instruction for 16 bit values. 1127 \param [in] ptr Pointer to data 1128 \return value of type uint16_t at (*ptr) 1129 */ 1130 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) 1131 { 1132 uint32_t result; 1133 1134 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); 1135 return ((uint16_t) result); 1136 } 1137 1138 1139 /** 1140 \brief Load-Acquire (32 bit) 1141 \details Executes a LDA instruction for 32 bit values. 1142 \param [in] ptr Pointer to data 1143 \return value of type uint32_t at (*ptr) 1144 */ 1145 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) 1146 { 1147 uint32_t result; 1148 1149 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); 1150 return(result); 1151 } 1152 1153 1154 /** 1155 \brief Store-Release (8 bit) 1156 \details Executes a STLB instruction for 8 bit values. 1157 \param [in] value Value to store 1158 \param [in] ptr Pointer to location 1159 */ 1160 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) 1161 { 1162 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 1163 } 1164 1165 1166 /** 1167 \brief Store-Release (16 bit) 1168 \details Executes a STLH instruction for 16 bit values. 1169 \param [in] value Value to store 1170 \param [in] ptr Pointer to location 1171 */ 1172 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) 1173 { 1174 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 1175 } 1176 1177 1178 /** 1179 \brief Store-Release (32 bit) 1180 \details Executes a STL instruction for 32 bit values. 1181 \param [in] value Value to store 1182 \param [in] ptr Pointer to location 1183 */ 1184 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) 1185 { 1186 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 1187 } 1188 1189 1190 /** 1191 \brief Load-Acquire Exclusive (8 bit) 1192 \details Executes a LDAB exclusive instruction for 8 bit value. 1193 \param [in] ptr Pointer to data 1194 \return value of type uint8_t at (*ptr) 1195 */ 1196 #define __LDAEXB (uint8_t)__builtin_arm_ldaex 1197 1198 1199 /** 1200 \brief Load-Acquire Exclusive (16 bit) 1201 \details Executes a LDAH exclusive instruction for 16 bit values. 1202 \param [in] ptr Pointer to data 1203 \return value of type uint16_t at (*ptr) 1204 */ 1205 #define __LDAEXH (uint16_t)__builtin_arm_ldaex 1206 1207 1208 /** 1209 \brief Load-Acquire Exclusive (32 bit) 1210 \details Executes a LDA exclusive instruction for 32 bit values. 1211 \param [in] ptr Pointer to data 1212 \return value of type uint32_t at (*ptr) 1213 */ 1214 #define __LDAEX (uint32_t)__builtin_arm_ldaex 1215 1216 1217 /** 1218 \brief Store-Release Exclusive (8 bit) 1219 \details Executes a STLB exclusive instruction for 8 bit values. 1220 \param [in] value Value to store 1221 \param [in] ptr Pointer to location 1222 \return 0 Function succeeded 1223 \return 1 Function failed 1224 */ 1225 #define __STLEXB (uint32_t)__builtin_arm_stlex 1226 1227 1228 /** 1229 \brief Store-Release Exclusive (16 bit) 1230 \details Executes a STLH exclusive instruction for 16 bit values. 1231 \param [in] value Value to store 1232 \param [in] ptr Pointer to location 1233 \return 0 Function succeeded 1234 \return 1 Function failed 1235 */ 1236 #define __STLEXH (uint32_t)__builtin_arm_stlex 1237 1238 1239 /** 1240 \brief Store-Release Exclusive (32 bit) 1241 \details Executes a STL exclusive instruction for 32 bit values. 1242 \param [in] value Value to store 1243 \param [in] ptr Pointer to location 1244 \return 0 Function succeeded 1245 \return 1 Function failed 1246 */ 1247 #define __STLEX (uint32_t)__builtin_arm_stlex 1248 1249 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 1250 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 1251 1252 /*@}*//* end of group CMSIS_Core_InstructionInterface */ 1253 1254 /* ################### Compiler specific Intrinsics ########################### */ 1255 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 1256 Access to dedicated SIMD instructions 1257 @{ 1258 */ 1259 1260 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) 1261 1262 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) 1263 { 1264 uint32_t result; 1265 1266 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1267 return(result); 1268 } 1269 1270 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) 1271 { 1272 uint32_t result; 1273 1274 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1275 return(result); 1276 } 1277 1278 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) 1279 { 1280 uint32_t result; 1281 1282 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1283 return(result); 1284 } 1285 1286 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) 1287 { 1288 uint32_t result; 1289 1290 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1291 return(result); 1292 } 1293 1294 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) 1295 { 1296 uint32_t result; 1297 1298 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1299 return(result); 1300 } 1301 1302 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) 1303 { 1304 uint32_t result; 1305 1306 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1307 return(result); 1308 } 1309 1310 1311 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) 1312 { 1313 uint32_t result; 1314 1315 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1316 return(result); 1317 } 1318 1319 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) 1320 { 1321 uint32_t result; 1322 1323 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1324 return(result); 1325 } 1326 1327 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) 1328 { 1329 uint32_t result; 1330 1331 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1332 return(result); 1333 } 1334 1335 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) 1336 { 1337 uint32_t result; 1338 1339 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1340 return(result); 1341 } 1342 1343 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) 1344 { 1345 uint32_t result; 1346 1347 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1348 return(result); 1349 } 1350 1351 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) 1352 { 1353 uint32_t result; 1354 1355 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1356 return(result); 1357 } 1358 1359 1360 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) 1361 { 1362 uint32_t result; 1363 1364 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1365 return(result); 1366 } 1367 1368 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) 1369 { 1370 uint32_t result; 1371 1372 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1373 return(result); 1374 } 1375 1376 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) 1377 { 1378 uint32_t result; 1379 1380 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1381 return(result); 1382 } 1383 1384 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) 1385 { 1386 uint32_t result; 1387 1388 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1389 return(result); 1390 } 1391 1392 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) 1393 { 1394 uint32_t result; 1395 1396 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1397 return(result); 1398 } 1399 1400 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) 1401 { 1402 uint32_t result; 1403 1404 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1405 return(result); 1406 } 1407 1408 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) 1409 { 1410 uint32_t result; 1411 1412 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1413 return(result); 1414 } 1415 1416 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) 1417 { 1418 uint32_t result; 1419 1420 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1421 return(result); 1422 } 1423 1424 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) 1425 { 1426 uint32_t result; 1427 1428 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1429 return(result); 1430 } 1431 1432 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) 1433 { 1434 uint32_t result; 1435 1436 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1437 return(result); 1438 } 1439 1440 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) 1441 { 1442 uint32_t result; 1443 1444 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1445 return(result); 1446 } 1447 1448 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) 1449 { 1450 uint32_t result; 1451 1452 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1453 return(result); 1454 } 1455 1456 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) 1457 { 1458 uint32_t result; 1459 1460 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1461 return(result); 1462 } 1463 1464 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) 1465 { 1466 uint32_t result; 1467 1468 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1469 return(result); 1470 } 1471 1472 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) 1473 { 1474 uint32_t result; 1475 1476 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1477 return(result); 1478 } 1479 1480 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) 1481 { 1482 uint32_t result; 1483 1484 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1485 return(result); 1486 } 1487 1488 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) 1489 { 1490 uint32_t result; 1491 1492 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1493 return(result); 1494 } 1495 1496 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) 1497 { 1498 uint32_t result; 1499 1500 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1501 return(result); 1502 } 1503 1504 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) 1505 { 1506 uint32_t result; 1507 1508 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1509 return(result); 1510 } 1511 1512 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) 1513 { 1514 uint32_t result; 1515 1516 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1517 return(result); 1518 } 1519 1520 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) 1521 { 1522 uint32_t result; 1523 1524 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1525 return(result); 1526 } 1527 1528 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) 1529 { 1530 uint32_t result; 1531 1532 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1533 return(result); 1534 } 1535 1536 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) 1537 { 1538 uint32_t result; 1539 1540 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1541 return(result); 1542 } 1543 1544 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) 1545 { 1546 uint32_t result; 1547 1548 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1549 return(result); 1550 } 1551 1552 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) 1553 { 1554 uint32_t result; 1555 1556 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1557 return(result); 1558 } 1559 1560 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) 1561 { 1562 uint32_t result; 1563 1564 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1565 return(result); 1566 } 1567 1568 #define __SSAT16(ARG1,ARG2) \ 1569 ({ \ 1570 int32_t __RES, __ARG1 = (ARG1); \ 1571 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 1572 __RES; \ 1573 }) 1574 1575 #define __USAT16(ARG1,ARG2) \ 1576 ({ \ 1577 uint32_t __RES, __ARG1 = (ARG1); \ 1578 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 1579 __RES; \ 1580 }) 1581 1582 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) 1583 { 1584 uint32_t result; 1585 1586 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); 1587 return(result); 1588 } 1589 1590 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) 1591 { 1592 uint32_t result; 1593 1594 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1595 return(result); 1596 } 1597 1598 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) 1599 { 1600 uint32_t result; 1601 1602 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); 1603 return(result); 1604 } 1605 1606 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) 1607 { 1608 uint32_t result; 1609 1610 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1611 return(result); 1612 } 1613 1614 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) 1615 { 1616 uint32_t result; 1617 1618 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1619 return(result); 1620 } 1621 1622 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) 1623 { 1624 uint32_t result; 1625 1626 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1627 return(result); 1628 } 1629 1630 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) 1631 { 1632 uint32_t result; 1633 1634 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1635 return(result); 1636 } 1637 1638 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) 1639 { 1640 uint32_t result; 1641 1642 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1643 return(result); 1644 } 1645 1646 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) 1647 { 1648 union llreg_u{ 1649 uint32_t w32[2]; 1650 uint64_t w64; 1651 } llr; 1652 llr.w64 = acc; 1653 1654 #ifndef __ARMEB__ /* Little endian */ 1655 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 1656 #else /* Big endian */ 1657 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 1658 #endif 1659 1660 return(llr.w64); 1661 } 1662 1663 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) 1664 { 1665 union llreg_u{ 1666 uint32_t w32[2]; 1667 uint64_t w64; 1668 } llr; 1669 llr.w64 = acc; 1670 1671 #ifndef __ARMEB__ /* Little endian */ 1672 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 1673 #else /* Big endian */ 1674 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 1675 #endif 1676 1677 return(llr.w64); 1678 } 1679 1680 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) 1681 { 1682 uint32_t result; 1683 1684 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1685 return(result); 1686 } 1687 1688 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) 1689 { 1690 uint32_t result; 1691 1692 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1693 return(result); 1694 } 1695 1696 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) 1697 { 1698 uint32_t result; 1699 1700 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1701 return(result); 1702 } 1703 1704 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) 1705 { 1706 uint32_t result; 1707 1708 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); 1709 return(result); 1710 } 1711 1712 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) 1713 { 1714 union llreg_u{ 1715 uint32_t w32[2]; 1716 uint64_t w64; 1717 } llr; 1718 llr.w64 = acc; 1719 1720 #ifndef __ARMEB__ /* Little endian */ 1721 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 1722 #else /* Big endian */ 1723 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 1724 #endif 1725 1726 return(llr.w64); 1727 } 1728 1729 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) 1730 { 1731 union llreg_u{ 1732 uint32_t w32[2]; 1733 uint64_t w64; 1734 } llr; 1735 llr.w64 = acc; 1736 1737 #ifndef __ARMEB__ /* Little endian */ 1738 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); 1739 #else /* Big endian */ 1740 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); 1741 #endif 1742 1743 return(llr.w64); 1744 } 1745 1746 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) 1747 { 1748 uint32_t result; 1749 1750 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1751 return(result); 1752 } 1753 1754 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) 1755 { 1756 int32_t result; 1757 1758 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1759 return(result); 1760 } 1761 1762 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) 1763 { 1764 int32_t result; 1765 1766 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); 1767 return(result); 1768 } 1769 1770 #if 0 1771 #define __PKHBT(ARG1,ARG2,ARG3) \ 1772 ({ \ 1773 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ 1774 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ 1775 __RES; \ 1776 }) 1777 1778 #define __PKHTB(ARG1,ARG2,ARG3) \ 1779 ({ \ 1780 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ 1781 if (ARG3 == 0) \ 1782 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ 1783 else \ 1784 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ 1785 __RES; \ 1786 }) 1787 #endif 1788 1789 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ 1790 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) 1791 1792 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ 1793 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) 1794 1795 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) 1796 { 1797 int32_t result; 1798 1799 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); 1800 return(result); 1801 } 1802 1803 #endif /* (__ARM_FEATURE_DSP == 1) */ 1804 /*@} end of group CMSIS_SIMD_intrinsics */ 1805 1806 #endif /* __CMSIS_ARMCLANG_H */