tdse-tp0_03-hw_sw_test

FIUBA - Electrónica - Taller de Sistemas Embebidos - Trabajo Práctico N°: 0 - Proyecto N°: 03
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   1 /**
   2  ******************************************************************************
   3  * @file    stm32f1xx.h
   4  * @author  MCD Application Team
   5  * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File. 
   6  *
   7  *          The file is the unique include file that the application programmer
   8  *          is using in the C source code, usually in main.c. This file contains:
   9  *            - Configuration section that allows to select:
  10  *              - The STM32F1xx device used in the target application
  11  *              - To use or not the peripheral's drivers in application code(i.e. 
  12  *                code will be based on direct access to peripheral's registers 
  13  *                rather than drivers API), this option is controlled by 
  14  *                "#define USE_HAL_DRIVER"
  15  *  
  16  ******************************************************************************
  17  * @attention
  18  *
  19  * Copyright (c) 2017-2021 STMicroelectronics.
  20  * All rights reserved.
  21  *
  22  * This software is licensed under terms that can be found in the LICENSE file
  23  * in the root directory of this software component.
  24  * If no LICENSE file comes with this software, it is provided AS-IS.
  25  *
  26  ******************************************************************************
  27  */
  28 
  29 /** @addtogroup CMSIS
  30  * @{
  31  */
  32 
  33 /** @addtogroup stm32f1xx
  34  * @{
  35  */
  36 
  37 #ifndef __STM32F1XX_H
  38 #define __STM32F1XX_H
  39 
  40 #ifdef __cplusplus
  41  extern "C" {
  42 #endif /* __cplusplus */
  43 
  44 /** @addtogroup Library_configuration_section
  45  * @{
  46  */
  47 
  48 /**
  49  * @brief STM32 Family
  50  */
  51 #if !defined (STM32F1)
  52 #define STM32F1
  53 #endif /* STM32F1 */
  54 
  55 /* Uncomment the line below according to the target STM32L device used in your 
  56  application 
  57  */
  58 
  59 #if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
  60     !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
  61     !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
  62   /* #define STM32F100xB  */   /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
  63   /* #define STM32F100xE */    /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
  64   /* #define STM32F101x6  */   /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
  65   /* #define STM32F101xB  */   /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
  66   /* #define STM32F101xE */    /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ 
  67   /* #define STM32F101xG  */   /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
  68   /* #define STM32F102x6 */    /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
  69   /* #define STM32F102xB  */   /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
  70   /* #define STM32F103x6  */   /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
  71   /* #define STM32F103xB  */   /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
  72   /* #define STM32F103xE */    /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
  73   /* #define STM32F103xG  */   /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
  74   /* #define STM32F105xC */    /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
  75   /* #define STM32F107xC  */   /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */  
  76 #endif
  77 
  78 /*  Tip: To avoid modifying this file each time you need to switch between these
  79  devices, you can define the device in your toolchain compiler preprocessor.
  80  */
  81 
  82 #if !defined  (USE_HAL_DRIVER)
  83 /**
  84  * @brief Comment the line below if you will not use the peripherals drivers.
  85    In this case, these drivers will not be included and the application code will 
  86    be based on direct access to peripherals registers 
  87    */
  88   /*#define USE_HAL_DRIVER */
  89 #endif /* USE_HAL_DRIVER */
  90 
  91 /**
  92  * @brief CMSIS Device version number
  93  */
  94 #define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */
  95 #define __STM32F1_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
  96 #define __STM32F1_CMSIS_VERSION_SUB2   (0x05) /*!< [15:8]  sub2 version */
  97 #define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
  98 #define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
  99                                        |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
 100                                        |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
 101                                        |(__STM32F1_CMSIS_VERSION_RC))
 102 
 103 /**
 104  * @}
 105  */
 106 
 107 /** @addtogroup Device_Included
 108  * @{
 109  */
 110 
 111 #if defined(STM32F100xB)
 112   #include "stm32f100xb.h"
 113 #elif defined(STM32F100xE)
 114   #include "stm32f100xe.h"
 115 #elif defined(STM32F101x6)
 116   #include "stm32f101x6.h"
 117 #elif defined(STM32F101xB)
 118   #include "stm32f101xb.h"
 119 #elif defined(STM32F101xE)
 120   #include "stm32f101xe.h"
 121 #elif defined(STM32F101xG)
 122   #include "stm32f101xg.h"
 123 #elif defined(STM32F102x6)
 124   #include "stm32f102x6.h"
 125 #elif defined(STM32F102xB)
 126   #include "stm32f102xb.h"
 127 #elif defined(STM32F103x6)
 128   #include "stm32f103x6.h"
 129 #elif defined(STM32F103xB)
 130 #include "stm32f103xb.h"
 131 #elif defined(STM32F103xE)
 132   #include "stm32f103xe.h"
 133 #elif defined(STM32F103xG)
 134   #include "stm32f103xg.h"
 135 #elif defined(STM32F105xC)
 136   #include "stm32f105xc.h"
 137 #elif defined(STM32F107xC)
 138   #include "stm32f107xc.h"
 139 #else
 140  #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
 141 #endif
 142 
 143 /**
 144  * @}
 145  */
 146 
 147 /** @addtogroup Exported_types
 148  * @{
 149  */
 150 typedef enum {
 151     RESET = 0, SET = !RESET
 152 } FlagStatus, ITStatus;
 153 
 154 typedef enum {
 155     DISABLE = 0, ENABLE = !DISABLE
 156 } FunctionalState;
 157 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
 158 
 159 typedef enum {
 160     SUCCESS = 0U, ERROR = !SUCCESS
 161 } ErrorStatus;
 162 
 163 /**
 164  * @}
 165  */
 166 
 167 /** @addtogroup Exported_macros
 168  * @{
 169  */
 170 #define SET_BIT(REG, BIT)     ((REG) |= (BIT))
 171 
 172 #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
 173 
 174 #define READ_BIT(REG, BIT)    ((REG) & (BIT))
 175 
 176 #define CLEAR_REG(REG)        ((REG) = (0x0))
 177 
 178 #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
 179 
 180 #define READ_REG(REG)         ((REG))
 181 
 182 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
 183 
 184 #define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
 185 
 186 /* Use of CMSIS compiler intrinsics for register exclusive access */
 187 /* Atomic 32-bit register access macro to set one or several bits */
 188 #define ATOMIC_SET_BIT(REG, BIT)                             \
 189   do {                                                       \
 190     uint32_t val;                                            \
 191     do {                                                     \
 192       val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
 193     } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
 194   } while(0)
 195 
 196 /* Atomic 32-bit register access macro to clear one or several bits */
 197 #define ATOMIC_CLEAR_BIT(REG, BIT)                           \
 198   do {                                                       \
 199     uint32_t val;                                            \
 200     do {                                                     \
 201       val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
 202     } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
 203   } while(0)
 204 
 205 /* Atomic 32-bit register access macro to clear and set one or several bits */
 206 #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
 207   do {                                                                     \
 208     uint32_t val;                                                          \
 209     do {                                                                   \
 210       val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
 211     } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
 212   } while(0)
 213 
 214 /* Atomic 16-bit register access macro to set one or several bits */
 215 #define ATOMIC_SETH_BIT(REG, BIT)                            \
 216   do {                                                       \
 217     uint16_t val;                                            \
 218     do {                                                     \
 219       val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
 220     } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
 221   } while(0)
 222 
 223 /* Atomic 16-bit register access macro to clear one or several bits */
 224 #define ATOMIC_CLEARH_BIT(REG, BIT)                          \
 225   do {                                                       \
 226     uint16_t val;                                            \
 227     do {                                                     \
 228       val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
 229     } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
 230   } while(0)
 231 
 232 /* Atomic 16-bit register access macro to clear and set one or several bits */
 233 #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
 234   do {                                                                     \
 235     uint16_t val;                                                          \
 236     do {                                                                   \
 237       val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
 238     } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
 239   } while(0)
 240 
 241 /**
 242  * @}
 243  */
 244 
 245 #if defined (USE_HAL_DRIVER)
 246 #include "stm32f1xx_hal.h"
 247 #endif /* USE_HAL_DRIVER */
 248 
 249 #ifdef __cplusplus
 250 }
 251 #endif /* __cplusplus */
 252 
 253 #endif /* __STM32F1xx_H */
 254 /**
 255  * @}
 256  */
 257 
 258 /**
 259  * @}
 260  */
 261