commit db99ababd2f6291ff564b5f4169ea7200ffe8e41 parent 14427b48a7f3122ef561f7e13c3164200b2093b4 Author: Martin Klöckner <mjkloeckner@gmail.com> Date: Sat, 18 Apr 2026 12:12:26 -0300 Remove `tps/1/src/tb/rtc_tb.vhd` Diffstat:
| D | tps/1/src/tb/rtc_tb.vhd | | | 27 | --------------------------- |
1 file changed, 0 insertions(+), 27 deletions(-) diff --git a/tps/1/src/tb/rtc_tb.vhd b/tps/1/src/tb/rtc_tb.vhd @@ -1,27 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity rtc_tb is -end entity; - -architecture rtc_arq of rtc_tb is - - constant CLK_FREQ : integer := 1e6; -- 1 MHz clock frecuency - - signal sig_clk : std_logic := '1'; - signal sig_rst : std_logic := '0'; - signal sig_seg_flag : std_logic; - -begin - - rtc : entity work.rtc(rtc_arq) - generic map(clk_freq => CLK_FREQ) - port map( - clk => sig_clk, - rst => sig_rst, - seg_flag => sig_seg_flag); - - sig_clk <= not sig_clk after 500 ns; -- 1 MHz clock frequency - -end architecture;