Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c (51686B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_adc_ex.c 4 * @author MCD Application Team 5 * @brief This file provides firmware functions to manage the following 6 * functionalities of the Analog to Digital Convertor (ADC) 7 * peripheral: 8 * + Peripheral Control functions 9 * Other functions (generic functions) are available in file 10 * "stm32f1xx_hal_adc.c". 11 * 12 ****************************************************************************** 13 * @attention 14 * 15 * Copyright (c) 2016 STMicroelectronics. 16 * All rights reserved. 17 * 18 * This software is licensed under terms that can be found in the LICENSE file 19 * in the root directory of this software component. 20 * If no LICENSE file comes with this software, it is provided AS-IS. 21 * 22 ****************************************************************************** 23 @verbatim 24 [..] 25 (@) Sections "ADC peripheral features" and "How to use this driver" are 26 available in file of generic functions "stm32f1xx_hal_adc.c". 27 [..] 28 @endverbatim 29 */ 30 31 /* Includes ------------------------------------------------------------------*/ 32 #include "stm32f1xx_hal.h" 33 34 /** @addtogroup STM32F1xx_HAL_Driver 35 * @{ 36 */ 37 38 /** @defgroup ADCEx ADCEx 39 * @brief ADC Extension HAL module driver 40 * @{ 41 */ 42 43 #ifdef HAL_ADC_MODULE_ENABLED 44 45 /* Private typedef -----------------------------------------------------------*/ 46 /* Private define ------------------------------------------------------------*/ 47 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants 48 * @{ 49 */ 50 51 /* Delay for ADC calibration: */ 52 /* Hardware prerequisite before starting a calibration: the ADC must have */ 53 /* been in power-on state for at least two ADC clock cycles. */ 54 /* Unit: ADC clock cycles */ 55 #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U 56 57 /* Timeout value for ADC calibration */ 58 /* Value defined to be higher than worst cases: low clocks freq, */ 59 /* maximum prescaler. */ 60 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ 61 /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ 62 /* Unit: ms */ 63 #define ADC_CALIBRATION_TIMEOUT 10U 64 65 /* Delay for temperature sensor stabilization time. */ 66 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ 67 /* Unit: us */ 68 #define ADC_TEMPSENSOR_DELAY_US 10U 69 70 /** 71 * @} 72 */ 73 74 /* Private macro -------------------------------------------------------------*/ 75 /* Private variables ---------------------------------------------------------*/ 76 /* Private function prototypes -----------------------------------------------*/ 77 /* Private functions ---------------------------------------------------------*/ 78 79 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions 80 * @{ 81 */ 82 83 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions 84 * @brief Extended Extended Input and Output operation functions 85 * 86 @verbatim 87 =============================================================================== 88 ##### IO operation functions ##### 89 =============================================================================== 90 [..] This section provides functions allowing to: 91 (+) Start conversion of injected group. 92 (+) Stop conversion of injected group. 93 (+) Poll for conversion complete on injected group. 94 (+) Get result of injected channel conversion. 95 (+) Start conversion of injected group and enable interruptions. 96 (+) Stop conversion of injected group and disable interruptions. 97 98 (+) Start multimode and enable DMA transfer. 99 (+) Stop multimode and disable ADC DMA transfer. 100 (+) Get result of multimode conversion. 101 102 (+) Perform the ADC self-calibration for single or differential ending. 103 (+) Get calibration factors for single or differential ending. 104 (+) Set calibration factors for single or differential ending. 105 106 @endverbatim 107 * @{ 108 */ 109 110 /** 111 * @brief Perform an ADC automatic self-calibration 112 * Calibration prerequisite: ADC must be disabled (execute this 113 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). 114 * During calibration process, ADC is enabled. ADC is let enabled at 115 * the completion of this function. 116 * @param hadc: ADC handle 117 * @retval HAL status 118 */ 119 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) 120 { 121 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 122 uint32_t tickstart; 123 __IO uint32_t wait_loop_index = 0U; 124 125 /* Check the parameters */ 126 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 127 128 /* Process locked */ 129 __HAL_LOCK(hadc); 130 131 /* 1. Disable ADC peripheral */ 132 tmp_hal_status = ADC_ConversionStop_Disable(hadc); 133 134 /* 2. Calibration prerequisite delay before starting the calibration. */ 135 /* - ADC must be enabled for at least two ADC clock cycles */ 136 tmp_hal_status = ADC_Enable(hadc); 137 138 /* Check if ADC is effectively enabled */ 139 if (tmp_hal_status == HAL_OK) 140 { 141 /* Set ADC state */ 142 ADC_STATE_CLR_SET(hadc->State, 143 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 144 HAL_ADC_STATE_BUSY_INTERNAL); 145 146 /* Hardware prerequisite: delay before starting the calibration. */ 147 /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ 148 /* - Wait for the expected ADC clock cycles delay */ 149 wait_loop_index = ((SystemCoreClock 150 / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 151 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); 152 153 while(wait_loop_index != 0U) 154 { 155 wait_loop_index--; 156 } 157 158 /* 3. Resets ADC calibration registers */ 159 SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); 160 161 tickstart = HAL_GetTick(); 162 163 /* Wait for calibration reset completion */ 164 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 165 { 166 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 167 { 168 /* New check to avoid false timeout detection in case of preemption */ 169 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) 170 { 171 /* Update ADC state machine to error */ 172 ADC_STATE_CLR_SET(hadc->State, 173 HAL_ADC_STATE_BUSY_INTERNAL, 174 HAL_ADC_STATE_ERROR_INTERNAL); 175 176 /* Process unlocked */ 177 __HAL_UNLOCK(hadc); 178 179 return HAL_ERROR; 180 } 181 } 182 } 183 184 /* 4. Start ADC calibration */ 185 SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); 186 187 tickstart = HAL_GetTick(); 188 189 /* Wait for calibration completion */ 190 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 191 { 192 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) 193 { 194 /* New check to avoid false timeout detection in case of preemption */ 195 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) 196 { 197 /* Update ADC state machine to error */ 198 ADC_STATE_CLR_SET(hadc->State, 199 HAL_ADC_STATE_BUSY_INTERNAL, 200 HAL_ADC_STATE_ERROR_INTERNAL); 201 202 /* Process unlocked */ 203 __HAL_UNLOCK(hadc); 204 205 return HAL_ERROR; 206 } 207 } 208 } 209 210 /* Set ADC state */ 211 ADC_STATE_CLR_SET(hadc->State, 212 HAL_ADC_STATE_BUSY_INTERNAL, 213 HAL_ADC_STATE_READY); 214 } 215 216 /* Process unlocked */ 217 __HAL_UNLOCK(hadc); 218 219 /* Return function status */ 220 return tmp_hal_status; 221 } 222 223 /** 224 * @brief Enables ADC, starts conversion of injected group. 225 * Interruptions enabled in this function: None. 226 * @param hadc: ADC handle 227 * @retval HAL status 228 */ 229 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) 230 { 231 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 232 233 /* Check the parameters */ 234 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 235 236 /* Process locked */ 237 __HAL_LOCK(hadc); 238 239 /* Enable the ADC peripheral */ 240 tmp_hal_status = ADC_Enable(hadc); 241 242 /* Start conversion if ADC is effectively enabled */ 243 if (tmp_hal_status == HAL_OK) 244 { 245 /* Set ADC state */ 246 /* - Clear state bitfield related to injected group conversion results */ 247 /* - Set state bitfield related to injected operation */ 248 ADC_STATE_CLR_SET(hadc->State, 249 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, 250 HAL_ADC_STATE_INJ_BUSY); 251 252 /* Case of independent mode or multimode (for devices with several ADCs): */ 253 /* Set multimode state. */ 254 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 255 { 256 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 257 } 258 else 259 { 260 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 261 } 262 263 /* Check if a regular conversion is ongoing */ 264 /* Note: On this device, there is no ADC error code fields related to */ 265 /* conversions on group injected only. In case of conversion on */ 266 /* going on group regular, no error code is reset. */ 267 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 268 { 269 /* Reset ADC all error code fields */ 270 ADC_CLEAR_ERRORCODE(hadc); 271 } 272 273 /* Process unlocked */ 274 /* Unlock before starting ADC conversions: in case of potential */ 275 /* interruption, to let the process to ADC IRQ Handler. */ 276 __HAL_UNLOCK(hadc); 277 278 /* Clear injected group conversion flag */ 279 /* (To ensure of no unknown state from potential previous ADC operations) */ 280 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); 281 282 /* Enable conversion of injected group. */ 283 /* If software start has been selected, conversion starts immediately. */ 284 /* If external trigger has been selected, conversion will start at next */ 285 /* trigger event. */ 286 /* If automatic injected conversion is enabled, conversion will start */ 287 /* after next regular group conversion. */ 288 /* Case of multimode enabled (for devices with several ADCs): if ADC is */ 289 /* slave, ADC is enabled only (conversion is not started). If ADC is */ 290 /* master, ADC is enabled and conversion is started. */ 291 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) 292 { 293 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && 294 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 295 { 296 /* Start ADC conversion on injected group with SW start */ 297 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); 298 } 299 else 300 { 301 /* Start ADC conversion on injected group with external trigger */ 302 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); 303 } 304 } 305 } 306 else 307 { 308 /* Process unlocked */ 309 __HAL_UNLOCK(hadc); 310 } 311 312 /* Return function status */ 313 return tmp_hal_status; 314 } 315 316 /** 317 * @brief Stop conversion of injected channels. Disable ADC peripheral if 318 * no regular conversion is on going. 319 * @note If ADC must be disabled and if conversion is on going on 320 * regular group, function HAL_ADC_Stop must be used to stop both 321 * injected and regular groups, and disable the ADC. 322 * @note If injected group mode auto-injection is enabled, 323 * function HAL_ADC_Stop must be used. 324 * @note In case of auto-injection mode, HAL_ADC_Stop must be used. 325 * @param hadc: ADC handle 326 * @retval None 327 */ 328 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) 329 { 330 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 331 332 /* Check the parameters */ 333 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 334 335 /* Process locked */ 336 __HAL_LOCK(hadc); 337 338 /* Stop potential conversion and disable ADC peripheral */ 339 /* Conditioned to: */ 340 /* - No conversion on the other group (regular group) is intended to */ 341 /* continue (injected and regular groups stop conversion and ADC disable */ 342 /* are common) */ 343 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ 344 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && 345 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) 346 { 347 /* Stop potential conversion on going, on regular and injected groups */ 348 /* Disable ADC peripheral */ 349 tmp_hal_status = ADC_ConversionStop_Disable(hadc); 350 351 /* Check if ADC is effectively disabled */ 352 if (tmp_hal_status == HAL_OK) 353 { 354 /* Set ADC state */ 355 ADC_STATE_CLR_SET(hadc->State, 356 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 357 HAL_ADC_STATE_READY); 358 } 359 } 360 else 361 { 362 /* Update ADC state machine to error */ 363 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 364 365 tmp_hal_status = HAL_ERROR; 366 } 367 368 /* Process unlocked */ 369 __HAL_UNLOCK(hadc); 370 371 /* Return function status */ 372 return tmp_hal_status; 373 } 374 375 /** 376 * @brief Wait for injected group conversion to be completed. 377 * @param hadc: ADC handle 378 * @param Timeout: Timeout value in millisecond. 379 * @retval HAL status 380 */ 381 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) 382 { 383 uint32_t tickstart; 384 385 /* Variables for polling in case of scan mode enabled and polling for each */ 386 /* conversion. */ 387 __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; 388 uint32_t Conversion_Timeout_CPU_cycles_max = 0U; 389 390 /* Check the parameters */ 391 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 392 393 /* Get timeout */ 394 tickstart = HAL_GetTick(); 395 396 /* Polling for end of conversion: differentiation if single/sequence */ 397 /* conversion. */ 398 /* For injected group, flag JEOC is set only at the end of the sequence, */ 399 /* not for each conversion within the sequence. */ 400 /* - If single conversion for injected group (scan mode disabled or */ 401 /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */ 402 /* conversion completion. */ 403 /* - If sequence conversion for injected group (scan mode enabled and */ 404 /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ 405 /* sequence. */ 406 /* To poll for each conversion, the maximum conversion time is computed */ 407 /* from ADC conversion time (selected sampling time + conversion time of */ 408 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ 409 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ 410 /* As flag JEOC is not set after each conversion, no timeout status can */ 411 /* be set. */ 412 if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) 413 { 414 /* Wait until End of Conversion flag is raised */ 415 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) 416 { 417 /* Check if timeout is disabled (set to infinite wait) */ 418 if(Timeout != HAL_MAX_DELAY) 419 { 420 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) 421 { 422 /* New check to avoid false timeout detection in case of preemption */ 423 if(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) 424 { 425 /* Update ADC state machine to timeout */ 426 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 427 428 /* Process unlocked */ 429 __HAL_UNLOCK(hadc); 430 431 return HAL_TIMEOUT; 432 } 433 } 434 } 435 } 436 } 437 else 438 { 439 /* Replace polling by wait for maximum conversion time */ 440 /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ 441 /* and ADC maximum conversion cycles on all channels. */ 442 /* - Wait for the expected ADC clock cycles delay */ 443 Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock 444 / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) 445 * ADC_CONVCYCLES_MAX_RANGE(hadc) ); 446 447 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 448 { 449 /* Check if timeout is disabled (set to infinite wait) */ 450 if(Timeout != HAL_MAX_DELAY) 451 { 452 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) 453 { 454 /* New check to avoid false timeout detection in case of preemption */ 455 if(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) 456 { 457 /* Update ADC state machine to timeout */ 458 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 459 460 /* Process unlocked */ 461 __HAL_UNLOCK(hadc); 462 463 return HAL_TIMEOUT; 464 } 465 } 466 } 467 Conversion_Timeout_CPU_cycles ++; 468 } 469 } 470 471 /* Clear injected group conversion flag */ 472 /* Note: On STM32F1 ADC, clear regular conversion flag raised */ 473 /* simultaneously. */ 474 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); 475 476 /* Update ADC state machine */ 477 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 478 479 /* Determine whether any further conversion upcoming on group injected */ 480 /* by external trigger or by automatic injected conversion */ 481 /* from group regular. */ 482 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 483 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 484 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 485 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 486 { 487 /* Set ADC state */ 488 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 489 490 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 491 { 492 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 493 } 494 } 495 496 /* Return ADC state */ 497 return HAL_OK; 498 } 499 500 /** 501 * @brief Enables ADC, starts conversion of injected group with interruption. 502 * - JEOC (end of conversion of injected group) 503 * Each of these interruptions has its dedicated callback function. 504 * @param hadc: ADC handle 505 * @retval HAL status. 506 */ 507 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) 508 { 509 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 510 511 /* Check the parameters */ 512 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 513 514 /* Process locked */ 515 __HAL_LOCK(hadc); 516 517 /* Enable the ADC peripheral */ 518 tmp_hal_status = ADC_Enable(hadc); 519 520 /* Start conversion if ADC is effectively enabled */ 521 if (tmp_hal_status == HAL_OK) 522 { 523 /* Set ADC state */ 524 /* - Clear state bitfield related to injected group conversion results */ 525 /* - Set state bitfield related to injected operation */ 526 ADC_STATE_CLR_SET(hadc->State, 527 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, 528 HAL_ADC_STATE_INJ_BUSY); 529 530 /* Case of independent mode or multimode (for devices with several ADCs): */ 531 /* Set multimode state. */ 532 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 533 { 534 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 535 } 536 else 537 { 538 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 539 } 540 541 /* Check if a regular conversion is ongoing */ 542 /* Note: On this device, there is no ADC error code fields related to */ 543 /* conversions on group injected only. In case of conversion on */ 544 /* going on group regular, no error code is reset. */ 545 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 546 { 547 /* Reset ADC all error code fields */ 548 ADC_CLEAR_ERRORCODE(hadc); 549 } 550 551 /* Process unlocked */ 552 /* Unlock before starting ADC conversions: in case of potential */ 553 /* interruption, to let the process to ADC IRQ Handler. */ 554 __HAL_UNLOCK(hadc); 555 556 /* Clear injected group conversion flag */ 557 /* (To ensure of no unknown state from potential previous ADC operations) */ 558 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); 559 560 /* Enable end of conversion interrupt for injected channels */ 561 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); 562 563 /* Start conversion of injected group if software start has been selected */ 564 /* and if automatic injected conversion is disabled. */ 565 /* If external trigger has been selected, conversion will start at next */ 566 /* trigger event. */ 567 /* If automatic injected conversion is enabled, conversion will start */ 568 /* after next regular group conversion. */ 569 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) 570 { 571 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && 572 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) ) 573 { 574 /* Start ADC conversion on injected group with SW start */ 575 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); 576 } 577 else 578 { 579 /* Start ADC conversion on injected group with external trigger */ 580 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG); 581 } 582 } 583 } 584 else 585 { 586 /* Process unlocked */ 587 __HAL_UNLOCK(hadc); 588 } 589 590 /* Return function status */ 591 return tmp_hal_status; 592 } 593 594 /** 595 * @brief Stop conversion of injected channels, disable interruption of 596 * end-of-conversion. Disable ADC peripheral if no regular conversion 597 * is on going. 598 * @note If ADC must be disabled and if conversion is on going on 599 * regular group, function HAL_ADC_Stop must be used to stop both 600 * injected and regular groups, and disable the ADC. 601 * @note If injected group mode auto-injection is enabled, 602 * function HAL_ADC_Stop must be used. 603 * @param hadc: ADC handle 604 * @retval None 605 */ 606 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) 607 { 608 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 609 610 /* Check the parameters */ 611 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 612 613 /* Process locked */ 614 __HAL_LOCK(hadc); 615 616 /* Stop potential conversion and disable ADC peripheral */ 617 /* Conditioned to: */ 618 /* - No conversion on the other group (regular group) is intended to */ 619 /* continue (injected and regular groups stop conversion and ADC disable */ 620 /* are common) */ 621 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ 622 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && 623 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) 624 { 625 /* Stop potential conversion on going, on regular and injected groups */ 626 /* Disable ADC peripheral */ 627 tmp_hal_status = ADC_ConversionStop_Disable(hadc); 628 629 /* Check if ADC is effectively disabled */ 630 if (tmp_hal_status == HAL_OK) 631 { 632 /* Disable ADC end of conversion interrupt for injected channels */ 633 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 634 635 /* Set ADC state */ 636 ADC_STATE_CLR_SET(hadc->State, 637 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 638 HAL_ADC_STATE_READY); 639 } 640 } 641 else 642 { 643 /* Update ADC state machine to error */ 644 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 645 646 tmp_hal_status = HAL_ERROR; 647 } 648 649 /* Process unlocked */ 650 __HAL_UNLOCK(hadc); 651 652 /* Return function status */ 653 return tmp_hal_status; 654 } 655 656 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) 657 /** 658 * @brief Enables ADC, starts conversion of regular group and transfers result 659 * through DMA. 660 * Multimode must have been previously configured using 661 * HAL_ADCEx_MultiModeConfigChannel() function. 662 * Interruptions enabled in this function: 663 * - DMA transfer complete 664 * - DMA half transfer 665 * Each of these interruptions has its dedicated callback function. 666 * @note: On STM32F1 devices, ADC slave regular group must be configured 667 * with conversion trigger ADC_SOFTWARE_START. 668 * @note: ADC slave can be enabled preliminarily using single-mode 669 * HAL_ADC_Start() function. 670 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) 671 * @param pData: The destination Buffer address. 672 * @param Length: The length of data to be transferred from ADC peripheral to memory. 673 * @retval None 674 */ 675 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) 676 { 677 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 678 ADC_HandleTypeDef tmphadcSlave={0}; 679 680 /* Check the parameters */ 681 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 682 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 683 684 /* Process locked */ 685 __HAL_LOCK(hadc); 686 687 /* Set a temporary handle of the ADC slave associated to the ADC master */ 688 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 689 690 /* On STM32F1 devices, ADC slave regular group must be configured with */ 691 /* conversion trigger ADC_SOFTWARE_START. */ 692 /* Note: External trigger of ADC slave must be enabled, it is already done */ 693 /* into function "HAL_ADC_Init()". */ 694 if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) 695 { 696 /* Update ADC state machine to error */ 697 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 698 699 /* Process unlocked */ 700 __HAL_UNLOCK(hadc); 701 702 return HAL_ERROR; 703 } 704 705 /* Enable the ADC peripherals: master and slave (in case if not already */ 706 /* enabled previously) */ 707 tmp_hal_status = ADC_Enable(hadc); 708 if (tmp_hal_status == HAL_OK) 709 { 710 tmp_hal_status = ADC_Enable(&tmphadcSlave); 711 } 712 713 /* Start conversion if all ADCs of multimode are effectively enabled */ 714 if (tmp_hal_status == HAL_OK) 715 { 716 /* Set ADC state (ADC master) */ 717 /* - Clear state bitfield related to regular group conversion results */ 718 /* - Set state bitfield related to regular operation */ 719 ADC_STATE_CLR_SET(hadc->State, 720 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE, 721 HAL_ADC_STATE_REG_BUSY); 722 723 /* If conversions on group regular are also triggering group injected, */ 724 /* update ADC state. */ 725 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 726 { 727 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 728 } 729 730 /* Process unlocked */ 731 /* Unlock before starting ADC conversions: in case of potential */ 732 /* interruption, to let the process to ADC IRQ Handler. */ 733 __HAL_UNLOCK(hadc); 734 735 /* Set ADC error code to none */ 736 ADC_CLEAR_ERRORCODE(hadc); 737 738 739 /* Set the DMA transfer complete callback */ 740 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 741 742 /* Set the DMA half transfer complete callback */ 743 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 744 745 /* Set the DMA error callback */ 746 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 747 748 749 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ 750 /* start (in case of SW start): */ 751 752 /* Clear regular group conversion flag and overrun flag */ 753 /* (To ensure of no unknown state from potential previous ADC operations) */ 754 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 755 756 /* Enable ADC DMA mode of ADC master */ 757 SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 758 759 /* Start the DMA channel */ 760 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 761 762 /* Start conversion of regular group if software start has been selected. */ 763 /* If external trigger has been selected, conversion will start at next */ 764 /* trigger event. */ 765 /* Note: Alternate trigger for single conversion could be to force an */ 766 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ 767 if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) 768 { 769 /* Start ADC conversion on regular group with SW start */ 770 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 771 } 772 else 773 { 774 /* Start ADC conversion on regular group with external trigger */ 775 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); 776 } 777 } 778 else 779 { 780 /* Process unlocked */ 781 __HAL_UNLOCK(hadc); 782 } 783 784 /* Return function status */ 785 return tmp_hal_status; 786 } 787 788 /** 789 * @brief Stop ADC conversion of regular group (and injected channels in 790 * case of auto_injection mode), disable ADC DMA transfer, disable 791 * ADC peripheral. 792 * @note Multimode is kept enabled after this function. To disable multimode 793 * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be 794 * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit(). 795 * @note In case of DMA configured in circular mode, function 796 * HAL_ADC_Stop_DMA must be called after this function with handle of 797 * ADC slave, to properly disable the DMA channel. 798 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) 799 * @retval None 800 */ 801 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) 802 { 803 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 804 ADC_HandleTypeDef tmphadcSlave={0}; 805 806 /* Check the parameters */ 807 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 808 809 /* Process locked */ 810 __HAL_LOCK(hadc); 811 812 /* Stop potential conversion on going, on regular and injected groups */ 813 /* Disable ADC master peripheral */ 814 tmp_hal_status = ADC_ConversionStop_Disable(hadc); 815 816 /* Check if ADC is effectively disabled */ 817 if(tmp_hal_status == HAL_OK) 818 { 819 /* Set a temporary handle of the ADC slave associated to the ADC master */ 820 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 821 822 /* Disable ADC slave peripheral */ 823 tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave); 824 825 /* Check if ADC is effectively disabled */ 826 if(tmp_hal_status != HAL_OK) 827 { 828 /* Update ADC state machine to error */ 829 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 830 831 /* Process unlocked */ 832 __HAL_UNLOCK(hadc); 833 834 return HAL_ERROR; 835 } 836 837 /* Disable ADC DMA mode */ 838 CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); 839 840 /* Reset configuration of ADC DMA continuous request for dual mode */ 841 CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD); 842 843 /* Disable the DMA channel (in case of DMA in circular mode or stop while */ 844 /* while DMA transfer is on going) */ 845 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 846 847 /* Change ADC state (ADC master) */ 848 ADC_STATE_CLR_SET(hadc->State, 849 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 850 HAL_ADC_STATE_READY); 851 } 852 853 /* Process unlocked */ 854 __HAL_UNLOCK(hadc); 855 856 /* Return function status */ 857 return tmp_hal_status; 858 } 859 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ 860 861 /** 862 * @brief Get ADC injected group conversion result. 863 * @note Reading register JDRx automatically clears ADC flag JEOC 864 * (ADC group injected end of unitary conversion). 865 * @note This function does not clear ADC flag JEOS 866 * (ADC group injected end of sequence conversion) 867 * Occurrence of flag JEOS rising: 868 * - If sequencer is composed of 1 rank, flag JEOS is equivalent 869 * to flag JEOC. 870 * - If sequencer is composed of several ranks, during the scan 871 * sequence flag JEOC only is raised, at the end of the scan sequence 872 * both flags JEOC and EOS are raised. 873 * Flag JEOS must not be cleared by this function because 874 * it would not be compliant with low power features 875 * (feature low power auto-wait, not available on all STM32 families). 876 * To clear this flag, either use function: 877 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming 878 * model polling: @ref HAL_ADCEx_InjectedPollForConversion() 879 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). 880 * @param hadc: ADC handle 881 * @param InjectedRank: the converted ADC injected rank. 882 * This parameter can be one of the following values: 883 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected 884 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected 885 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected 886 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected 887 * @retval ADC group injected conversion data 888 */ 889 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) 890 { 891 uint32_t tmp_jdr = 0U; 892 893 /* Check the parameters */ 894 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 895 assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); 896 897 /* Get ADC converted value */ 898 switch(InjectedRank) 899 { 900 case ADC_INJECTED_RANK_4: 901 tmp_jdr = hadc->Instance->JDR4; 902 break; 903 case ADC_INJECTED_RANK_3: 904 tmp_jdr = hadc->Instance->JDR3; 905 break; 906 case ADC_INJECTED_RANK_2: 907 tmp_jdr = hadc->Instance->JDR2; 908 break; 909 case ADC_INJECTED_RANK_1: 910 default: 911 tmp_jdr = hadc->Instance->JDR1; 912 break; 913 } 914 915 /* Return ADC converted value */ 916 return tmp_jdr; 917 } 918 919 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) 920 /** 921 * @brief Returns the last ADC Master&Slave regular conversions results data 922 * in the selected multi mode. 923 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) 924 * @retval The converted data value. 925 */ 926 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) 927 { 928 uint32_t tmpDR = 0U; 929 930 /* Check the parameters */ 931 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 932 933 /* Check the parameters */ 934 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 935 936 /* Note: EOC flag is not cleared here by software because automatically */ 937 /* cleared by hardware when reading register DR. */ 938 939 /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */ 940 /* only if ADC1 DMA mode is enabled. */ 941 tmpDR = hadc->Instance->DR; 942 943 if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) 944 { 945 tmpDR |= (ADC2->DR << 16U); 946 } 947 948 /* Return ADC converted value */ 949 return tmpDR; 950 } 951 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ 952 953 /** 954 * @brief Injected conversion complete callback in non blocking mode 955 * @param hadc: ADC handle 956 * @retval None 957 */ 958 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) 959 { 960 /* Prevent unused argument(s) compilation warning */ 961 UNUSED(hadc); 962 /* NOTE : This function Should not be modified, when the callback is needed, 963 the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file 964 */ 965 } 966 967 /** 968 * @} 969 */ 970 971 /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions 972 * @brief Extended Peripheral Control functions 973 * 974 @verbatim 975 =============================================================================== 976 ##### Peripheral Control functions ##### 977 =============================================================================== 978 [..] This section provides functions allowing to: 979 (+) Configure channels on injected group 980 (+) Configure multimode 981 982 @endverbatim 983 * @{ 984 */ 985 986 /** 987 * @brief Configures the ADC injected group and the selected channel to be 988 * linked to the injected group. 989 * @note Possibility to update parameters on the fly: 990 * This function initializes injected group, following calls to this 991 * function can be used to reconfigure some parameters of structure 992 * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. 993 * The setting of these parameters is conditioned to ADC state: 994 * this function must be called when ADC is not under conversion. 995 * @param hadc: ADC handle 996 * @param sConfigInjected: Structure of ADC injected group and ADC channel for 997 * injected group. 998 * @retval None 999 */ 1000 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) 1001 { 1002 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 1003 __IO uint32_t wait_loop_index = 0U; 1004 1005 /* Check the parameters */ 1006 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 1007 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); 1008 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); 1009 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); 1010 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); 1011 assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); 1012 1013 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 1014 { 1015 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); 1016 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); 1017 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); 1018 } 1019 1020 /* Process locked */ 1021 __HAL_LOCK(hadc); 1022 1023 /* Configuration of injected group sequencer: */ 1024 /* - if scan mode is disabled, injected channels sequence length is set to */ 1025 /* 0x00: 1 channel converted (channel on regular rank 1) */ 1026 /* Parameter "InjectedNbrOfConversion" is discarded. */ 1027 /* Note: Scan mode is present by hardware on this device and, if */ 1028 /* disabled, discards automatically nb of conversions. Anyway, nb of */ 1029 /* conversions is forced to 0x00 for alignment over all STM32 devices. */ 1030 /* - if scan mode is enabled, injected channels sequence length is set to */ 1031 /* parameter "InjectedNbrOfConversion". */ 1032 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) 1033 { 1034 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) 1035 { 1036 /* Clear the old SQx bits for all injected ranks */ 1037 MODIFY_REG(hadc->Instance->JSQR , 1038 ADC_JSQR_JL | 1039 ADC_JSQR_JSQ4 | 1040 ADC_JSQR_JSQ3 | 1041 ADC_JSQR_JSQ2 | 1042 ADC_JSQR_JSQ1 , 1043 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, 1044 ADC_INJECTED_RANK_1, 1045 0x01U)); 1046 } 1047 /* If another injected rank than rank1 was intended to be set, and could */ 1048 /* not due to ScanConvMode disabled, error is reported. */ 1049 else 1050 { 1051 /* Update ADC state machine to error */ 1052 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 1053 1054 tmp_hal_status = HAL_ERROR; 1055 } 1056 } 1057 else 1058 { 1059 /* Since injected channels rank conv. order depends on total number of */ 1060 /* injected conversions, selected rank must be below or equal to total */ 1061 /* number of injected conversions to be updated. */ 1062 if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) 1063 { 1064 /* Clear the old SQx bits for the selected rank */ 1065 /* Set the SQx bits for the selected rank */ 1066 MODIFY_REG(hadc->Instance->JSQR , 1067 1068 ADC_JSQR_JL | 1069 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, 1070 sConfigInjected->InjectedRank, 1071 sConfigInjected->InjectedNbrOfConversion) , 1072 1073 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | 1074 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, 1075 sConfigInjected->InjectedRank, 1076 sConfigInjected->InjectedNbrOfConversion) ); 1077 } 1078 else 1079 { 1080 /* Clear the old SQx bits for the selected rank */ 1081 MODIFY_REG(hadc->Instance->JSQR , 1082 1083 ADC_JSQR_JL | 1084 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, 1085 sConfigInjected->InjectedRank, 1086 sConfigInjected->InjectedNbrOfConversion) , 1087 1088 0x00000000U); 1089 } 1090 } 1091 1092 /* Configuration of injected group */ 1093 /* Parameters update conditioned to ADC state: */ 1094 /* Parameters that can be updated only when ADC is disabled: */ 1095 /* - external trigger to start conversion */ 1096 /* Parameters update not conditioned to ADC state: */ 1097 /* - Automatic injected conversion */ 1098 /* - Injected discontinuous mode */ 1099 /* Note: In case of ADC already enabled, caution to not launch an unwanted */ 1100 /* conversion while modifying register CR2 by writing 1 to bit ADON. */ 1101 if (ADC_IS_ENABLE(hadc) == RESET) 1102 { 1103 MODIFY_REG(hadc->Instance->CR2 , 1104 ADC_CR2_JEXTSEL | 1105 ADC_CR2_ADON , 1106 ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) ); 1107 } 1108 1109 1110 /* Configuration of injected group */ 1111 /* - Automatic injected conversion */ 1112 /* - Injected discontinuous mode */ 1113 1114 /* Automatic injected conversion can be enabled if injected group */ 1115 /* external triggers are disabled. */ 1116 if (sConfigInjected->AutoInjectedConv == ENABLE) 1117 { 1118 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) 1119 { 1120 SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); 1121 } 1122 else 1123 { 1124 /* Update ADC state machine to error */ 1125 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 1126 1127 tmp_hal_status = HAL_ERROR; 1128 } 1129 } 1130 1131 /* Injected discontinuous can be enabled only if auto-injected mode is */ 1132 /* disabled. */ 1133 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) 1134 { 1135 if (sConfigInjected->AutoInjectedConv == DISABLE) 1136 { 1137 SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); 1138 } 1139 else 1140 { 1141 /* Update ADC state machine to error */ 1142 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 1143 1144 tmp_hal_status = HAL_ERROR; 1145 } 1146 } 1147 1148 1149 /* InjectedChannel sampling time configuration */ 1150 /* For channels 10 to 17 */ 1151 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) 1152 { 1153 MODIFY_REG(hadc->Instance->SMPR1 , 1154 ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) , 1155 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); 1156 } 1157 else /* For channels 0 to 9 */ 1158 { 1159 MODIFY_REG(hadc->Instance->SMPR2 , 1160 ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) , 1161 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); 1162 } 1163 1164 /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */ 1165 /* and VREFINT measurement path. */ 1166 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || 1167 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) 1168 { 1169 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 1170 } 1171 1172 1173 /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ 1174 switch(sConfigInjected->InjectedRank) 1175 { 1176 case 1: 1177 /* Set injected channel 1 offset */ 1178 MODIFY_REG(hadc->Instance->JOFR1, 1179 ADC_JOFR1_JOFFSET1, 1180 sConfigInjected->InjectedOffset); 1181 break; 1182 case 2: 1183 /* Set injected channel 2 offset */ 1184 MODIFY_REG(hadc->Instance->JOFR2, 1185 ADC_JOFR2_JOFFSET2, 1186 sConfigInjected->InjectedOffset); 1187 break; 1188 case 3: 1189 /* Set injected channel 3 offset */ 1190 MODIFY_REG(hadc->Instance->JOFR3, 1191 ADC_JOFR3_JOFFSET3, 1192 sConfigInjected->InjectedOffset); 1193 break; 1194 case 4: 1195 default: 1196 MODIFY_REG(hadc->Instance->JOFR4, 1197 ADC_JOFR4_JOFFSET4, 1198 sConfigInjected->InjectedOffset); 1199 break; 1200 } 1201 1202 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ 1203 /* and VREFINT measurement path. */ 1204 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || 1205 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) 1206 { 1207 /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ 1208 /* measurement channels (VrefInt/TempSensor). If these channels are */ 1209 /* intended to be set on other ADC instances, an error is reported. */ 1210 if (hadc->Instance == ADC1) 1211 { 1212 if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) 1213 { 1214 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); 1215 1216 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) 1217 { 1218 /* Delay for temperature sensor stabilization time */ 1219 /* Compute number of CPU cycles to wait for */ 1220 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); 1221 while(wait_loop_index != 0U) 1222 { 1223 wait_loop_index--; 1224 } 1225 } 1226 } 1227 } 1228 else 1229 { 1230 /* Update ADC state machine to error */ 1231 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 1232 1233 tmp_hal_status = HAL_ERROR; 1234 } 1235 } 1236 1237 /* Process unlocked */ 1238 __HAL_UNLOCK(hadc); 1239 1240 /* Return function status */ 1241 return tmp_hal_status; 1242 } 1243 1244 #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) 1245 /** 1246 * @brief Enable ADC multimode and configure multimode parameters 1247 * @note Possibility to update parameters on the fly: 1248 * This function initializes multimode parameters, following 1249 * calls to this function can be used to reconfigure some parameters 1250 * of structure "ADC_MultiModeTypeDef" on the fly, without resetting 1251 * the ADCs (both ADCs of the common group). 1252 * The setting of these parameters is conditioned to ADC state. 1253 * For parameters constraints, see comments of structure 1254 * "ADC_MultiModeTypeDef". 1255 * @note To change back configuration from multimode to single mode, ADC must 1256 * be reset (using function HAL_ADC_Init() ). 1257 * @param hadc: ADC handle 1258 * @param multimode: Structure of ADC multimode configuration 1259 * @retval HAL status 1260 */ 1261 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) 1262 { 1263 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 1264 ADC_HandleTypeDef tmphadcSlave={0}; 1265 1266 /* Check the parameters */ 1267 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); 1268 assert_param(IS_ADC_MODE(multimode->Mode)); 1269 1270 /* Process locked */ 1271 __HAL_LOCK(hadc); 1272 1273 /* Set a temporary handle of the ADC slave associated to the ADC master */ 1274 ADC_MULTI_SLAVE(hadc, &tmphadcSlave); 1275 1276 /* Parameters update conditioned to ADC state: */ 1277 /* Parameters that can be updated when ADC is disabled or enabled without */ 1278 /* conversion on going on regular group: */ 1279 /* - ADC master and ADC slave DMA configuration */ 1280 /* Parameters that can be updated only when ADC is disabled: */ 1281 /* - Multimode mode selection */ 1282 /* To optimize code, all multimode settings can be set when both ADCs of */ 1283 /* the common group are in state: disabled. */ 1284 if ((ADC_IS_ENABLE(hadc) == RESET) && 1285 (ADC_IS_ENABLE(&tmphadcSlave) == RESET) && 1286 (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) ) 1287 { 1288 MODIFY_REG(hadc->Instance->CR1, 1289 ADC_CR1_DUALMOD , 1290 multimode->Mode ); 1291 } 1292 /* If one of the ADC sharing the same common group is enabled, no update */ 1293 /* could be done on neither of the multimode structure parameters. */ 1294 else 1295 { 1296 /* Update ADC state machine to error */ 1297 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 1298 1299 tmp_hal_status = HAL_ERROR; 1300 } 1301 1302 1303 /* Process unlocked */ 1304 __HAL_UNLOCK(hadc); 1305 1306 /* Return function status */ 1307 return tmp_hal_status; 1308 } 1309 #endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ 1310 /** 1311 * @} 1312 */ 1313 1314 /** 1315 * @} 1316 */ 1317 1318 #endif /* HAL_ADC_MODULE_ENABLED */ 1319 /** 1320 * @} 1321 */ 1322 1323 /** 1324 * @} 1325 */