Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h (83977B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F1xx_LL_RCC_H 20 #define __STM32F1xx_LL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f1xx.h" 28 29 /** @addtogroup STM32F1xx_LL_Driver 30 * @{ 31 */ 32 33 #if defined(RCC) 34 35 /** @defgroup RCC_LL RCC 36 * @{ 37 */ 38 39 /* Private types -------------------------------------------------------------*/ 40 /* Private variables ---------------------------------------------------------*/ 41 /* Private constants ---------------------------------------------------------*/ 42 /* Private macros ------------------------------------------------------------*/ 43 #if defined(USE_FULL_LL_DRIVER) 44 /** @defgroup RCC_LL_Private_Macros RCC Private Macros 45 * @{ 46 */ 47 /** 48 * @} 49 */ 50 #endif /*USE_FULL_LL_DRIVER*/ 51 /* Exported types ------------------------------------------------------------*/ 52 #if defined(USE_FULL_LL_DRIVER) 53 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 54 * @{ 55 */ 56 57 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 58 * @{ 59 */ 60 61 /** 62 * @brief RCC Clocks Frequency Structure 63 */ 64 typedef struct 65 { 66 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ 67 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ 68 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ 69 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ 70 } LL_RCC_ClocksTypeDef; 71 72 /** 73 * @} 74 */ 75 76 /** 77 * @} 78 */ 79 #endif /* USE_FULL_LL_DRIVER */ 80 81 /* Exported constants --------------------------------------------------------*/ 82 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 83 * @{ 84 */ 85 86 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 87 * @brief Defines used to adapt values of different oscillators 88 * @note These values could be modified in the user environment according to 89 * HW set-up. 90 * @{ 91 */ 92 #if !defined (HSE_VALUE) 93 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ 94 #endif /* HSE_VALUE */ 95 96 #if !defined (HSI_VALUE) 97 #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ 98 #endif /* HSI_VALUE */ 99 100 #if !defined (LSE_VALUE) 101 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ 102 #endif /* LSE_VALUE */ 103 104 #if !defined (LSI_VALUE) 105 #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ 106 #endif /* LSI_VALUE */ 107 /** 108 * @} 109 */ 110 111 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines 112 * @brief Flags defines which can be used with LL_RCC_WriteReg function 113 * @{ 114 */ 115 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ 116 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ 117 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ 118 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ 119 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ 120 #define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */ 121 #define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */ 122 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ 123 /** 124 * @} 125 */ 126 127 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines 128 * @brief Flags defines which can be used with LL_RCC_ReadReg function 129 * @{ 130 */ 131 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ 132 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ 133 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ 134 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ 135 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ 136 #define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */ 137 #define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 138 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ 139 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ 140 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ 141 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ 142 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 143 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 144 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ 145 /** 146 * @} 147 */ 148 149 /** @defgroup RCC_LL_EC_IT IT Defines 150 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions 151 * @{ 152 */ 153 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ 154 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ 155 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ 156 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ 157 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ 158 #define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */ 159 #define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */ 160 /** 161 * @} 162 */ 163 164 #if defined(RCC_CFGR2_PREDIV2) 165 /** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor 166 * @{ 167 */ 168 #define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ 169 #define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ 170 #define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ 171 #define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ 172 #define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ 173 #define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ 174 #define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ 175 #define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ 176 #define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ 177 #define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ 178 #define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ 179 #define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ 180 #define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ 181 #define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ 182 #define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ 183 #define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ 184 /** 185 * @} 186 */ 187 188 #endif /* RCC_CFGR2_PREDIV2 */ 189 190 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 191 * @{ 192 */ 193 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 194 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 195 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 196 /** 197 * @} 198 */ 199 200 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 201 * @{ 202 */ 203 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 204 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 205 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 206 /** 207 * @} 208 */ 209 210 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler 211 * @{ 212 */ 213 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 214 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 215 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 216 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 217 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 218 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 219 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 220 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 221 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 227 * @{ 228 */ 229 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 230 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 231 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 232 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 233 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) 239 * @{ 240 */ 241 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ 242 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ 243 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ 244 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ 245 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection 251 * @{ 252 */ 253 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK /*!< MCO output disabled, no clock on MCO */ 254 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK /*!< SYSCLK selection as MCO source */ 255 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI /*!< HSI selection as MCO source */ 256 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE /*!< HSE selection as MCO source */ 257 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!< PLL clock divided by 2*/ 258 #if defined(RCC_CFGR_MCO_PLL2CLK) 259 #define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCO_PLL2CLK /*!< PLL2 clock selected as MCO source*/ 260 #endif /* RCC_CFGR_MCO_PLL2CLK */ 261 #if defined(RCC_CFGR_MCO_PLL3CLK_DIV2) 262 #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/ 263 #endif /* RCC_CFGR_MCO_PLL3CLK_DIV2 */ 264 #if defined(RCC_CFGR_MCO_EXT_HSE) 265 #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCO_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ 266 #endif /* RCC_CFGR_MCO_EXT_HSE */ 267 #if defined(RCC_CFGR_MCO_PLL3CLK) 268 #define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCO_PLL3CLK /*!< PLLI2S clock selected as MCO source */ 269 #endif /* RCC_CFGR_MCO_PLL3CLK */ 270 /** 271 * @} 272 */ 273 274 #if defined(USE_FULL_LL_DRIVER) 275 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 276 * @{ 277 */ 278 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ 279 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 280 /** 281 * @} 282 */ 283 #endif /* USE_FULL_LL_DRIVER */ 284 285 #if defined(RCC_CFGR2_I2S2SRC) 286 /** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection 287 * @{ 288 */ 289 #define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */ 290 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */ 291 #define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */ 292 #define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */ 293 /** 294 * @} 295 */ 296 #endif /* RCC_CFGR2_I2S2SRC */ 297 298 #if defined(USB_OTG_FS) || defined(USB) 299 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 300 * @{ 301 */ 302 #if defined(RCC_CFGR_USBPRE) 303 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ 304 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */ 305 #endif /*RCC_CFGR_USBPRE*/ 306 #if defined(RCC_CFGR_OTGFSPRE) 307 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ 308 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */ 309 #endif /*RCC_CFGR_OTGFSPRE*/ 310 /** 311 * @} 312 */ 313 #endif /* USB_OTG_FS || USB */ 314 315 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection 316 * @{ 317 */ 318 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/ 319 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/ 320 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/ 321 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/ 322 /** 323 * @} 324 */ 325 326 #if defined(RCC_CFGR2_I2S2SRC) 327 /** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source 328 * @{ 329 */ 330 #define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */ 331 #define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */ 332 /** 333 * @} 334 */ 335 336 #endif /* RCC_CFGR2_I2S2SRC */ 337 338 #if defined(USB_OTG_FS) || defined(USB) 339 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 340 * @{ 341 */ 342 #define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */ 343 /** 344 * @} 345 */ 346 347 #endif /* USB_OTG_FS || USB */ 348 349 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source 350 * @{ 351 */ 352 #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 358 * @{ 359 */ 360 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 361 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 362 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 363 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ 364 /** 365 * @} 366 */ 367 368 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor 369 * @{ 370 */ 371 #if defined(RCC_CFGR_PLLMULL2) 372 #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */ 373 #endif /*RCC_CFGR_PLLMULL2*/ 374 #if defined(RCC_CFGR_PLLMULL3) 375 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */ 376 #endif /*RCC_CFGR_PLLMULL3*/ 377 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */ 378 #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */ 379 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */ 380 #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */ 381 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */ 382 #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */ 383 #if defined(RCC_CFGR_PLLMULL6_5) 384 #define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */ 385 #else 386 #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */ 387 #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */ 388 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */ 389 #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */ 390 #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */ 391 #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */ 392 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */ 393 #endif /*RCC_CFGR_PLLMULL6_5*/ 394 /** 395 * @} 396 */ 397 398 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE 399 * @{ 400 */ 401 #define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ 402 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */ 403 #if defined(RCC_CFGR2_PREDIV1SRC) 404 #define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */ 405 #endif /*RCC_CFGR2_PREDIV1SRC*/ 406 407 #if defined(RCC_CFGR2_PREDIV1) 408 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */ 409 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ 410 #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ 411 #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ 412 #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ 413 #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ 414 #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ 415 #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ 416 #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ 417 #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ 418 #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ 419 #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ 420 #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ 421 #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ 422 #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ 423 #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ 424 #if defined(RCC_CFGR2_PREDIV1SRC) 425 #define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */ 426 #define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */ 427 #define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */ 428 #define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */ 429 #define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */ 430 #define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */ 431 #define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */ 432 #define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */ 433 #define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */ 434 #define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */ 435 #define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */ 436 #define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */ 437 #define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */ 438 #define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */ 439 #define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */ 440 #define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */ 441 #endif /*RCC_CFGR2_PREDIV1SRC*/ 442 #else 443 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */ 444 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */ 445 #endif /*RCC_CFGR2_PREDIV1*/ 446 /** 447 * @} 448 */ 449 450 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor 451 * @{ 452 */ 453 #if defined(RCC_CFGR2_PREDIV1) 454 #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */ 455 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */ 456 #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */ 457 #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */ 458 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */ 459 #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */ 460 #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */ 461 #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */ 462 #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */ 463 #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */ 464 #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */ 465 #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */ 466 #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */ 467 #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */ 468 #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */ 469 #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */ 470 #else 471 #define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */ 472 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */ 473 #endif /*RCC_CFGR2_PREDIV1*/ 474 /** 475 * @} 476 */ 477 478 #if defined(RCC_PLLI2S_SUPPORT) 479 /** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL 480 * @{ 481 */ 482 #define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ 483 #define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ 484 #define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ 485 #define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ 486 #define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ 487 #define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ 488 #define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ 489 #define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ 490 #define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ 491 /** 492 * @} 493 */ 494 495 #endif /* RCC_PLLI2S_SUPPORT */ 496 497 #if defined(RCC_PLL2_SUPPORT) 498 /** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL 499 * @{ 500 */ 501 #define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ 502 #define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ 503 #define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ 504 #define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ 505 #define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ 506 #define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ 507 #define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ 508 #define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ 509 #define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ 510 /** 511 * @} 512 */ 513 514 #endif /* RCC_PLL2_SUPPORT */ 515 516 /** 517 * @} 518 */ 519 520 /* Exported macro ------------------------------------------------------------*/ 521 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 522 * @{ 523 */ 524 525 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 526 * @{ 527 */ 528 529 /** 530 * @brief Write a value in RCC register 531 * @param __REG__ Register to be written 532 * @param __VALUE__ Value to be written in the register 533 * @retval None 534 */ 535 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 536 537 /** 538 * @brief Read a value in RCC register 539 * @param __REG__ Register to be read 540 * @retval Register value 541 */ 542 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 543 /** 544 * @} 545 */ 546 547 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 548 * @{ 549 */ 550 551 #if defined(RCC_CFGR_PLLMULL6_5) 552 /** 553 * @brief Helper macro to calculate the PLLCLK frequency 554 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); 555 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1) 556 * @param __PLLMUL__: This parameter can be one of the following values: 557 * @arg @ref LL_RCC_PLL_MUL_4 558 * @arg @ref LL_RCC_PLL_MUL_5 559 * @arg @ref LL_RCC_PLL_MUL_6 560 * @arg @ref LL_RCC_PLL_MUL_7 561 * @arg @ref LL_RCC_PLL_MUL_8 562 * @arg @ref LL_RCC_PLL_MUL_9 563 * @arg @ref LL_RCC_PLL_MUL_6_5 564 * @retval PLL clock frequency (in Hz) 565 */ 566 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ 567 (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \ 568 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\ 569 (((__INPUTFREQ__) * 13U) / 2U)) 570 571 #else 572 /** 573 * @brief Helper macro to calculate the PLLCLK frequency 574 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ()); 575 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2) 576 * @param __PLLMUL__: This parameter can be one of the following values: 577 * @arg @ref LL_RCC_PLL_MUL_2 578 * @arg @ref LL_RCC_PLL_MUL_3 579 * @arg @ref LL_RCC_PLL_MUL_4 580 * @arg @ref LL_RCC_PLL_MUL_5 581 * @arg @ref LL_RCC_PLL_MUL_6 582 * @arg @ref LL_RCC_PLL_MUL_7 583 * @arg @ref LL_RCC_PLL_MUL_8 584 * @arg @ref LL_RCC_PLL_MUL_9 585 * @arg @ref LL_RCC_PLL_MUL_10 586 * @arg @ref LL_RCC_PLL_MUL_11 587 * @arg @ref LL_RCC_PLL_MUL_12 588 * @arg @ref LL_RCC_PLL_MUL_13 589 * @arg @ref LL_RCC_PLL_MUL_14 590 * @arg @ref LL_RCC_PLL_MUL_15 591 * @arg @ref LL_RCC_PLL_MUL_16 592 * @retval PLL clock frequency (in Hz) 593 */ 594 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U)) 595 #endif /* RCC_CFGR_PLLMULL6_5 */ 596 597 #if defined(RCC_PLLI2S_SUPPORT) 598 /** 599 * @brief Helper macro to calculate the PLLI2S frequency 600 * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); 601 * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value) 602 * @param __PLLI2SMUL__: This parameter can be one of the following values: 603 * @arg @ref LL_RCC_PLLI2S_MUL_8 604 * @arg @ref LL_RCC_PLLI2S_MUL_9 605 * @arg @ref LL_RCC_PLLI2S_MUL_10 606 * @arg @ref LL_RCC_PLLI2S_MUL_11 607 * @arg @ref LL_RCC_PLLI2S_MUL_12 608 * @arg @ref LL_RCC_PLLI2S_MUL_13 609 * @arg @ref LL_RCC_PLLI2S_MUL_14 610 * @arg @ref LL_RCC_PLLI2S_MUL_16 611 * @arg @ref LL_RCC_PLLI2S_MUL_20 612 * @param __PLLI2SDIV__: This parameter can be one of the following values: 613 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 614 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 615 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 616 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 617 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 618 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 619 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 620 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 621 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 622 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 623 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 624 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 625 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 626 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 627 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 628 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 629 * @retval PLLI2S clock frequency (in Hz) 630 */ 631 #define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) 632 #endif /* RCC_PLLI2S_SUPPORT */ 633 634 #if defined(RCC_PLL2_SUPPORT) 635 /** 636 * @brief Helper macro to calculate the PLL2 frequency 637 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); 638 * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value) 639 * @param __PLL2MUL__: This parameter can be one of the following values: 640 * @arg @ref LL_RCC_PLL2_MUL_8 641 * @arg @ref LL_RCC_PLL2_MUL_9 642 * @arg @ref LL_RCC_PLL2_MUL_10 643 * @arg @ref LL_RCC_PLL2_MUL_11 644 * @arg @ref LL_RCC_PLL2_MUL_12 645 * @arg @ref LL_RCC_PLL2_MUL_13 646 * @arg @ref LL_RCC_PLL2_MUL_14 647 * @arg @ref LL_RCC_PLL2_MUL_16 648 * @arg @ref LL_RCC_PLL2_MUL_20 649 * @param __PLL2DIV__: This parameter can be one of the following values: 650 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 651 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 652 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 653 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 654 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 655 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 656 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 657 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 658 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 659 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 660 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 661 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 662 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 663 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 664 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 665 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 666 * @retval PLL2 clock frequency (in Hz) 667 */ 668 #define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) 669 #endif /* RCC_PLL2_SUPPORT */ 670 671 /** 672 * @brief Helper macro to calculate the HCLK frequency 673 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler 674 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) 675 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) 676 * @param __AHBPRESCALER__: This parameter can be one of the following values: 677 * @arg @ref LL_RCC_SYSCLK_DIV_1 678 * @arg @ref LL_RCC_SYSCLK_DIV_2 679 * @arg @ref LL_RCC_SYSCLK_DIV_4 680 * @arg @ref LL_RCC_SYSCLK_DIV_8 681 * @arg @ref LL_RCC_SYSCLK_DIV_16 682 * @arg @ref LL_RCC_SYSCLK_DIV_64 683 * @arg @ref LL_RCC_SYSCLK_DIV_128 684 * @arg @ref LL_RCC_SYSCLK_DIV_256 685 * @arg @ref LL_RCC_SYSCLK_DIV_512 686 * @retval HCLK clock frequency (in Hz) 687 */ 688 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) 689 690 /** 691 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 692 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler 693 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) 694 * @param __HCLKFREQ__ HCLK frequency 695 * @param __APB1PRESCALER__: This parameter can be one of the following values: 696 * @arg @ref LL_RCC_APB1_DIV_1 697 * @arg @ref LL_RCC_APB1_DIV_2 698 * @arg @ref LL_RCC_APB1_DIV_4 699 * @arg @ref LL_RCC_APB1_DIV_8 700 * @arg @ref LL_RCC_APB1_DIV_16 701 * @retval PCLK1 clock frequency (in Hz) 702 */ 703 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) 704 705 /** 706 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 707 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler 708 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) 709 * @param __HCLKFREQ__ HCLK frequency 710 * @param __APB2PRESCALER__: This parameter can be one of the following values: 711 * @arg @ref LL_RCC_APB2_DIV_1 712 * @arg @ref LL_RCC_APB2_DIV_2 713 * @arg @ref LL_RCC_APB2_DIV_4 714 * @arg @ref LL_RCC_APB2_DIV_8 715 * @arg @ref LL_RCC_APB2_DIV_16 716 * @retval PCLK2 clock frequency (in Hz) 717 */ 718 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) 719 720 /** 721 * @} 722 */ 723 724 /** 725 * @} 726 */ 727 728 /* Exported functions --------------------------------------------------------*/ 729 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 730 * @{ 731 */ 732 733 /** @defgroup RCC_LL_EF_HSE HSE 734 * @{ 735 */ 736 737 /** 738 * @brief Enable the Clock Security System. 739 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS 740 * @retval None 741 */ 742 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 743 { 744 SET_BIT(RCC->CR, RCC_CR_CSSON); 745 } 746 747 /** 748 * @brief Enable HSE external oscillator (HSE Bypass) 749 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 750 * @retval None 751 */ 752 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 753 { 754 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 755 } 756 757 /** 758 * @brief Disable HSE external oscillator (HSE Bypass) 759 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 760 * @retval None 761 */ 762 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 763 { 764 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 765 } 766 767 /** 768 * @brief Enable HSE crystal oscillator (HSE ON) 769 * @rmtoll CR HSEON LL_RCC_HSE_Enable 770 * @retval None 771 */ 772 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 773 { 774 SET_BIT(RCC->CR, RCC_CR_HSEON); 775 } 776 777 /** 778 * @brief Disable HSE crystal oscillator (HSE ON) 779 * @rmtoll CR HSEON LL_RCC_HSE_Disable 780 * @retval None 781 */ 782 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 783 { 784 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 785 } 786 787 /** 788 * @brief Check if HSE oscillator Ready 789 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 790 * @retval State of bit (1 or 0). 791 */ 792 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 793 { 794 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); 795 } 796 797 #if defined(RCC_CFGR2_PREDIV2) 798 /** 799 * @brief Get PREDIV2 division factor 800 * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2 801 * @retval Returned value can be one of the following values: 802 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 803 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 804 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 805 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 806 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 807 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 808 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 809 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 810 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 811 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 812 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 813 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 814 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 815 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 816 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 817 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 818 */ 819 __STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void) 820 { 821 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); 822 } 823 #endif /* RCC_CFGR2_PREDIV2 */ 824 825 /** 826 * @} 827 */ 828 829 /** @defgroup RCC_LL_EF_HSI HSI 830 * @{ 831 */ 832 833 /** 834 * @brief Enable HSI oscillator 835 * @rmtoll CR HSION LL_RCC_HSI_Enable 836 * @retval None 837 */ 838 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 839 { 840 SET_BIT(RCC->CR, RCC_CR_HSION); 841 } 842 843 /** 844 * @brief Disable HSI oscillator 845 * @rmtoll CR HSION LL_RCC_HSI_Disable 846 * @retval None 847 */ 848 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 849 { 850 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 851 } 852 853 /** 854 * @brief Check if HSI clock is ready 855 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 856 * @retval State of bit (1 or 0). 857 */ 858 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 859 { 860 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); 861 } 862 863 /** 864 * @brief Get HSI Calibration value 865 * @note When HSITRIM is written, HSICAL is updated with the sum of 866 * HSITRIM and the factory trim value 867 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration 868 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF 869 */ 870 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 871 { 872 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); 873 } 874 875 /** 876 * @brief Set HSI Calibration trimming 877 * @note user-programmable trimming value that is added to the HSICAL 878 * @note Default value is 16, which, when added to the HSICAL value, 879 * should trim the HSI to 16 MHz +/- 1 % 880 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming 881 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F 882 * @retval None 883 */ 884 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 885 { 886 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); 887 } 888 889 /** 890 * @brief Get HSI Calibration trimming 891 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming 892 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F 893 */ 894 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 895 { 896 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); 897 } 898 899 /** 900 * @} 901 */ 902 903 /** @defgroup RCC_LL_EF_LSE LSE 904 * @{ 905 */ 906 907 /** 908 * @brief Enable Low Speed External (LSE) crystal. 909 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 910 * @retval None 911 */ 912 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 913 { 914 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 915 } 916 917 /** 918 * @brief Disable Low Speed External (LSE) crystal. 919 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 920 * @retval None 921 */ 922 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 923 { 924 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 925 } 926 927 /** 928 * @brief Enable external clock source (LSE bypass). 929 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 930 * @retval None 931 */ 932 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 933 { 934 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 935 } 936 937 /** 938 * @brief Disable external clock source (LSE bypass). 939 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 940 * @retval None 941 */ 942 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 943 { 944 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 945 } 946 947 /** 948 * @brief Check if LSE oscillator Ready 949 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 950 * @retval State of bit (1 or 0). 951 */ 952 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 953 { 954 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); 955 } 956 957 /** 958 * @} 959 */ 960 961 /** @defgroup RCC_LL_EF_LSI LSI 962 * @{ 963 */ 964 965 /** 966 * @brief Enable LSI Oscillator 967 * @rmtoll CSR LSION LL_RCC_LSI_Enable 968 * @retval None 969 */ 970 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 971 { 972 SET_BIT(RCC->CSR, RCC_CSR_LSION); 973 } 974 975 /** 976 * @brief Disable LSI Oscillator 977 * @rmtoll CSR LSION LL_RCC_LSI_Disable 978 * @retval None 979 */ 980 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 981 { 982 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 983 } 984 985 /** 986 * @brief Check if LSI is Ready 987 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady 988 * @retval State of bit (1 or 0). 989 */ 990 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 991 { 992 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); 993 } 994 995 /** 996 * @} 997 */ 998 999 /** @defgroup RCC_LL_EF_System System 1000 * @{ 1001 */ 1002 1003 /** 1004 * @brief Configure the system clock source 1005 * @rmtoll CFGR SW LL_RCC_SetSysClkSource 1006 * @param Source This parameter can be one of the following values: 1007 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 1008 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 1009 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL 1010 * @retval None 1011 */ 1012 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 1013 { 1014 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 1015 } 1016 1017 /** 1018 * @brief Get the system clock source 1019 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource 1020 * @retval Returned value can be one of the following values: 1021 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 1022 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 1023 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL 1024 */ 1025 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 1026 { 1027 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 1028 } 1029 1030 /** 1031 * @brief Set AHB prescaler 1032 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler 1033 * @param Prescaler This parameter can be one of the following values: 1034 * @arg @ref LL_RCC_SYSCLK_DIV_1 1035 * @arg @ref LL_RCC_SYSCLK_DIV_2 1036 * @arg @ref LL_RCC_SYSCLK_DIV_4 1037 * @arg @ref LL_RCC_SYSCLK_DIV_8 1038 * @arg @ref LL_RCC_SYSCLK_DIV_16 1039 * @arg @ref LL_RCC_SYSCLK_DIV_64 1040 * @arg @ref LL_RCC_SYSCLK_DIV_128 1041 * @arg @ref LL_RCC_SYSCLK_DIV_256 1042 * @arg @ref LL_RCC_SYSCLK_DIV_512 1043 * @retval None 1044 */ 1045 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 1046 { 1047 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 1048 } 1049 1050 /** 1051 * @brief Set APB1 prescaler 1052 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler 1053 * @param Prescaler This parameter can be one of the following values: 1054 * @arg @ref LL_RCC_APB1_DIV_1 1055 * @arg @ref LL_RCC_APB1_DIV_2 1056 * @arg @ref LL_RCC_APB1_DIV_4 1057 * @arg @ref LL_RCC_APB1_DIV_8 1058 * @arg @ref LL_RCC_APB1_DIV_16 1059 * @retval None 1060 */ 1061 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 1062 { 1063 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 1064 } 1065 1066 /** 1067 * @brief Set APB2 prescaler 1068 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler 1069 * @param Prescaler This parameter can be one of the following values: 1070 * @arg @ref LL_RCC_APB2_DIV_1 1071 * @arg @ref LL_RCC_APB2_DIV_2 1072 * @arg @ref LL_RCC_APB2_DIV_4 1073 * @arg @ref LL_RCC_APB2_DIV_8 1074 * @arg @ref LL_RCC_APB2_DIV_16 1075 * @retval None 1076 */ 1077 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 1078 { 1079 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 1080 } 1081 1082 /** 1083 * @brief Get AHB prescaler 1084 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler 1085 * @retval Returned value can be one of the following values: 1086 * @arg @ref LL_RCC_SYSCLK_DIV_1 1087 * @arg @ref LL_RCC_SYSCLK_DIV_2 1088 * @arg @ref LL_RCC_SYSCLK_DIV_4 1089 * @arg @ref LL_RCC_SYSCLK_DIV_8 1090 * @arg @ref LL_RCC_SYSCLK_DIV_16 1091 * @arg @ref LL_RCC_SYSCLK_DIV_64 1092 * @arg @ref LL_RCC_SYSCLK_DIV_128 1093 * @arg @ref LL_RCC_SYSCLK_DIV_256 1094 * @arg @ref LL_RCC_SYSCLK_DIV_512 1095 */ 1096 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 1097 { 1098 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 1099 } 1100 1101 /** 1102 * @brief Get APB1 prescaler 1103 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler 1104 * @retval Returned value can be one of the following values: 1105 * @arg @ref LL_RCC_APB1_DIV_1 1106 * @arg @ref LL_RCC_APB1_DIV_2 1107 * @arg @ref LL_RCC_APB1_DIV_4 1108 * @arg @ref LL_RCC_APB1_DIV_8 1109 * @arg @ref LL_RCC_APB1_DIV_16 1110 */ 1111 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 1112 { 1113 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 1114 } 1115 1116 /** 1117 * @brief Get APB2 prescaler 1118 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler 1119 * @retval Returned value can be one of the following values: 1120 * @arg @ref LL_RCC_APB2_DIV_1 1121 * @arg @ref LL_RCC_APB2_DIV_2 1122 * @arg @ref LL_RCC_APB2_DIV_4 1123 * @arg @ref LL_RCC_APB2_DIV_8 1124 * @arg @ref LL_RCC_APB2_DIV_16 1125 */ 1126 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 1127 { 1128 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 1129 } 1130 1131 /** 1132 * @} 1133 */ 1134 1135 /** @defgroup RCC_LL_EF_MCO MCO 1136 * @{ 1137 */ 1138 1139 /** 1140 * @brief Configure MCOx 1141 * @rmtoll CFGR MCO LL_RCC_ConfigMCO 1142 * @param MCOxSource This parameter can be one of the following values: 1143 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK 1144 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK 1145 * @arg @ref LL_RCC_MCO1SOURCE_HSI 1146 * @arg @ref LL_RCC_MCO1SOURCE_HSE 1147 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 1148 * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*) 1149 * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*) 1150 * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*) 1151 * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*) 1152 * 1153 * (*) value not defined in all devices 1154 * @retval None 1155 */ 1156 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource) 1157 { 1158 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); 1159 } 1160 1161 /** 1162 * @} 1163 */ 1164 1165 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 1166 * @{ 1167 */ 1168 1169 #if defined(RCC_CFGR2_I2S2SRC) 1170 /** 1171 * @brief Configure I2Sx clock source 1172 * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n 1173 * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource 1174 * @param I2SxSource This parameter can be one of the following values: 1175 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK 1176 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO 1177 * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK 1178 * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO 1179 * @retval None 1180 */ 1181 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) 1182 { 1183 MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); 1184 } 1185 #endif /* RCC_CFGR2_I2S2SRC */ 1186 1187 #if defined(USB_OTG_FS) || defined(USB) 1188 /** 1189 * @brief Configure USB clock source 1190 * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n 1191 * CFGR USBPRE LL_RCC_SetUSBClockSource 1192 * @param USBxSource This parameter can be one of the following values: 1193 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) 1194 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) 1195 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) 1196 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) 1197 * 1198 * (*) value not defined in all devices 1199 * @retval None 1200 */ 1201 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) 1202 { 1203 #if defined(RCC_CFGR_USBPRE) 1204 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); 1205 #else /*RCC_CFGR_OTGFSPRE*/ 1206 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource); 1207 #endif /*RCC_CFGR_USBPRE*/ 1208 } 1209 #endif /* USB_OTG_FS || USB */ 1210 1211 /** 1212 * @brief Configure ADC clock source 1213 * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource 1214 * @param ADCxSource This parameter can be one of the following values: 1215 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 1216 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 1217 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 1218 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 1219 * @retval None 1220 */ 1221 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) 1222 { 1223 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); 1224 } 1225 1226 #if defined(RCC_CFGR2_I2S2SRC) 1227 /** 1228 * @brief Get I2Sx clock source 1229 * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n 1230 * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource 1231 * @param I2Sx This parameter can be one of the following values: 1232 * @arg @ref LL_RCC_I2S2_CLKSOURCE 1233 * @arg @ref LL_RCC_I2S3_CLKSOURCE 1234 * @retval Returned value can be one of the following values: 1235 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK 1236 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO 1237 * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK 1238 * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO 1239 */ 1240 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) 1241 { 1242 return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); 1243 } 1244 #endif /* RCC_CFGR2_I2S2SRC */ 1245 1246 #if defined(USB_OTG_FS) || defined(USB) 1247 /** 1248 * @brief Get USBx clock source 1249 * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n 1250 * CFGR USBPRE LL_RCC_GetUSBClockSource 1251 * @param USBx This parameter can be one of the following values: 1252 * @arg @ref LL_RCC_USB_CLKSOURCE 1253 * @retval Returned value can be one of the following values: 1254 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) 1255 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) 1256 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) 1257 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) 1258 * 1259 * (*) value not defined in all devices 1260 */ 1261 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) 1262 { 1263 return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); 1264 } 1265 #endif /* USB_OTG_FS || USB */ 1266 1267 /** 1268 * @brief Get ADCx clock source 1269 * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource 1270 * @param ADCx This parameter can be one of the following values: 1271 * @arg @ref LL_RCC_ADC_CLKSOURCE 1272 * @retval Returned value can be one of the following values: 1273 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 1274 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 1275 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 1276 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 1277 */ 1278 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) 1279 { 1280 return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); 1281 } 1282 1283 /** 1284 * @} 1285 */ 1286 1287 /** @defgroup RCC_LL_EF_RTC RTC 1288 * @{ 1289 */ 1290 1291 /** 1292 * @brief Set RTC Clock Source 1293 * @note Once the RTC clock source has been selected, it cannot be changed any more unless 1294 * the Backup domain is reset. The BDRST bit can be used to reset them. 1295 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 1296 * @param Source This parameter can be one of the following values: 1297 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 1298 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 1299 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 1300 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 1301 * @retval None 1302 */ 1303 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 1304 { 1305 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 1306 } 1307 1308 /** 1309 * @brief Get RTC Clock Source 1310 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 1311 * @retval Returned value can be one of the following values: 1312 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 1313 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 1314 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 1315 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 1316 */ 1317 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 1318 { 1319 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 1320 } 1321 1322 /** 1323 * @brief Enable RTC 1324 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 1325 * @retval None 1326 */ 1327 __STATIC_INLINE void LL_RCC_EnableRTC(void) 1328 { 1329 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 1330 } 1331 1332 /** 1333 * @brief Disable RTC 1334 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 1335 * @retval None 1336 */ 1337 __STATIC_INLINE void LL_RCC_DisableRTC(void) 1338 { 1339 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 1340 } 1341 1342 /** 1343 * @brief Check if RTC has been enabled or not 1344 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 1345 * @retval State of bit (1 or 0). 1346 */ 1347 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 1348 { 1349 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); 1350 } 1351 1352 /** 1353 * @brief Force the Backup domain reset 1354 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset 1355 * @retval None 1356 */ 1357 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 1358 { 1359 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 1360 } 1361 1362 /** 1363 * @brief Release the Backup domain reset 1364 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset 1365 * @retval None 1366 */ 1367 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 1368 { 1369 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 1370 } 1371 1372 /** 1373 * @} 1374 */ 1375 1376 /** @defgroup RCC_LL_EF_PLL PLL 1377 * @{ 1378 */ 1379 1380 /** 1381 * @brief Enable PLL 1382 * @rmtoll CR PLLON LL_RCC_PLL_Enable 1383 * @retval None 1384 */ 1385 __STATIC_INLINE void LL_RCC_PLL_Enable(void) 1386 { 1387 SET_BIT(RCC->CR, RCC_CR_PLLON); 1388 } 1389 1390 /** 1391 * @brief Disable PLL 1392 * @note Cannot be disabled if the PLL clock is used as the system clock 1393 * @rmtoll CR PLLON LL_RCC_PLL_Disable 1394 * @retval None 1395 */ 1396 __STATIC_INLINE void LL_RCC_PLL_Disable(void) 1397 { 1398 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 1399 } 1400 1401 /** 1402 * @brief Check if PLL Ready 1403 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady 1404 * @retval State of bit (1 or 0). 1405 */ 1406 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) 1407 { 1408 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); 1409 } 1410 1411 /** 1412 * @brief Configure PLL used for SYSCLK Domain 1413 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n 1414 * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n 1415 * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n 1416 * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n 1417 * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS 1418 * @param Source This parameter can be one of the following values: 1419 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 1420 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 1421 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*) 1422 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*) 1423 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*) 1424 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*) 1425 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*) 1426 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*) 1427 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*) 1428 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*) 1429 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*) 1430 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*) 1431 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*) 1432 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*) 1433 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*) 1434 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*) 1435 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*) 1436 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*) 1437 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*) 1438 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*) 1439 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*) 1440 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*) 1441 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*) 1442 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*) 1443 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*) 1444 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*) 1445 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*) 1446 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*) 1447 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*) 1448 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*) 1449 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*) 1450 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*) 1451 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*) 1452 * 1453 * (*) value not defined in all devices 1454 * @param PLLMul This parameter can be one of the following values: 1455 * @arg @ref LL_RCC_PLL_MUL_2 (*) 1456 * @arg @ref LL_RCC_PLL_MUL_3 (*) 1457 * @arg @ref LL_RCC_PLL_MUL_4 1458 * @arg @ref LL_RCC_PLL_MUL_5 1459 * @arg @ref LL_RCC_PLL_MUL_6 1460 * @arg @ref LL_RCC_PLL_MUL_7 1461 * @arg @ref LL_RCC_PLL_MUL_8 1462 * @arg @ref LL_RCC_PLL_MUL_9 1463 * @arg @ref LL_RCC_PLL_MUL_6_5 (*) 1464 * @arg @ref LL_RCC_PLL_MUL_10 (*) 1465 * @arg @ref LL_RCC_PLL_MUL_11 (*) 1466 * @arg @ref LL_RCC_PLL_MUL_12 (*) 1467 * @arg @ref LL_RCC_PLL_MUL_13 (*) 1468 * @arg @ref LL_RCC_PLL_MUL_14 (*) 1469 * @arg @ref LL_RCC_PLL_MUL_15 (*) 1470 * @arg @ref LL_RCC_PLL_MUL_16 (*) 1471 * 1472 * (*) value not defined in all devices 1473 * @retval None 1474 */ 1475 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) 1476 { 1477 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL, 1478 (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul); 1479 #if defined(RCC_CFGR2_PREDIV1) 1480 #if defined(RCC_CFGR2_PREDIV1SRC) 1481 MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), 1482 (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); 1483 #else 1484 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); 1485 #endif /*RCC_CFGR2_PREDIV1SRC*/ 1486 #endif /*RCC_CFGR2_PREDIV1*/ 1487 } 1488 1489 /** 1490 * @brief Configure PLL clock source 1491 * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n 1492 * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource 1493 * @param PLLSource This parameter can be one of the following values: 1494 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 1495 * @arg @ref LL_RCC_PLLSOURCE_HSE 1496 * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) 1497 * @retval None 1498 */ 1499 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) 1500 { 1501 #if defined(RCC_CFGR2_PREDIV1SRC) 1502 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); 1503 #endif /* RCC_CFGR2_PREDIV1SRC */ 1504 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); 1505 } 1506 1507 /** 1508 * @brief Get the oscillator used as PLL clock source. 1509 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n 1510 * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource 1511 * @retval Returned value can be one of the following values: 1512 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 1513 * @arg @ref LL_RCC_PLLSOURCE_HSE 1514 * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) 1515 * 1516 * (*) value not defined in all devices 1517 */ 1518 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) 1519 { 1520 #if defined(RCC_CFGR2_PREDIV1SRC) 1521 uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); 1522 uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); 1523 return (uint32_t)(pllsrc | predivsrc); 1524 #else 1525 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); 1526 #endif /*RCC_CFGR2_PREDIV1SRC*/ 1527 } 1528 1529 /** 1530 * @brief Get PLL multiplication Factor 1531 * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator 1532 * @retval Returned value can be one of the following values: 1533 * @arg @ref LL_RCC_PLL_MUL_2 (*) 1534 * @arg @ref LL_RCC_PLL_MUL_3 (*) 1535 * @arg @ref LL_RCC_PLL_MUL_4 1536 * @arg @ref LL_RCC_PLL_MUL_5 1537 * @arg @ref LL_RCC_PLL_MUL_6 1538 * @arg @ref LL_RCC_PLL_MUL_7 1539 * @arg @ref LL_RCC_PLL_MUL_8 1540 * @arg @ref LL_RCC_PLL_MUL_9 1541 * @arg @ref LL_RCC_PLL_MUL_6_5 (*) 1542 * @arg @ref LL_RCC_PLL_MUL_10 (*) 1543 * @arg @ref LL_RCC_PLL_MUL_11 (*) 1544 * @arg @ref LL_RCC_PLL_MUL_12 (*) 1545 * @arg @ref LL_RCC_PLL_MUL_13 (*) 1546 * @arg @ref LL_RCC_PLL_MUL_14 (*) 1547 * @arg @ref LL_RCC_PLL_MUL_15 (*) 1548 * @arg @ref LL_RCC_PLL_MUL_16 (*) 1549 * 1550 * (*) value not defined in all devices 1551 */ 1552 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) 1553 { 1554 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL)); 1555 } 1556 1557 /** 1558 * @brief Get PREDIV1 division factor for the main PLL 1559 * @note They can be written only when the PLL is disabled 1560 * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n 1561 * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv 1562 * @retval Returned value can be one of the following values: 1563 * @arg @ref LL_RCC_PREDIV_DIV_1 1564 * @arg @ref LL_RCC_PREDIV_DIV_2 1565 * @arg @ref LL_RCC_PREDIV_DIV_3 (*) 1566 * @arg @ref LL_RCC_PREDIV_DIV_4 (*) 1567 * @arg @ref LL_RCC_PREDIV_DIV_5 (*) 1568 * @arg @ref LL_RCC_PREDIV_DIV_6 (*) 1569 * @arg @ref LL_RCC_PREDIV_DIV_7 (*) 1570 * @arg @ref LL_RCC_PREDIV_DIV_8 (*) 1571 * @arg @ref LL_RCC_PREDIV_DIV_9 (*) 1572 * @arg @ref LL_RCC_PREDIV_DIV_10 (*) 1573 * @arg @ref LL_RCC_PREDIV_DIV_11 (*) 1574 * @arg @ref LL_RCC_PREDIV_DIV_12 (*) 1575 * @arg @ref LL_RCC_PREDIV_DIV_13 (*) 1576 * @arg @ref LL_RCC_PREDIV_DIV_14 (*) 1577 * @arg @ref LL_RCC_PREDIV_DIV_15 (*) 1578 * @arg @ref LL_RCC_PREDIV_DIV_16 (*) 1579 * 1580 * (*) value not defined in all devices 1581 */ 1582 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) 1583 { 1584 #if defined(RCC_CFGR2_PREDIV1) 1585 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); 1586 #else 1587 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos); 1588 #endif /*RCC_CFGR2_PREDIV1*/ 1589 } 1590 1591 /** 1592 * @} 1593 */ 1594 1595 #if defined(RCC_PLLI2S_SUPPORT) 1596 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S 1597 * @{ 1598 */ 1599 1600 /** 1601 * @brief Enable PLLI2S 1602 * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable 1603 * @retval None 1604 */ 1605 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) 1606 { 1607 SET_BIT(RCC->CR, RCC_CR_PLL3ON); 1608 } 1609 1610 /** 1611 * @brief Disable PLLI2S 1612 * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable 1613 * @retval None 1614 */ 1615 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) 1616 { 1617 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 1618 } 1619 1620 /** 1621 * @brief Check if PLLI2S Ready 1622 * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady 1623 * @retval State of bit (1 or 0). 1624 */ 1625 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) 1626 { 1627 return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)); 1628 } 1629 1630 /** 1631 * @brief Configure PLLI2S used for I2S Domain 1632 * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n 1633 * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S 1634 * @param Divider This parameter can be one of the following values: 1635 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 1636 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 1637 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 1638 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 1639 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 1640 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 1641 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 1642 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 1643 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 1644 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 1645 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 1646 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 1647 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 1648 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 1649 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 1650 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 1651 * @param Multiplicator This parameter can be one of the following values: 1652 * @arg @ref LL_RCC_PLLI2S_MUL_8 1653 * @arg @ref LL_RCC_PLLI2S_MUL_9 1654 * @arg @ref LL_RCC_PLLI2S_MUL_10 1655 * @arg @ref LL_RCC_PLLI2S_MUL_11 1656 * @arg @ref LL_RCC_PLLI2S_MUL_12 1657 * @arg @ref LL_RCC_PLLI2S_MUL_13 1658 * @arg @ref LL_RCC_PLLI2S_MUL_14 1659 * @arg @ref LL_RCC_PLLI2S_MUL_16 1660 * @arg @ref LL_RCC_PLLI2S_MUL_20 1661 * @retval None 1662 */ 1663 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator) 1664 { 1665 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); 1666 } 1667 1668 /** 1669 * @brief Get PLLI2S Multiplication Factor 1670 * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator 1671 * @retval Returned value can be one of the following values: 1672 * @arg @ref LL_RCC_PLLI2S_MUL_8 1673 * @arg @ref LL_RCC_PLLI2S_MUL_9 1674 * @arg @ref LL_RCC_PLLI2S_MUL_10 1675 * @arg @ref LL_RCC_PLLI2S_MUL_11 1676 * @arg @ref LL_RCC_PLLI2S_MUL_12 1677 * @arg @ref LL_RCC_PLLI2S_MUL_13 1678 * @arg @ref LL_RCC_PLLI2S_MUL_14 1679 * @arg @ref LL_RCC_PLLI2S_MUL_16 1680 * @arg @ref LL_RCC_PLLI2S_MUL_20 1681 */ 1682 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void) 1683 { 1684 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); 1685 } 1686 1687 /** 1688 * @} 1689 */ 1690 #endif /* RCC_PLLI2S_SUPPORT */ 1691 1692 #if defined(RCC_PLL2_SUPPORT) 1693 /** @defgroup RCC_LL_EF_PLL2 PLL2 1694 * @{ 1695 */ 1696 1697 /** 1698 * @brief Enable PLL2 1699 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable 1700 * @retval None 1701 */ 1702 __STATIC_INLINE void LL_RCC_PLL2_Enable(void) 1703 { 1704 SET_BIT(RCC->CR, RCC_CR_PLL2ON); 1705 } 1706 1707 /** 1708 * @brief Disable PLL2 1709 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable 1710 * @retval None 1711 */ 1712 __STATIC_INLINE void LL_RCC_PLL2_Disable(void) 1713 { 1714 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 1715 } 1716 1717 /** 1718 * @brief Check if PLL2 Ready 1719 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady 1720 * @retval State of bit (1 or 0). 1721 */ 1722 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) 1723 { 1724 return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)); 1725 } 1726 1727 /** 1728 * @brief Configure PLL2 used for PLL2 Domain 1729 * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n 1730 * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2 1731 * @param Divider This parameter can be one of the following values: 1732 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 1733 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 1734 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 1735 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 1736 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 1737 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 1738 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 1739 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 1740 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 1741 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 1742 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 1743 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 1744 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 1745 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 1746 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 1747 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 1748 * @param Multiplicator This parameter can be one of the following values: 1749 * @arg @ref LL_RCC_PLL2_MUL_8 1750 * @arg @ref LL_RCC_PLL2_MUL_9 1751 * @arg @ref LL_RCC_PLL2_MUL_10 1752 * @arg @ref LL_RCC_PLL2_MUL_11 1753 * @arg @ref LL_RCC_PLL2_MUL_12 1754 * @arg @ref LL_RCC_PLL2_MUL_13 1755 * @arg @ref LL_RCC_PLL2_MUL_14 1756 * @arg @ref LL_RCC_PLL2_MUL_16 1757 * @arg @ref LL_RCC_PLL2_MUL_20 1758 * @retval None 1759 */ 1760 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator) 1761 { 1762 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator); 1763 } 1764 1765 /** 1766 * @brief Get PLL2 Multiplication Factor 1767 * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator 1768 * @retval Returned value can be one of the following values: 1769 * @arg @ref LL_RCC_PLL2_MUL_8 1770 * @arg @ref LL_RCC_PLL2_MUL_9 1771 * @arg @ref LL_RCC_PLL2_MUL_10 1772 * @arg @ref LL_RCC_PLL2_MUL_11 1773 * @arg @ref LL_RCC_PLL2_MUL_12 1774 * @arg @ref LL_RCC_PLL2_MUL_13 1775 * @arg @ref LL_RCC_PLL2_MUL_14 1776 * @arg @ref LL_RCC_PLL2_MUL_16 1777 * @arg @ref LL_RCC_PLL2_MUL_20 1778 */ 1779 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void) 1780 { 1781 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL)); 1782 } 1783 1784 /** 1785 * @} 1786 */ 1787 #endif /* RCC_PLL2_SUPPORT */ 1788 1789 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 1790 * @{ 1791 */ 1792 1793 /** 1794 * @brief Clear LSI ready interrupt flag 1795 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY 1796 * @retval None 1797 */ 1798 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 1799 { 1800 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); 1801 } 1802 1803 /** 1804 * @brief Clear LSE ready interrupt flag 1805 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY 1806 * @retval None 1807 */ 1808 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 1809 { 1810 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); 1811 } 1812 1813 /** 1814 * @brief Clear HSI ready interrupt flag 1815 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY 1816 * @retval None 1817 */ 1818 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 1819 { 1820 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); 1821 } 1822 1823 /** 1824 * @brief Clear HSE ready interrupt flag 1825 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY 1826 * @retval None 1827 */ 1828 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 1829 { 1830 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); 1831 } 1832 1833 /** 1834 * @brief Clear PLL ready interrupt flag 1835 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY 1836 * @retval None 1837 */ 1838 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) 1839 { 1840 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); 1841 } 1842 1843 #if defined(RCC_PLLI2S_SUPPORT) 1844 /** 1845 * @brief Clear PLLI2S ready interrupt flag 1846 * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY 1847 * @retval None 1848 */ 1849 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) 1850 { 1851 SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC); 1852 } 1853 #endif /* RCC_PLLI2S_SUPPORT */ 1854 1855 #if defined(RCC_PLL2_SUPPORT) 1856 /** 1857 * @brief Clear PLL2 ready interrupt flag 1858 * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY 1859 * @retval None 1860 */ 1861 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) 1862 { 1863 SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC); 1864 } 1865 #endif /* RCC_PLL2_SUPPORT */ 1866 1867 /** 1868 * @brief Clear Clock security system interrupt flag 1869 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS 1870 * @retval None 1871 */ 1872 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 1873 { 1874 SET_BIT(RCC->CIR, RCC_CIR_CSSC); 1875 } 1876 1877 /** 1878 * @brief Check if LSI ready interrupt occurred or not 1879 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 1880 * @retval State of bit (1 or 0). 1881 */ 1882 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 1883 { 1884 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); 1885 } 1886 1887 /** 1888 * @brief Check if LSE ready interrupt occurred or not 1889 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY 1890 * @retval State of bit (1 or 0). 1891 */ 1892 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 1893 { 1894 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); 1895 } 1896 1897 /** 1898 * @brief Check if HSI ready interrupt occurred or not 1899 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 1900 * @retval State of bit (1 or 0). 1901 */ 1902 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 1903 { 1904 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); 1905 } 1906 1907 /** 1908 * @brief Check if HSE ready interrupt occurred or not 1909 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY 1910 * @retval State of bit (1 or 0). 1911 */ 1912 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 1913 { 1914 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); 1915 } 1916 1917 /** 1918 * @brief Check if PLL ready interrupt occurred or not 1919 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY 1920 * @retval State of bit (1 or 0). 1921 */ 1922 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) 1923 { 1924 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); 1925 } 1926 1927 #if defined(RCC_PLLI2S_SUPPORT) 1928 /** 1929 * @brief Check if PLLI2S ready interrupt occurred or not 1930 * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY 1931 * @retval State of bit (1 or 0). 1932 */ 1933 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) 1934 { 1935 return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF)); 1936 } 1937 #endif /* RCC_PLLI2S_SUPPORT */ 1938 1939 #if defined(RCC_PLL2_SUPPORT) 1940 /** 1941 * @brief Check if PLL2 ready interrupt occurred or not 1942 * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY 1943 * @retval State of bit (1 or 0). 1944 */ 1945 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) 1946 { 1947 return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF)); 1948 } 1949 #endif /* RCC_PLL2_SUPPORT */ 1950 1951 /** 1952 * @brief Check if Clock security system interrupt occurred or not 1953 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS 1954 * @retval State of bit (1 or 0). 1955 */ 1956 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 1957 { 1958 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); 1959 } 1960 1961 /** 1962 * @brief Check if RCC flag Independent Watchdog reset is set or not. 1963 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST 1964 * @retval State of bit (1 or 0). 1965 */ 1966 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) 1967 { 1968 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); 1969 } 1970 1971 /** 1972 * @brief Check if RCC flag Low Power reset is set or not. 1973 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST 1974 * @retval State of bit (1 or 0). 1975 */ 1976 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 1977 { 1978 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); 1979 } 1980 1981 /** 1982 * @brief Check if RCC flag Pin reset is set or not. 1983 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST 1984 * @retval State of bit (1 or 0). 1985 */ 1986 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 1987 { 1988 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); 1989 } 1990 1991 /** 1992 * @brief Check if RCC flag POR/PDR reset is set or not. 1993 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST 1994 * @retval State of bit (1 or 0). 1995 */ 1996 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) 1997 { 1998 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); 1999 } 2000 2001 /** 2002 * @brief Check if RCC flag Software reset is set or not. 2003 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST 2004 * @retval State of bit (1 or 0). 2005 */ 2006 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 2007 { 2008 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); 2009 } 2010 2011 /** 2012 * @brief Check if RCC flag Window Watchdog reset is set or not. 2013 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST 2014 * @retval State of bit (1 or 0). 2015 */ 2016 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) 2017 { 2018 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); 2019 } 2020 2021 /** 2022 * @brief Set RMVF bit to clear the reset flags. 2023 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags 2024 * @retval None 2025 */ 2026 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 2027 { 2028 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 2029 } 2030 2031 /** 2032 * @} 2033 */ 2034 2035 /** @defgroup RCC_LL_EF_IT_Management IT Management 2036 * @{ 2037 */ 2038 2039 /** 2040 * @brief Enable LSI ready interrupt 2041 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY 2042 * @retval None 2043 */ 2044 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 2045 { 2046 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); 2047 } 2048 2049 /** 2050 * @brief Enable LSE ready interrupt 2051 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY 2052 * @retval None 2053 */ 2054 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 2055 { 2056 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); 2057 } 2058 2059 /** 2060 * @brief Enable HSI ready interrupt 2061 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY 2062 * @retval None 2063 */ 2064 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 2065 { 2066 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); 2067 } 2068 2069 /** 2070 * @brief Enable HSE ready interrupt 2071 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY 2072 * @retval None 2073 */ 2074 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 2075 { 2076 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); 2077 } 2078 2079 /** 2080 * @brief Enable PLL ready interrupt 2081 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY 2082 * @retval None 2083 */ 2084 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) 2085 { 2086 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); 2087 } 2088 2089 #if defined(RCC_PLLI2S_SUPPORT) 2090 /** 2091 * @brief Enable PLLI2S ready interrupt 2092 * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY 2093 * @retval None 2094 */ 2095 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) 2096 { 2097 SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); 2098 } 2099 #endif /* RCC_PLLI2S_SUPPORT */ 2100 2101 #if defined(RCC_PLL2_SUPPORT) 2102 /** 2103 * @brief Enable PLL2 ready interrupt 2104 * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY 2105 * @retval None 2106 */ 2107 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) 2108 { 2109 SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); 2110 } 2111 #endif /* RCC_PLL2_SUPPORT */ 2112 2113 /** 2114 * @brief Disable LSI ready interrupt 2115 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY 2116 * @retval None 2117 */ 2118 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 2119 { 2120 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); 2121 } 2122 2123 /** 2124 * @brief Disable LSE ready interrupt 2125 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY 2126 * @retval None 2127 */ 2128 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 2129 { 2130 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); 2131 } 2132 2133 /** 2134 * @brief Disable HSI ready interrupt 2135 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY 2136 * @retval None 2137 */ 2138 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 2139 { 2140 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); 2141 } 2142 2143 /** 2144 * @brief Disable HSE ready interrupt 2145 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY 2146 * @retval None 2147 */ 2148 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 2149 { 2150 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); 2151 } 2152 2153 /** 2154 * @brief Disable PLL ready interrupt 2155 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY 2156 * @retval None 2157 */ 2158 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) 2159 { 2160 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); 2161 } 2162 2163 #if defined(RCC_PLLI2S_SUPPORT) 2164 /** 2165 * @brief Disable PLLI2S ready interrupt 2166 * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY 2167 * @retval None 2168 */ 2169 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) 2170 { 2171 CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); 2172 } 2173 #endif /* RCC_PLLI2S_SUPPORT */ 2174 2175 #if defined(RCC_PLL2_SUPPORT) 2176 /** 2177 * @brief Disable PLL2 ready interrupt 2178 * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY 2179 * @retval None 2180 */ 2181 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) 2182 { 2183 CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); 2184 } 2185 #endif /* RCC_PLL2_SUPPORT */ 2186 2187 /** 2188 * @brief Checks if LSI ready interrupt source is enabled or disabled. 2189 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY 2190 * @retval State of bit (1 or 0). 2191 */ 2192 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) 2193 { 2194 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); 2195 } 2196 2197 /** 2198 * @brief Checks if LSE ready interrupt source is enabled or disabled. 2199 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY 2200 * @retval State of bit (1 or 0). 2201 */ 2202 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) 2203 { 2204 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); 2205 } 2206 2207 /** 2208 * @brief Checks if HSI ready interrupt source is enabled or disabled. 2209 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY 2210 * @retval State of bit (1 or 0). 2211 */ 2212 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) 2213 { 2214 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); 2215 } 2216 2217 /** 2218 * @brief Checks if HSE ready interrupt source is enabled or disabled. 2219 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY 2220 * @retval State of bit (1 or 0). 2221 */ 2222 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) 2223 { 2224 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); 2225 } 2226 2227 /** 2228 * @brief Checks if PLL ready interrupt source is enabled or disabled. 2229 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY 2230 * @retval State of bit (1 or 0). 2231 */ 2232 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) 2233 { 2234 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); 2235 } 2236 2237 #if defined(RCC_PLLI2S_SUPPORT) 2238 /** 2239 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. 2240 * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY 2241 * @retval State of bit (1 or 0). 2242 */ 2243 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) 2244 { 2245 return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE)); 2246 } 2247 #endif /* RCC_PLLI2S_SUPPORT */ 2248 2249 #if defined(RCC_PLL2_SUPPORT) 2250 /** 2251 * @brief Checks if PLL2 ready interrupt source is enabled or disabled. 2252 * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY 2253 * @retval State of bit (1 or 0). 2254 */ 2255 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) 2256 { 2257 return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE)); 2258 } 2259 #endif /* RCC_PLL2_SUPPORT */ 2260 2261 /** 2262 * @} 2263 */ 2264 2265 #if defined(USE_FULL_LL_DRIVER) 2266 /** @defgroup RCC_LL_EF_Init De-initialization function 2267 * @{ 2268 */ 2269 ErrorStatus LL_RCC_DeInit(void); 2270 /** 2271 * @} 2272 */ 2273 2274 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 2275 * @{ 2276 */ 2277 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 2278 #if defined(RCC_CFGR2_I2S2SRC) 2279 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); 2280 #endif /* RCC_CFGR2_I2S2SRC */ 2281 #if defined(USB_OTG_FS) || defined(USB) 2282 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 2283 #endif /* USB_OTG_FS || USB */ 2284 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); 2285 /** 2286 * @} 2287 */ 2288 #endif /* USE_FULL_LL_DRIVER */ 2289 2290 /** 2291 * @} 2292 */ 2293 2294 /** 2295 * @} 2296 */ 2297 2298 #endif /* RCC */ 2299 2300 /** 2301 * @} 2302 */ 2303 2304 #ifdef __cplusplus 2305 } 2306 #endif 2307 2308 #endif /* __STM32F1xx_LL_RCC_H */ 2309