Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h (228411B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F1xx_LL_ADC_H 21 #define __STM32F1xx_LL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f1xx.h" 29 30 /** @addtogroup STM32F1xx_LL_Driver 31 * @{ 32 */ 33 34 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 35 36 /** @defgroup ADC_LL ADC 37 * @{ 38 */ 39 40 /* Private types -------------------------------------------------------------*/ 41 /* Private variables ---------------------------------------------------------*/ 42 43 /* Private constants ---------------------------------------------------------*/ 44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants 45 * @{ 46 */ 47 48 /* Internal mask for ADC group regular sequencer: */ 49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ 50 /* - sequencer register offset */ 51 /* - sequencer rank bits position into the selected register */ 52 53 /* Internal register offset for ADC group regular sequencer configuration */ 54 /* (offset placed into a spare area of literal definition) */ 55 #define ADC_SQR1_REGOFFSET 0x00000000U 56 #define ADC_SQR2_REGOFFSET 0x00000100U 57 #define ADC_SQR3_REGOFFSET 0x00000200U 58 #define ADC_SQR4_REGOFFSET 0x00000300U 59 60 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) 61 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 62 63 /* Definition of ADC group regular sequencer bits information to be inserted */ 64 /* into ADC group regular sequencer ranks literals definition. */ 65 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ 66 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ 67 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ 68 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ 69 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ 70 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ 71 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ 72 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ 73 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ 74 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ 75 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ 76 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ 77 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ 78 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ 79 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ 80 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ 81 82 /* Internal mask for ADC group injected sequencer: */ 83 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ 84 /* - data register offset */ 85 /* - offset register offset */ 86 /* - sequencer rank bits position into the selected register */ 87 88 /* Internal register offset for ADC group injected data register */ 89 /* (offset placed into a spare area of literal definition) */ 90 #define ADC_JDR1_REGOFFSET 0x00000000U 91 #define ADC_JDR2_REGOFFSET 0x00000100U 92 #define ADC_JDR3_REGOFFSET 0x00000200U 93 #define ADC_JDR4_REGOFFSET 0x00000300U 94 95 /* Internal register offset for ADC group injected offset configuration */ 96 /* (offset placed into a spare area of literal definition) */ 97 #define ADC_JOFR1_REGOFFSET 0x00000000U 98 #define ADC_JOFR2_REGOFFSET 0x00001000U 99 #define ADC_JOFR3_REGOFFSET 0x00002000U 100 #define ADC_JOFR4_REGOFFSET 0x00003000U 101 102 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) 103 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) 104 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) 105 106 /* Internal mask for ADC channel: */ 107 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ 108 /* - channel identifier defined by number */ 109 /* - channel differentiation between external channels (connected to */ 110 /* GPIO pins) and internal channels (connected to internal paths) */ 111 /* - channel sampling time defined by SMPRx register offset */ 112 /* and SMPx bits positions into SMPRx register */ 113 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) 114 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ 115 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) 116 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ 117 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ 118 119 /* Channel differentiation between external and internal channels */ 120 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ 121 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ 122 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) 123 124 /* Internal register offset for ADC channel sampling time configuration */ 125 /* (offset placed into a spare area of literal definition) */ 126 #define ADC_SMPR1_REGOFFSET 0x00000000U 127 #define ADC_SMPR2_REGOFFSET 0x02000000U 128 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) 129 130 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U 131 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ 132 133 /* Definition of channels ID number information to be inserted into */ 134 /* channels literals definition. */ 135 #define ADC_CHANNEL_0_NUMBER 0x00000000U 136 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) 137 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) 138 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 139 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) 140 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 141 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 142 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 143 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) 144 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) 145 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) 146 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 147 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) 148 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) 149 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) 150 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) 151 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) 152 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) 153 154 /* Definition of channels sampling time information to be inserted into */ 155 /* channels literals definition. */ 156 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ 157 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ 158 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ 159 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ 160 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ 161 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ 162 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ 163 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ 164 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ 165 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ 166 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ 167 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ 168 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ 169 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ 170 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ 171 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ 172 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ 173 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ 174 175 /* Internal mask for ADC analog watchdog: */ 176 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ 177 /* (concatenation of multiple bits used in different analog watchdogs, */ 178 /* (feature of several watchdogs not available on all STM32 families)). */ 179 /* - analog watchdog 1: monitored channel defined by number, */ 180 /* selection of ADC group (ADC groups regular and-or injected). */ 181 182 /* Internal register offset for ADC analog watchdog channel configuration */ 183 #define ADC_AWD_CR1_REGOFFSET 0x00000000U 184 185 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) 186 187 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) 188 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) 189 190 /* Internal register offset for ADC analog watchdog threshold configuration */ 191 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U 192 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U 193 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) 194 195 /* ADC registers bits positions */ 196 #define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */ 197 198 /** 199 * @} 200 */ 201 202 203 /* Private macros ------------------------------------------------------------*/ 204 /** @defgroup ADC_LL_Private_Macros ADC Private Macros 205 * @{ 206 */ 207 208 /** 209 * @brief Driver macro reserved for internal use: isolate bits with the 210 * selected mask and shift them to the register LSB 211 * (shift mask on register position bit 0). 212 * @param __BITS__ Bits in register 32 bits 213 * @param __MASK__ Mask in register 32 bits 214 * @retval Bits in register 32 bits 215 */ 216 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ 217 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 218 219 /** 220 * @brief Driver macro reserved for internal use: set a pointer to 221 * a register from a register basis from which an offset 222 * is applied. 223 * @param __REG__ Register basis from which the offset is applied. 224 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 225 * @retval Pointer to register address 226 */ 227 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 228 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 229 230 /** 231 * @} 232 */ 233 234 235 /* Exported types ------------------------------------------------------------*/ 236 #if defined(USE_FULL_LL_DRIVER) 237 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure 238 * @{ 239 */ 240 241 /** 242 * @brief Structure definition of some features of ADC common parameters 243 * and multimode 244 * (all ADC instances belonging to the same ADC common instance). 245 * @note The setting of these parameters by function @ref LL_ADC_CommonInit() 246 * is conditioned to ADC instances state (all ADC instances 247 * sharing the same ADC common instance): 248 * All ADC instances sharing the same ADC common instance must be 249 * disabled. 250 */ 251 typedef struct 252 { 253 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). 254 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE 255 256 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ 257 } LL_ADC_CommonInitTypeDef; 258 /** 259 * @brief Structure definition of some features of ADC instance. 260 * @note These parameters have an impact on ADC scope: ADC instance. 261 * Affects both group regular and group injected (availability 262 * of ADC group injected depends on STM32 families). 263 * Refer to corresponding unitary functions into 264 * @ref ADC_LL_EF_Configuration_ADC_Instance . 265 * @note The setting of these parameters by function @ref LL_ADC_Init() 266 * is conditioned to ADC state: 267 * ADC instance must be disabled. 268 * This condition is applied to all ADC features, for efficiency 269 * and compatibility over all STM32 families. However, the different 270 * features can be set under different ADC state conditions 271 * (setting possible with ADC enabled without conversion on going, 272 * ADC enabled with conversion on going, ...) 273 * Each feature can be updated afterwards with a unitary function 274 * and potentially with ADC in a different state than disabled, 275 * refer to description of each function for setting 276 * conditioned to ADC state. 277 */ 278 typedef struct 279 { 280 uint32_t DataAlignment; /*!< Set ADC conversion data alignment. 281 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN 282 283 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ 284 285 uint32_t SequencersScanMode; /*!< Set ADC scan selection. 286 This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION 287 288 This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ 289 290 } LL_ADC_InitTypeDef; 291 292 /** 293 * @brief Structure definition of some features of ADC group regular. 294 * @note These parameters have an impact on ADC scope: ADC group regular. 295 * Refer to corresponding unitary functions into 296 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 297 * (functions with prefix "REG"). 298 * @note The setting of these parameters by function @ref LL_ADC_REG_Init() 299 * is conditioned to ADC state: 300 * ADC instance must be disabled. 301 * This condition is applied to all ADC features, for efficiency 302 * and compatibility over all STM32 families. However, the different 303 * features can be set under different ADC state conditions 304 * (setting possible with ADC enabled without conversion on going, 305 * ADC enabled with conversion on going, ...) 306 * Each feature can be updated afterwards with a unitary function 307 * and potentially with ADC in a different state than disabled, 308 * refer to description of each function for setting 309 * conditioned to ADC state. 310 */ 311 typedef struct 312 { 313 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 314 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE 315 @note On this STM32 series, external trigger is set with trigger polarity: rising edge 316 (only trigger polarity available on this STM32 series). 317 318 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ 319 320 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. 321 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH 322 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 323 324 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ 325 326 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 327 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE 328 @note This parameter has an effect only if group regular sequencer is enabled 329 (scan length of 2 ranks or more). 330 331 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ 332 333 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). 334 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE 335 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. 336 337 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ 338 339 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. 340 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER 341 342 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ 343 344 } LL_ADC_REG_InitTypeDef; 345 346 /** 347 * @brief Structure definition of some features of ADC group injected. 348 * @note These parameters have an impact on ADC scope: ADC group injected. 349 * Refer to corresponding unitary functions into 350 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 351 * (functions with prefix "INJ"). 352 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() 353 * is conditioned to ADC state: 354 * ADC instance must be disabled. 355 * This condition is applied to all ADC features, for efficiency 356 * and compatibility over all STM32 families. However, the different 357 * features can be set under different ADC state conditions 358 * (setting possible with ADC enabled without conversion on going, 359 * ADC enabled with conversion on going, ...) 360 * Each feature can be updated afterwards with a unitary function 361 * and potentially with ADC in a different state than disabled, 362 * refer to description of each function for setting 363 * conditioned to ADC state. 364 */ 365 typedef struct 366 { 367 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). 368 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE 369 @note On this STM32 series, external trigger is set with trigger polarity: rising edge 370 (only trigger polarity available on this STM32 series). 371 372 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ 373 374 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. 375 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH 376 @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). 377 378 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ 379 380 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. 381 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE 382 @note This parameter has an effect only if group injected sequencer is enabled 383 (scan length of 2 ranks or more). 384 385 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ 386 387 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. 388 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO 389 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. 390 391 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ 392 393 } LL_ADC_INJ_InitTypeDef; 394 395 /** 396 * @} 397 */ 398 #endif /* USE_FULL_LL_DRIVER */ 399 400 /* Exported constants --------------------------------------------------------*/ 401 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants 402 * @{ 403 */ 404 405 /** @defgroup ADC_LL_EC_FLAG ADC flags 406 * @brief Flags defines which can be used with LL_ADC_ReadReg function 407 * @{ 408 */ 409 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ 410 #define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ 411 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ 412 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 413 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ 414 #if defined(ADC_MULTIMODE_SUPPORT) 415 #define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ 416 #define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ 417 #define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 418 #define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ 419 #define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ 420 #define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ 421 #endif 422 /** 423 * @} 424 */ 425 426 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) 427 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions 428 * @{ 429 */ 430 #define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 series, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ 431 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ 432 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ 433 /** 434 * @} 435 */ 436 437 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose 438 * @{ 439 */ 440 /* List of ADC registers intended to be used (most commonly) with */ 441 /* DMA transfer. */ 442 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ 443 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ 444 #if defined(ADC_MULTIMODE_SUPPORT) 445 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ 446 #endif 447 /** 448 * @} 449 */ 450 451 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels 452 * @{ 453 */ 454 /* Note: Other measurement paths to internal channels may be available */ 455 /* (connections to other peripherals). */ 456 /* If they are not listed below, they do not require any specific */ 457 /* path enable. In this case, Access to measurement path is done */ 458 /* only by selecting the corresponding ADC internal channel. */ 459 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */ 460 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ 461 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ 462 /** 463 * @} 464 */ 465 466 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution 467 * @{ 468 */ 469 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ 470 /** 471 * @} 472 */ 473 474 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment 475 * @{ 476 */ 477 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 478 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 479 /** 480 * @} 481 */ 482 483 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection 484 * @{ 485 */ 486 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ 487 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ 488 /** 489 * @} 490 */ 491 492 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups 493 * @{ 494 */ 495 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ 496 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ 497 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ 498 /** 499 * @} 500 */ 501 502 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number 503 * @{ 504 */ 505 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 506 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 507 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 508 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 509 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 510 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 511 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 512 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 513 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 514 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 515 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 516 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 517 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 518 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 519 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 520 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 521 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 522 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 523 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */ 524 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ 525 /** 526 * @} 527 */ 528 529 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source 530 * @{ 531 */ 532 /* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ 533 #define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */ 534 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 535 /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ 536 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 537 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 538 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 539 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 540 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 541 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 542 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) 543 /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ 544 /* XL-density devices. */ 545 /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ 546 /* A remap of trigger must be done at top level (refer to */ 547 /* AFIO peripheral). */ 548 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/ 549 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 550 #if defined (STM32F103xE) || defined (STM32F103xG) 551 /* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ 552 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 553 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 554 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 555 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 556 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 557 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 558 #endif 559 /** 560 * @} 561 */ 562 563 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge 564 * @{ 565 */ 566 #define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */ 567 /** 568 * @} 569 */ 570 571 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode 572 * @{ 573 */ 574 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ 575 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ 576 /** 577 * @} 578 */ 579 580 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data 581 * @{ 582 */ 583 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ 584 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ 585 /** 586 * @} 587 */ 588 589 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length 590 * @{ 591 */ 592 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 593 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ 594 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ 595 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ 596 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ 597 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ 598 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ 599 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ 600 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ 601 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ 602 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ 603 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ 604 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ 605 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ 606 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ 607 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ 608 /** 609 * @} 610 */ 611 612 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode 613 * @{ 614 */ 615 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ 616 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ 617 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ 618 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ 619 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ 620 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ 621 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ 622 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ 623 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ 624 /** 625 * @} 626 */ 627 628 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 629 * @{ 630 */ 631 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ 632 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ 633 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ 634 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ 635 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ 636 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ 637 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ 638 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ 639 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ 640 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ 641 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ 642 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ 643 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ 644 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ 645 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ 646 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source 652 * @{ 653 */ 654 /* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ 655 #define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */ 656 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 657 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 658 /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ 659 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 660 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 661 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 662 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 663 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 664 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) 665 /* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */ 666 /* XL-density devices. */ 667 /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ 668 /* A remap of trigger must be done at top level (refer to */ 669 /* AFIO peripheral). */ 670 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */ 671 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ 672 #if defined (STM32F103xE) || defined (STM32F103xG) 673 /* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ 674 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 675 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 676 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 677 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ 678 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 679 #endif 680 /** 681 * @} 682 */ 683 684 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge 685 * @{ 686 */ 687 #define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */ 688 /** 689 * @} 690 */ 691 692 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode 693 * @{ 694 */ 695 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ 696 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ 697 /** 698 * @} 699 */ 700 701 702 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length 703 * @{ 704 */ 705 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ 706 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ 707 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ 708 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ 709 /** 710 * @} 711 */ 712 713 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode 714 * @{ 715 */ 716 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ 717 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ 718 /** 719 * @} 720 */ 721 722 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 723 * @{ 724 */ 725 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ 726 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ 727 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ 728 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ 729 /** 730 * @} 731 */ 732 733 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 734 * @{ 735 */ 736 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ 737 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */ 738 #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */ 739 #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */ 740 #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */ 741 #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */ 742 #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */ 743 #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */ 744 /** 745 * @} 746 */ 747 748 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 749 * @{ 750 */ 751 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ 752 /** 753 * @} 754 */ 755 756 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels 757 * @{ 758 */ 759 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ 760 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ 761 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ 762 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ 763 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ 764 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ 765 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ 766 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ 767 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ 768 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ 769 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ 770 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ 771 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ 772 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ 773 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ 774 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ 775 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ 776 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ 777 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ 778 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ 779 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ 780 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ 781 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ 782 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ 783 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ 784 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ 785 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ 786 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ 787 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ 788 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ 789 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ 790 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ 791 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ 792 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ 793 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ 794 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ 795 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ 796 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ 797 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ 798 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ 799 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ 800 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ 801 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ 802 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ 803 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ 804 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ 805 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ 806 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ 807 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ 808 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ 809 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ 810 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ 811 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ 812 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ 813 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ 814 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ 815 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ 816 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ 817 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ 818 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ 819 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ 820 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ 821 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ 822 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ 823 /** 824 * @} 825 */ 826 827 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds 828 * @{ 829 */ 830 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ 831 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ 832 /** 833 * @} 834 */ 835 836 #if !defined(ADC_MULTIMODE_SUPPORT) 837 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 838 * @{ 839 */ 840 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ 841 /** 842 * @} 843 */ 844 #endif 845 #if defined(ADC_MULTIMODE_SUPPORT) 846 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode 847 * @{ 848 */ 849 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ 850 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ 851 #define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */ 852 #define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ 853 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ 854 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 855 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 856 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 857 #define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */ 858 #define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */ 859 860 /** 861 * @} 862 */ 863 864 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave 865 * @{ 866 */ 867 #define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */ 868 #define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */ 869 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ 870 /** 871 * @} 872 */ 873 874 #endif /* ADC_MULTIMODE_SUPPORT */ 875 876 877 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays 878 * @note Only ADC IP HW delays are defined in ADC LL driver driver, 879 * not timeout values. 880 * For details on delays values, refer to descriptions in source code 881 * above each literal definition. 882 * @{ 883 */ 884 885 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ 886 /* not timeout values. */ 887 /* Timeout values for ADC operations are dependent to device clock */ 888 /* configuration (system clock versus ADC clock), */ 889 /* and therefore must be defined in user application. */ 890 /* Indications for estimation of ADC timeout delays, for this */ 891 /* STM32 series: */ 892 /* - ADC enable time: maximum delay is 1us */ 893 /* (refer to device datasheet, parameter "tSTAB") */ 894 /* - ADC conversion time: duration depending on ADC clock and ADC */ 895 /* configuration. */ 896 /* (refer to device reference manual, section "Timing") */ 897 898 /* Delay for temperature sensor stabilization time. */ 899 /* Literal set to maximum value (refer to device datasheet, */ 900 /* parameter "tSTART"). */ 901 /* Unit: us */ 902 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */ 903 904 /* Delay required between ADC disable and ADC calibration start. */ 905 /* Note: On this STM32 series, before starting a calibration, */ 906 /* ADC must be disabled. */ 907 /* A minimum number of ADC clock cycles are required */ 908 /* between ADC disable state and calibration start. */ 909 /* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */ 910 /* Wait time can be computed in user application by waiting for the */ 911 /* equivalent number of CPU cycles, by taking into account */ 912 /* ratio of CPU clock versus ADC clock prescalers. */ 913 /* Unit: ADC clock cycles. */ 914 #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */ 915 916 /* Delay required between end of ADC Enable and the start of ADC calibration. */ 917 /* Note: On this STM32 series, a minimum number of ADC clock cycles */ 918 /* are required between the end of ADC enable and the start of ADC */ 919 /* calibration. */ 920 /* Wait time can be computed in user application by waiting for the */ 921 /* equivalent number of CPU cycles, by taking into account */ 922 /* ratio of CPU clock versus ADC clock prescalers. */ 923 /* Unit: ADC clock cycles. */ 924 #define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */ 925 926 /** 927 * @} 928 */ 929 930 /** 931 * @} 932 */ 933 934 935 /* Exported macro ------------------------------------------------------------*/ 936 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros 937 * @{ 938 */ 939 940 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros 941 * @{ 942 */ 943 944 /** 945 * @brief Write a value in ADC register 946 * @param __INSTANCE__ ADC Instance 947 * @param __REG__ Register to be written 948 * @param __VALUE__ Value to be written in the register 949 * @retval None 950 */ 951 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 952 953 /** 954 * @brief Read a value in ADC register 955 * @param __INSTANCE__ ADC Instance 956 * @param __REG__ Register to be read 957 * @retval Register value 958 */ 959 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 960 /** 961 * @} 962 */ 963 964 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro 965 * @{ 966 */ 967 968 /** 969 * @brief Helper macro to get ADC channel number in decimal format 970 * from literals LL_ADC_CHANNEL_x. 971 * @note Example: 972 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) 973 * will return decimal number "4". 974 * @note The input can be a value from functions where a channel 975 * number is returned, either defined with number 976 * or with bitfield (only one bit must be set). 977 * @param __CHANNEL__ This parameter can be one of the following values: 978 * @arg @ref LL_ADC_CHANNEL_0 979 * @arg @ref LL_ADC_CHANNEL_1 980 * @arg @ref LL_ADC_CHANNEL_2 981 * @arg @ref LL_ADC_CHANNEL_3 982 * @arg @ref LL_ADC_CHANNEL_4 983 * @arg @ref LL_ADC_CHANNEL_5 984 * @arg @ref LL_ADC_CHANNEL_6 985 * @arg @ref LL_ADC_CHANNEL_7 986 * @arg @ref LL_ADC_CHANNEL_8 987 * @arg @ref LL_ADC_CHANNEL_9 988 * @arg @ref LL_ADC_CHANNEL_10 989 * @arg @ref LL_ADC_CHANNEL_11 990 * @arg @ref LL_ADC_CHANNEL_12 991 * @arg @ref LL_ADC_CHANNEL_13 992 * @arg @ref LL_ADC_CHANNEL_14 993 * @arg @ref LL_ADC_CHANNEL_15 994 * @arg @ref LL_ADC_CHANNEL_16 995 * @arg @ref LL_ADC_CHANNEL_17 996 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 997 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 998 * 999 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 1000 * @retval Value between Min_Data=0 and Max_Data=18 1001 */ 1002 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1003 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) 1004 1005 /** 1006 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x 1007 * from number in decimal format. 1008 * @note Example: 1009 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1010 * will return a data equivalent to "LL_ADC_CHANNEL_4". 1011 * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 1012 * @retval Returned value can be one of the following values: 1013 * @arg @ref LL_ADC_CHANNEL_0 1014 * @arg @ref LL_ADC_CHANNEL_1 1015 * @arg @ref LL_ADC_CHANNEL_2 1016 * @arg @ref LL_ADC_CHANNEL_3 1017 * @arg @ref LL_ADC_CHANNEL_4 1018 * @arg @ref LL_ADC_CHANNEL_5 1019 * @arg @ref LL_ADC_CHANNEL_6 1020 * @arg @ref LL_ADC_CHANNEL_7 1021 * @arg @ref LL_ADC_CHANNEL_8 1022 * @arg @ref LL_ADC_CHANNEL_9 1023 * @arg @ref LL_ADC_CHANNEL_10 1024 * @arg @ref LL_ADC_CHANNEL_11 1025 * @arg @ref LL_ADC_CHANNEL_12 1026 * @arg @ref LL_ADC_CHANNEL_13 1027 * @arg @ref LL_ADC_CHANNEL_14 1028 * @arg @ref LL_ADC_CHANNEL_15 1029 * @arg @ref LL_ADC_CHANNEL_16 1030 * @arg @ref LL_ADC_CHANNEL_17 1031 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1032 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 1033 * 1034 * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n 1035 * (1) For ADC channel read back from ADC register, 1036 * comparison with internal channel parameter to be done 1037 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1038 */ 1039 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1040 (((__DECIMAL_NB__) <= 9U) \ 1041 ? ( \ 1042 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 1043 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 1044 ) \ 1045 : \ 1046 ( \ 1047 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ 1048 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ 1049 ) \ 1050 ) 1051 1052 /** 1053 * @brief Helper macro to determine whether the selected channel 1054 * corresponds to literal definitions of driver. 1055 * @note The different literal definitions of ADC channels are: 1056 * - ADC internal channel: 1057 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... 1058 * - ADC external channel (channel connected to a GPIO pin): 1059 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... 1060 * @note The channel parameter must be a value defined from literal 1061 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 1062 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 1063 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), 1064 * must not be a value from functions where a channel number is 1065 * returned from ADC registers, 1066 * because internal and external channels share the same channel 1067 * number in ADC registers. The differentiation is made only with 1068 * parameters definitions of driver. 1069 * @param __CHANNEL__ This parameter can be one of the following values: 1070 * @arg @ref LL_ADC_CHANNEL_0 1071 * @arg @ref LL_ADC_CHANNEL_1 1072 * @arg @ref LL_ADC_CHANNEL_2 1073 * @arg @ref LL_ADC_CHANNEL_3 1074 * @arg @ref LL_ADC_CHANNEL_4 1075 * @arg @ref LL_ADC_CHANNEL_5 1076 * @arg @ref LL_ADC_CHANNEL_6 1077 * @arg @ref LL_ADC_CHANNEL_7 1078 * @arg @ref LL_ADC_CHANNEL_8 1079 * @arg @ref LL_ADC_CHANNEL_9 1080 * @arg @ref LL_ADC_CHANNEL_10 1081 * @arg @ref LL_ADC_CHANNEL_11 1082 * @arg @ref LL_ADC_CHANNEL_12 1083 * @arg @ref LL_ADC_CHANNEL_13 1084 * @arg @ref LL_ADC_CHANNEL_14 1085 * @arg @ref LL_ADC_CHANNEL_15 1086 * @arg @ref LL_ADC_CHANNEL_16 1087 * @arg @ref LL_ADC_CHANNEL_17 1088 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1089 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 1090 * 1091 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 1092 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1093 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1094 */ 1095 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1096 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) 1097 1098 /** 1099 * @brief Helper macro to convert a channel defined from parameter 1100 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 1101 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 1102 * to its equivalent parameter definition of a ADC external channel 1103 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). 1104 * @note The channel parameter can be, additionally to a value 1105 * defined from parameter definition of a ADC internal channel 1106 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), 1107 * a value defined from parameter definition of 1108 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 1109 * or a value from functions where a channel number is returned 1110 * from ADC registers. 1111 * @param __CHANNEL__ This parameter can be one of the following values: 1112 * @arg @ref LL_ADC_CHANNEL_0 1113 * @arg @ref LL_ADC_CHANNEL_1 1114 * @arg @ref LL_ADC_CHANNEL_2 1115 * @arg @ref LL_ADC_CHANNEL_3 1116 * @arg @ref LL_ADC_CHANNEL_4 1117 * @arg @ref LL_ADC_CHANNEL_5 1118 * @arg @ref LL_ADC_CHANNEL_6 1119 * @arg @ref LL_ADC_CHANNEL_7 1120 * @arg @ref LL_ADC_CHANNEL_8 1121 * @arg @ref LL_ADC_CHANNEL_9 1122 * @arg @ref LL_ADC_CHANNEL_10 1123 * @arg @ref LL_ADC_CHANNEL_11 1124 * @arg @ref LL_ADC_CHANNEL_12 1125 * @arg @ref LL_ADC_CHANNEL_13 1126 * @arg @ref LL_ADC_CHANNEL_14 1127 * @arg @ref LL_ADC_CHANNEL_15 1128 * @arg @ref LL_ADC_CHANNEL_16 1129 * @arg @ref LL_ADC_CHANNEL_17 1130 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1131 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 1132 * 1133 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 1134 * @retval Returned value can be one of the following values: 1135 * @arg @ref LL_ADC_CHANNEL_0 1136 * @arg @ref LL_ADC_CHANNEL_1 1137 * @arg @ref LL_ADC_CHANNEL_2 1138 * @arg @ref LL_ADC_CHANNEL_3 1139 * @arg @ref LL_ADC_CHANNEL_4 1140 * @arg @ref LL_ADC_CHANNEL_5 1141 * @arg @ref LL_ADC_CHANNEL_6 1142 * @arg @ref LL_ADC_CHANNEL_7 1143 * @arg @ref LL_ADC_CHANNEL_8 1144 * @arg @ref LL_ADC_CHANNEL_9 1145 * @arg @ref LL_ADC_CHANNEL_10 1146 * @arg @ref LL_ADC_CHANNEL_11 1147 * @arg @ref LL_ADC_CHANNEL_12 1148 * @arg @ref LL_ADC_CHANNEL_13 1149 * @arg @ref LL_ADC_CHANNEL_14 1150 * @arg @ref LL_ADC_CHANNEL_15 1151 * @arg @ref LL_ADC_CHANNEL_16 1152 * @arg @ref LL_ADC_CHANNEL_17 1153 */ 1154 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1155 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) 1156 1157 /** 1158 * @brief Helper macro to determine whether the internal channel 1159 * selected is available on the ADC instance selected. 1160 * @note The channel parameter must be a value defined from parameter 1161 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, 1162 * LL_ADC_CHANNEL_TEMPSENSOR, ...), 1163 * must not be a value defined from parameter definition of 1164 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) 1165 * or a value from functions where a channel number is 1166 * returned from ADC registers, 1167 * because internal and external channels share the same channel 1168 * number in ADC registers. The differentiation is made only with 1169 * parameters definitions of driver. 1170 * @param __ADC_INSTANCE__ ADC instance 1171 * @param __CHANNEL__ This parameter can be one of the following values: 1172 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1173 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 1174 * 1175 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 1176 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1177 * Value "1" if the internal channel selected is available on the ADC instance selected. 1178 */ 1179 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1180 (((__ADC_INSTANCE__) == ADC1) \ 1181 ? ( \ 1182 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ 1183 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \ 1184 ) \ 1185 : \ 1186 (0U) \ 1187 ) 1188 1189 /** 1190 * @brief Helper macro to define ADC analog watchdog parameter: 1191 * define a single channel to monitor with analog watchdog 1192 * from sequencer channel and groups definition. 1193 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). 1194 * Example: 1195 * LL_ADC_SetAnalogWDMonitChannels( 1196 * ADC1, LL_ADC_AWD1, 1197 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) 1198 * @param __CHANNEL__ This parameter can be one of the following values: 1199 * @arg @ref LL_ADC_CHANNEL_0 1200 * @arg @ref LL_ADC_CHANNEL_1 1201 * @arg @ref LL_ADC_CHANNEL_2 1202 * @arg @ref LL_ADC_CHANNEL_3 1203 * @arg @ref LL_ADC_CHANNEL_4 1204 * @arg @ref LL_ADC_CHANNEL_5 1205 * @arg @ref LL_ADC_CHANNEL_6 1206 * @arg @ref LL_ADC_CHANNEL_7 1207 * @arg @ref LL_ADC_CHANNEL_8 1208 * @arg @ref LL_ADC_CHANNEL_9 1209 * @arg @ref LL_ADC_CHANNEL_10 1210 * @arg @ref LL_ADC_CHANNEL_11 1211 * @arg @ref LL_ADC_CHANNEL_12 1212 * @arg @ref LL_ADC_CHANNEL_13 1213 * @arg @ref LL_ADC_CHANNEL_14 1214 * @arg @ref LL_ADC_CHANNEL_15 1215 * @arg @ref LL_ADC_CHANNEL_16 1216 * @arg @ref LL_ADC_CHANNEL_17 1217 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 1218 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 1219 * 1220 * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n 1221 * (1) For ADC channel read back from ADC register, 1222 * comparison with internal channel parameter to be done 1223 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1224 * @param __GROUP__ This parameter can be one of the following values: 1225 * @arg @ref LL_ADC_GROUP_REGULAR 1226 * @arg @ref LL_ADC_GROUP_INJECTED 1227 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED 1228 * @retval Returned value can be one of the following values: 1229 * @arg @ref LL_ADC_AWD_DISABLE 1230 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 1231 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 1232 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 1233 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 1234 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 1235 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 1236 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 1237 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 1238 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 1239 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 1240 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 1241 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 1242 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 1243 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 1244 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 1245 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 1246 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 1247 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 1248 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 1249 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 1250 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 1251 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 1252 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 1253 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 1254 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 1255 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 1256 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 1257 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 1258 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 1259 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 1260 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 1261 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 1262 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 1263 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 1264 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 1265 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 1266 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 1267 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 1268 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 1269 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 1270 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 1271 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 1272 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 1273 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 1274 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 1275 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 1276 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 1277 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 1278 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 1279 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 1280 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 1281 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 1282 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 1283 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 1284 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 1285 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 1286 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 1287 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 1288 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 1289 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 1290 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) 1291 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) 1292 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) 1293 * 1294 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 1295 */ 1296 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ 1297 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ 1298 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 1299 : \ 1300 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ 1301 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ 1302 : \ 1303 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ 1304 ) 1305 1306 /** 1307 * @brief Helper macro to set the value of ADC analog watchdog threshold high 1308 * or low in function of ADC resolution, when ADC resolution is 1309 * different of 12 bits. 1310 * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). 1311 * Example, with a ADC resolution of 8 bits, to set the value of 1312 * analog watchdog threshold high (on 8 bits): 1313 * LL_ADC_SetAnalogWDThresholds 1314 * (< ADCx param >, 1315 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>) 1316 * ); 1317 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1318 * @arg @ref LL_ADC_RESOLUTION_12B 1319 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF 1320 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1321 */ 1322 /* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */ 1323 /* This macro has been kept anyway for compatibility with other */ 1324 /* STM32 families featuring different ADC resolutions. */ 1325 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ 1326 ((__AWD_THRESHOLD__) << (0U)) 1327 1328 /** 1329 * @brief Helper macro to get the value of ADC analog watchdog threshold high 1330 * or low in function of ADC resolution, when ADC resolution is 1331 * different of 12 bits. 1332 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). 1333 * Example, with a ADC resolution of 8 bits, to get the value of 1334 * analog watchdog threshold high (on 8 bits): 1335 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION 1336 * (LL_ADC_RESOLUTION_8B, 1337 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH) 1338 * ); 1339 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1340 * @arg @ref LL_ADC_RESOLUTION_12B 1341 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF 1342 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1343 */ 1344 /* Note: On this STM32 series, ADC is fixed to resolution 12 bits. */ 1345 /* This macro has been kept anyway for compatibility with other */ 1346 /* STM32 families featuring different ADC resolutions. */ 1347 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ 1348 (__AWD_THRESHOLD_12_BITS__) 1349 1350 #if defined(ADC_MULTIMODE_SUPPORT) 1351 /** 1352 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1353 * or ADC slave from raw value with both ADC conversion data concatenated. 1354 * @note This macro is intended to be used when multimode transfer by DMA 1355 * is enabled. 1356 * In this case the transferred data need to processed with this macro 1357 * to separate the conversion data of ADC master and ADC slave. 1358 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1359 * @arg @ref LL_ADC_MULTI_MASTER 1360 * @arg @ref LL_ADC_MULTI_SLAVE 1361 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1362 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1363 */ 1364 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1365 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA) 1366 #endif 1367 1368 /** 1369 * @brief Helper macro to select the ADC common instance 1370 * to which is belonging the selected ADC instance. 1371 * @note ADC common register instance can be used for: 1372 * - Set parameters common to several ADC instances 1373 * - Multimode (for devices with several ADC instances) 1374 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1375 * @note On STM32F1, there is no common ADC instance. 1376 * However, ADC instance ADC1 has a role of common ADC instance 1377 * for ADC1 and ADC2: 1378 * this instance is used to manage internal channels 1379 * and multimode (these features are managed in ADC common 1380 * instances on some other STM32 devices). 1381 * ADC instance ADC3 (if available on the selected device) 1382 * has no ADC common instance. 1383 * @param __ADCx__ ADC instance 1384 * @retval ADC common register instance 1385 */ 1386 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 1387 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 1388 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \ 1389 ? ( \ 1390 (ADC12_COMMON) \ 1391 ) \ 1392 : \ 1393 ( \ 1394 (0U) \ 1395 ) \ 1396 ) 1397 #elif defined(ADC1) && defined(ADC2) 1398 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 1399 (ADC12_COMMON) 1400 #else 1401 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ 1402 (ADC1_COMMON) 1403 #endif 1404 1405 /** 1406 * @brief Helper macro to check if all ADC instances sharing the same 1407 * ADC common instance are disabled. 1408 * @note This check is required by functions with setting conditioned to 1409 * ADC state: 1410 * All ADC instances of the ADC common group must be disabled. 1411 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1412 * @note On devices with only 1 ADC common instance, parameter of this macro 1413 * is useless and can be ignored (parameter kept for compatibility 1414 * with devices featuring several ADC common instances). 1415 * @note On STM32F1, there is no common ADC instance. 1416 * However, ADC instance ADC1 has a role of common ADC instance 1417 * for ADC1 and ADC2: 1418 * this instance is used to manage internal channels 1419 * and multimode (these features are managed in ADC common 1420 * instances on some other STM32 devices). 1421 * ADC instance ADC3 (if available on the selected device) 1422 * has no ADC common instance. 1423 * @param __ADCXY_COMMON__ ADC common instance 1424 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1425 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1426 * are disabled. 1427 * Value "1" if at least one ADC instance sharing the same ADC common instance 1428 * is enabled. 1429 */ 1430 #if defined(ADC1) && defined(ADC2) && defined(ADC3) 1431 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1432 (((__ADCXY_COMMON__) == ADC12_COMMON) \ 1433 ? ( \ 1434 (LL_ADC_IsEnabled(ADC1) | \ 1435 LL_ADC_IsEnabled(ADC2) ) \ 1436 ) \ 1437 : \ 1438 ( \ 1439 LL_ADC_IsEnabled(ADC3) \ 1440 ) \ 1441 ) 1442 #elif defined(ADC1) && defined(ADC2) 1443 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1444 (LL_ADC_IsEnabled(ADC1) | \ 1445 LL_ADC_IsEnabled(ADC2) ) 1446 #else 1447 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1448 LL_ADC_IsEnabled(ADC1) 1449 #endif 1450 1451 /** 1452 * @brief Helper macro to define the ADC conversion data full-scale digital 1453 * value corresponding to the selected ADC resolution. 1454 * @note ADC conversion data full-scale corresponds to voltage range 1455 * determined by analog voltage references Vref+ and Vref- 1456 * (refer to reference manual). 1457 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1458 * @arg @ref LL_ADC_RESOLUTION_12B 1459 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1460 */ 1461 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1462 (0xFFFU) 1463 1464 1465 /** 1466 * @brief Helper macro to calculate the voltage (unit: mVolt) 1467 * corresponding to a ADC conversion data (unit: digital value). 1468 * @note Analog reference voltage (Vref+) must be known from 1469 * user board environment or can be calculated using ADC measurement. 1470 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1471 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1472 * (unit: digital value). 1473 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1474 * @arg @ref LL_ADC_RESOLUTION_12B 1475 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1476 */ 1477 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1478 __ADC_DATA__,\ 1479 __ADC_RESOLUTION__) \ 1480 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ 1481 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1482 ) 1483 1484 1485 /** 1486 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1487 * from ADC conversion data of internal temperature sensor. 1488 * @note Computation is using temperature sensor typical values 1489 * (refer to device datasheet). 1490 * @note Calculation formula: 1491 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1492 * / Avg_Slope + CALx_TEMP 1493 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1494 * (unit: digital value) 1495 * Avg_Slope = temperature sensor slope 1496 * (unit: uV/Degree Celsius) 1497 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1498 * temperature CALx_TEMP (unit: mV) 1499 * Caution: Calculation relevancy under reserve the temperature sensor 1500 * of the current device has characteristics in line with 1501 * datasheet typical values. 1502 * If temperature sensor calibration values are available on 1503 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1504 * temperature calculation will be more accurate using 1505 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1506 * @note As calculation input, the analog reference voltage (Vref+) must be 1507 * defined as it impacts the ADC LSB equivalent voltage. 1508 * @note Analog reference voltage (Vref+) must be known from 1509 * user board environment or can be calculated using ADC measurement. 1510 * @note ADC measurement data must correspond to a resolution of 12bits 1511 * (full scale digital value 4095). If not the case, the data must be 1512 * preliminarily rescaled to an equivalent resolution of 12 bits. 1513 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1514 * On STM32F1, refer to device datasheet parameter "Avg_Slope". 1515 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1516 * On STM32F1, refer to device datasheet parameter "V25". 1517 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1518 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1519 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1520 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1521 * This parameter can be one of the following values: 1522 * @arg @ref LL_ADC_RESOLUTION_12B 1523 * @retval Temperature (unit: degree Celsius) 1524 */ 1525 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1526 __TEMPSENSOR_TYP_CALX_V__,\ 1527 __TEMPSENSOR_CALX_TEMP__,\ 1528 __VREFANALOG_VOLTAGE__,\ 1529 __TEMPSENSOR_ADC_DATA__,\ 1530 __ADC_RESOLUTION__) \ 1531 ((( ( \ 1532 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ 1533 * 1000) \ 1534 - \ 1535 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ 1536 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ 1537 * 1000) \ 1538 ) \ 1539 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ 1540 ) + (__TEMPSENSOR_CALX_TEMP__) \ 1541 ) 1542 1543 /** 1544 * @} 1545 */ 1546 1547 /** 1548 * @} 1549 */ 1550 1551 1552 /* Exported functions --------------------------------------------------------*/ 1553 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions 1554 * @{ 1555 */ 1556 1557 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management 1558 * @{ 1559 */ 1560 /* Note: LL ADC functions to set DMA transfer are located into sections of */ 1561 /* configuration of ADC instance, groups and multimode (if available): */ 1562 /* @ref LL_ADC_REG_SetDMATransfer(), ... */ 1563 1564 /** 1565 * @brief Function to help to configure DMA transfer from ADC: retrieve the 1566 * ADC register address from ADC instance and a list of ADC registers 1567 * intended to be used (most commonly) with DMA transfer. 1568 * @note These ADC registers are data registers: 1569 * when ADC conversion data is available in ADC data registers, 1570 * ADC generates a DMA transfer request. 1571 * @note This macro is intended to be used with LL DMA driver, refer to 1572 * function "LL_DMA_ConfigAddresses()". 1573 * Example: 1574 * LL_DMA_ConfigAddresses(DMA1, 1575 * LL_DMA_CHANNEL_1, 1576 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), 1577 * (uint32_t)&< array or variable >, 1578 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); 1579 * @note For devices with several ADC: in multimode, some devices 1580 * use a different data register outside of ADC instance scope 1581 * (common data register). This macro manages this register difference, 1582 * only ADC instance has to be set as parameter. 1583 * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer 1584 * capability, not ADC2 (ADC2 and ADC3 instances not available on 1585 * all devices). 1586 * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3. 1587 * Therefore, the corresponding parameter of data transfer 1588 * for multimode can be used only with ADC1 and ADC2. 1589 * (ADC2 and ADC3 instances not available on all devices). 1590 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr 1591 * @param ADCx ADC instance 1592 * @param Register This parameter can be one of the following values: 1593 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA 1594 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) 1595 * 1596 * (1) Available on devices with several ADC instances. 1597 * @retval ADC register address 1598 */ 1599 #if defined(ADC_MULTIMODE_SUPPORT) 1600 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 1601 { 1602 uint32_t data_reg_addr = 0U; 1603 1604 if (Register == LL_ADC_DMA_REG_REGULAR_DATA) 1605 { 1606 /* Retrieve address of register DR */ 1607 data_reg_addr = (uint32_t)&(ADCx->DR); 1608 } 1609 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ 1610 { 1611 /* Retrieve address of register of multimode data */ 1612 data_reg_addr = (uint32_t)&(ADC12_COMMON->DR); 1613 } 1614 1615 return data_reg_addr; 1616 } 1617 #else 1618 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) 1619 { 1620 /* Retrieve address of register DR */ 1621 return (uint32_t)&(ADCx->DR); 1622 } 1623 #endif 1624 1625 /** 1626 * @} 1627 */ 1628 1629 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances 1630 * @{ 1631 */ 1632 1633 /** 1634 * @brief Set parameter common to several ADC: measurement path to internal 1635 * channels (VrefInt, temperature sensor, ...). 1636 * @note One or several values can be selected. 1637 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 1638 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 1639 * @note Stabilization time of measurement path to internal channel: 1640 * After enabling internal paths, before starting ADC conversion, 1641 * a delay is required for internal voltage reference and 1642 * temperature sensor stabilization time. 1643 * Refer to device datasheet. 1644 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. 1645 * @note ADC internal channel sampling time constraint: 1646 * For ADC conversion of internal channels, 1647 * a sampling time minimum value is required. 1648 * Refer to device datasheet. 1649 * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh 1650 * @param ADCxy_COMMON ADC common instance 1651 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1652 * @param PathInternal This parameter can be a combination of the following values: 1653 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 1654 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 1655 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 1656 * @retval None 1657 */ 1658 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) 1659 { 1660 MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal); 1661 } 1662 1663 /** 1664 * @brief Get parameter common to several ADC: measurement path to internal 1665 * channels (VrefInt, temperature sensor, ...). 1666 * @note One or several values can be selected. 1667 * Example: (LL_ADC_PATH_INTERNAL_VREFINT | 1668 * LL_ADC_PATH_INTERNAL_TEMPSENSOR) 1669 * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh 1670 * @param ADCxy_COMMON ADC common instance 1671 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1672 * @retval Returned value can be a combination of the following values: 1673 * @arg @ref LL_ADC_PATH_INTERNAL_NONE 1674 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT 1675 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR 1676 */ 1677 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) 1678 { 1679 return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE)); 1680 } 1681 1682 /** 1683 * @} 1684 */ 1685 1686 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance 1687 * @{ 1688 */ 1689 1690 /** 1691 * @brief Set ADC conversion data alignment. 1692 * @note Refer to reference manual for alignments formats 1693 * dependencies to ADC resolutions. 1694 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 1695 * @param ADCx ADC instance 1696 * @param DataAlignment This parameter can be one of the following values: 1697 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 1698 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 1699 * @retval None 1700 */ 1701 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) 1702 { 1703 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); 1704 } 1705 1706 /** 1707 * @brief Get ADC conversion data alignment. 1708 * @note Refer to reference manual for alignments formats 1709 * dependencies to ADC resolutions. 1710 * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment 1711 * @param ADCx ADC instance 1712 * @retval Returned value can be one of the following values: 1713 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT 1714 * @arg @ref LL_ADC_DATA_ALIGN_LEFT 1715 */ 1716 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) 1717 { 1718 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); 1719 } 1720 1721 /** 1722 * @brief Set ADC sequencers scan mode, for all ADC groups 1723 * (group regular, group injected). 1724 * @note According to sequencers scan mode : 1725 * - If disabled: ADC conversion is performed in unitary conversion 1726 * mode (one channel converted, that defined in rank 1). 1727 * Configuration of sequencers of all ADC groups 1728 * (sequencer scan length, ...) is discarded: equivalent to 1729 * scan length of 1 rank. 1730 * - If enabled: ADC conversions are performed in sequence conversions 1731 * mode, according to configuration of sequencers of 1732 * each ADC group (sequencer scan length, ...). 1733 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 1734 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 1735 * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode 1736 * @param ADCx ADC instance 1737 * @param ScanMode This parameter can be one of the following values: 1738 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 1739 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 1740 * @retval None 1741 */ 1742 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) 1743 { 1744 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); 1745 } 1746 1747 /** 1748 * @brief Get ADC sequencers scan mode, for all ADC groups 1749 * (group regular, group injected). 1750 * @note According to sequencers scan mode : 1751 * - If disabled: ADC conversion is performed in unitary conversion 1752 * mode (one channel converted, that defined in rank 1). 1753 * Configuration of sequencers of all ADC groups 1754 * (sequencer scan length, ...) is discarded: equivalent to 1755 * scan length of 1 rank. 1756 * - If enabled: ADC conversions are performed in sequence conversions 1757 * mode, according to configuration of sequencers of 1758 * each ADC group (sequencer scan length, ...). 1759 * Refer to function @ref LL_ADC_REG_SetSequencerLength() 1760 * and to function @ref LL_ADC_INJ_SetSequencerLength(). 1761 * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode 1762 * @param ADCx ADC instance 1763 * @retval Returned value can be one of the following values: 1764 * @arg @ref LL_ADC_SEQ_SCAN_DISABLE 1765 * @arg @ref LL_ADC_SEQ_SCAN_ENABLE 1766 */ 1767 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) 1768 { 1769 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); 1770 } 1771 1772 /** 1773 * @} 1774 */ 1775 1776 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular 1777 * @{ 1778 */ 1779 1780 /** 1781 * @brief Set ADC group regular conversion trigger source: 1782 * internal (SW start) or from external IP (timer event, 1783 * external interrupt line). 1784 * @note On this STM32 series, external trigger is set with trigger polarity: 1785 * rising edge (only trigger polarity available on this STM32 series). 1786 * @note Availability of parameters of trigger sources from timer 1787 * depends on timers availability on the selected device. 1788 * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource 1789 * @param ADCx ADC instance 1790 * @param TriggerSource This parameter can be one of the following values: 1791 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 1792 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) 1793 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) 1794 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) 1795 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) 1796 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) 1797 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) 1798 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) 1799 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) 1800 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) 1801 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) 1802 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) 1803 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) 1804 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) 1805 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) 1806 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) 1807 * 1808 * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n 1809 * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n 1810 * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n 1811 * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). 1812 * @retval None 1813 */ 1814 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 1815 { 1816 /* Note: On this STM32 series, ADC group regular external trigger edge */ 1817 /* is used to perform a ADC conversion start. */ 1818 /* This function does not set external trigger edge. */ 1819 /* This feature is set using function */ 1820 /* @ref LL_ADC_REG_StartConversionExtTrig(). */ 1821 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); 1822 } 1823 1824 /** 1825 * @brief Get ADC group regular conversion trigger source: 1826 * internal (SW start) or from external IP (timer event, 1827 * external interrupt line). 1828 * @note To determine whether group regular trigger source is 1829 * internal (SW start) or external, without detail 1830 * of which peripheral is selected as external trigger, 1831 * (equivalent to 1832 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") 1833 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. 1834 * @note Availability of parameters of trigger sources from timer 1835 * depends on timers availability on the selected device. 1836 * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource 1837 * @param ADCx ADC instance 1838 * @retval Returned value can be one of the following values: 1839 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE 1840 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) 1841 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) 1842 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) 1843 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) 1844 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) 1845 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) 1846 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) 1847 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) 1848 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) 1849 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) 1850 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) 1851 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) 1852 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) 1853 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) 1854 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) 1855 * 1856 * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n 1857 * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n 1858 * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n 1859 * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). 1860 */ 1861 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) 1862 { 1863 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL)); 1864 } 1865 1866 /** 1867 * @brief Get ADC group regular conversion trigger source internal (SW start) 1868 or external. 1869 * @note In case of group regular trigger source set to external trigger, 1870 * to determine which peripheral is selected as external trigger, 1871 * use function @ref LL_ADC_REG_GetTriggerSource(). 1872 * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart 1873 * @param ADCx ADC instance 1874 * @retval Value "0" if trigger source external trigger 1875 * Value "1" if trigger source SW start. 1876 */ 1877 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 1878 { 1879 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE)); 1880 } 1881 1882 1883 /** 1884 * @brief Set ADC group regular sequencer length and scan direction. 1885 * @note Description of ADC group regular sequencer features: 1886 * - For devices with sequencer fully configurable 1887 * (function "LL_ADC_REG_SetSequencerRanks()" available): 1888 * sequencer length and each rank affectation to a channel 1889 * are configurable. 1890 * This function performs configuration of: 1891 * - Sequence length: Number of ranks in the scan sequence. 1892 * - Sequence direction: Unless specified in parameters, sequencer 1893 * scan direction is forward (from rank 1 to rank n). 1894 * Sequencer ranks are selected using 1895 * function "LL_ADC_REG_SetSequencerRanks()". 1896 * - For devices with sequencer not fully configurable 1897 * (function "LL_ADC_REG_SetSequencerChannels()" available): 1898 * sequencer length and each rank affectation to a channel 1899 * are defined by channel number. 1900 * This function performs configuration of: 1901 * - Sequence length: Number of ranks in the scan sequence is 1902 * defined by number of channels set in the sequence, 1903 * rank of each channel is fixed by channel HW number. 1904 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 1905 * - Sequence direction: Unless specified in parameters, sequencer 1906 * scan direction is forward (from lowest channel number to 1907 * highest channel number). 1908 * Sequencer ranks are selected using 1909 * function "LL_ADC_REG_SetSequencerChannels()". 1910 * @note On this STM32 series, group regular sequencer configuration 1911 * is conditioned to ADC instance sequencer mode. 1912 * If ADC instance sequencer mode is disabled, sequencers of 1913 * all groups (group regular, group injected) can be configured 1914 * but their execution is disabled (limited to rank 1). 1915 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 1916 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 1917 * ADC conversion on only 1 channel. 1918 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 1919 * @param ADCx ADC instance 1920 * @param SequencerNbRanks This parameter can be one of the following values: 1921 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 1922 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 1923 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 1924 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 1925 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 1926 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 1927 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 1928 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 1929 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 1930 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 1931 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 1932 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 1933 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 1934 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 1935 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 1936 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 1937 * @retval None 1938 */ 1939 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 1940 { 1941 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); 1942 } 1943 1944 /** 1945 * @brief Get ADC group regular sequencer length and scan direction. 1946 * @note Description of ADC group regular sequencer features: 1947 * - For devices with sequencer fully configurable 1948 * (function "LL_ADC_REG_SetSequencerRanks()" available): 1949 * sequencer length and each rank affectation to a channel 1950 * are configurable. 1951 * This function retrieves: 1952 * - Sequence length: Number of ranks in the scan sequence. 1953 * - Sequence direction: Unless specified in parameters, sequencer 1954 * scan direction is forward (from rank 1 to rank n). 1955 * Sequencer ranks are selected using 1956 * function "LL_ADC_REG_SetSequencerRanks()". 1957 * - For devices with sequencer not fully configurable 1958 * (function "LL_ADC_REG_SetSequencerChannels()" available): 1959 * sequencer length and each rank affectation to a channel 1960 * are defined by channel number. 1961 * This function retrieves: 1962 * - Sequence length: Number of ranks in the scan sequence is 1963 * defined by number of channels set in the sequence, 1964 * rank of each channel is fixed by channel HW number. 1965 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 1966 * - Sequence direction: Unless specified in parameters, sequencer 1967 * scan direction is forward (from lowest channel number to 1968 * highest channel number). 1969 * Sequencer ranks are selected using 1970 * function "LL_ADC_REG_SetSequencerChannels()". 1971 * @note On this STM32 series, group regular sequencer configuration 1972 * is conditioned to ADC instance sequencer mode. 1973 * If ADC instance sequencer mode is disabled, sequencers of 1974 * all groups (group regular, group injected) can be configured 1975 * but their execution is disabled (limited to rank 1). 1976 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 1977 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 1978 * ADC conversion on only 1 channel. 1979 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength 1980 * @param ADCx ADC instance 1981 * @retval Returned value can be one of the following values: 1982 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE 1983 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS 1984 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS 1985 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS 1986 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS 1987 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS 1988 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS 1989 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS 1990 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS 1991 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS 1992 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS 1993 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS 1994 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS 1995 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS 1996 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS 1997 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS 1998 */ 1999 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) 2000 { 2001 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); 2002 } 2003 2004 /** 2005 * @brief Set ADC group regular sequencer discontinuous mode: 2006 * sequence subdivided and scan conversions interrupted every selected 2007 * number of ranks. 2008 * @note It is not possible to enable both ADC group regular 2009 * continuous mode and sequencer discontinuous mode. 2010 * @note It is not possible to enable both ADC auto-injected mode 2011 * and ADC group regular sequencer discontinuous mode. 2012 * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n 2013 * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont 2014 * @param ADCx ADC instance 2015 * @param SeqDiscont This parameter can be one of the following values: 2016 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 2017 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 2018 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 2019 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 2020 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 2021 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 2022 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 2023 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 2024 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 2025 * @retval None 2026 */ 2027 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 2028 { 2029 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); 2030 } 2031 2032 /** 2033 * @brief Get ADC group regular sequencer discontinuous mode: 2034 * sequence subdivided and scan conversions interrupted every selected 2035 * number of ranks. 2036 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n 2037 * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont 2038 * @param ADCx ADC instance 2039 * @retval Returned value can be one of the following values: 2040 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE 2041 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK 2042 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS 2043 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS 2044 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS 2045 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS 2046 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS 2047 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS 2048 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS 2049 */ 2050 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) 2051 { 2052 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); 2053 } 2054 2055 /** 2056 * @brief Set ADC group regular sequence: channel on the selected 2057 * scan sequence rank. 2058 * @note This function performs configuration of: 2059 * - Channels ordering into each rank of scan sequence: 2060 * whatever channel can be placed into whatever rank. 2061 * @note On this STM32 series, ADC group regular sequencer is 2062 * fully configurable: sequencer length and each rank 2063 * affectation to a channel are configurable. 2064 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 2065 * @note Depending on devices and packages, some channels may not be available. 2066 * Refer to device datasheet for channels availability. 2067 * @note On this STM32 series, to measure internal channels (VrefInt, 2068 * TempSensor, ...), measurement paths to internal channels must be 2069 * enabled separately. 2070 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 2071 * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n 2072 * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n 2073 * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n 2074 * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n 2075 * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n 2076 * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n 2077 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n 2078 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n 2079 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n 2080 * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n 2081 * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n 2082 * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n 2083 * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n 2084 * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n 2085 * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n 2086 * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks 2087 * @param ADCx ADC instance 2088 * @param Rank This parameter can be one of the following values: 2089 * @arg @ref LL_ADC_REG_RANK_1 2090 * @arg @ref LL_ADC_REG_RANK_2 2091 * @arg @ref LL_ADC_REG_RANK_3 2092 * @arg @ref LL_ADC_REG_RANK_4 2093 * @arg @ref LL_ADC_REG_RANK_5 2094 * @arg @ref LL_ADC_REG_RANK_6 2095 * @arg @ref LL_ADC_REG_RANK_7 2096 * @arg @ref LL_ADC_REG_RANK_8 2097 * @arg @ref LL_ADC_REG_RANK_9 2098 * @arg @ref LL_ADC_REG_RANK_10 2099 * @arg @ref LL_ADC_REG_RANK_11 2100 * @arg @ref LL_ADC_REG_RANK_12 2101 * @arg @ref LL_ADC_REG_RANK_13 2102 * @arg @ref LL_ADC_REG_RANK_14 2103 * @arg @ref LL_ADC_REG_RANK_15 2104 * @arg @ref LL_ADC_REG_RANK_16 2105 * @param Channel This parameter can be one of the following values: 2106 * @arg @ref LL_ADC_CHANNEL_0 2107 * @arg @ref LL_ADC_CHANNEL_1 2108 * @arg @ref LL_ADC_CHANNEL_2 2109 * @arg @ref LL_ADC_CHANNEL_3 2110 * @arg @ref LL_ADC_CHANNEL_4 2111 * @arg @ref LL_ADC_CHANNEL_5 2112 * @arg @ref LL_ADC_CHANNEL_6 2113 * @arg @ref LL_ADC_CHANNEL_7 2114 * @arg @ref LL_ADC_CHANNEL_8 2115 * @arg @ref LL_ADC_CHANNEL_9 2116 * @arg @ref LL_ADC_CHANNEL_10 2117 * @arg @ref LL_ADC_CHANNEL_11 2118 * @arg @ref LL_ADC_CHANNEL_12 2119 * @arg @ref LL_ADC_CHANNEL_13 2120 * @arg @ref LL_ADC_CHANNEL_14 2121 * @arg @ref LL_ADC_CHANNEL_15 2122 * @arg @ref LL_ADC_CHANNEL_16 2123 * @arg @ref LL_ADC_CHANNEL_17 2124 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2125 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 2126 * 2127 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 2128 * @retval None 2129 */ 2130 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 2131 { 2132 /* Set bits with content of parameter "Channel" with bits position */ 2133 /* in register and register position depending on parameter "Rank". */ 2134 /* Parameters "Rank" and "Channel" are used with masks because containing */ 2135 /* other bits reserved for other purpose. */ 2136 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 2137 2138 MODIFY_REG(*preg, 2139 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), 2140 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); 2141 } 2142 2143 /** 2144 * @brief Get ADC group regular sequence: channel on the selected 2145 * scan sequence rank. 2146 * @note On this STM32 series, ADC group regular sequencer is 2147 * fully configurable: sequencer length and each rank 2148 * affectation to a channel are configurable. 2149 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). 2150 * @note Depending on devices and packages, some channels may not be available. 2151 * Refer to device datasheet for channels availability. 2152 * @note Usage of the returned channel number: 2153 * - To reinject this channel into another function LL_ADC_xxx: 2154 * the returned channel number is only partly formatted on definition 2155 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 2156 * with parts of literals LL_ADC_CHANNEL_x or using 2157 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 2158 * Then the selected literal LL_ADC_CHANNEL_x can be used 2159 * as parameter for another function. 2160 * - To get the channel number in decimal format: 2161 * process the returned value with the helper macro 2162 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 2163 * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n 2164 * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n 2165 * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n 2166 * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n 2167 * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n 2168 * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n 2169 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n 2170 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n 2171 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n 2172 * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n 2173 * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n 2174 * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n 2175 * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n 2176 * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n 2177 * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n 2178 * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks 2179 * @param ADCx ADC instance 2180 * @param Rank This parameter can be one of the following values: 2181 * @arg @ref LL_ADC_REG_RANK_1 2182 * @arg @ref LL_ADC_REG_RANK_2 2183 * @arg @ref LL_ADC_REG_RANK_3 2184 * @arg @ref LL_ADC_REG_RANK_4 2185 * @arg @ref LL_ADC_REG_RANK_5 2186 * @arg @ref LL_ADC_REG_RANK_6 2187 * @arg @ref LL_ADC_REG_RANK_7 2188 * @arg @ref LL_ADC_REG_RANK_8 2189 * @arg @ref LL_ADC_REG_RANK_9 2190 * @arg @ref LL_ADC_REG_RANK_10 2191 * @arg @ref LL_ADC_REG_RANK_11 2192 * @arg @ref LL_ADC_REG_RANK_12 2193 * @arg @ref LL_ADC_REG_RANK_13 2194 * @arg @ref LL_ADC_REG_RANK_14 2195 * @arg @ref LL_ADC_REG_RANK_15 2196 * @arg @ref LL_ADC_REG_RANK_16 2197 * @retval Returned value can be one of the following values: 2198 * @arg @ref LL_ADC_CHANNEL_0 2199 * @arg @ref LL_ADC_CHANNEL_1 2200 * @arg @ref LL_ADC_CHANNEL_2 2201 * @arg @ref LL_ADC_CHANNEL_3 2202 * @arg @ref LL_ADC_CHANNEL_4 2203 * @arg @ref LL_ADC_CHANNEL_5 2204 * @arg @ref LL_ADC_CHANNEL_6 2205 * @arg @ref LL_ADC_CHANNEL_7 2206 * @arg @ref LL_ADC_CHANNEL_8 2207 * @arg @ref LL_ADC_CHANNEL_9 2208 * @arg @ref LL_ADC_CHANNEL_10 2209 * @arg @ref LL_ADC_CHANNEL_11 2210 * @arg @ref LL_ADC_CHANNEL_12 2211 * @arg @ref LL_ADC_CHANNEL_13 2212 * @arg @ref LL_ADC_CHANNEL_14 2213 * @arg @ref LL_ADC_CHANNEL_15 2214 * @arg @ref LL_ADC_CHANNEL_16 2215 * @arg @ref LL_ADC_CHANNEL_17 2216 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2217 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 2218 * 2219 * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n 2220 * (1) For ADC channel read back from ADC register, 2221 * comparison with internal channel parameter to be done 2222 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 2223 */ 2224 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 2225 { 2226 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); 2227 2228 return (uint32_t) (READ_BIT(*preg, 2229 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) 2230 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) 2231 ); 2232 } 2233 2234 /** 2235 * @brief Set ADC continuous conversion mode on ADC group regular. 2236 * @note Description of ADC continuous conversion mode: 2237 * - single mode: one conversion per trigger 2238 * - continuous mode: after the first trigger, following 2239 * conversions launched successively automatically. 2240 * @note It is not possible to enable both ADC group regular 2241 * continuous mode and sequencer discontinuous mode. 2242 * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode 2243 * @param ADCx ADC instance 2244 * @param Continuous This parameter can be one of the following values: 2245 * @arg @ref LL_ADC_REG_CONV_SINGLE 2246 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 2247 * @retval None 2248 */ 2249 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) 2250 { 2251 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); 2252 } 2253 2254 /** 2255 * @brief Get ADC continuous conversion mode on ADC group regular. 2256 * @note Description of ADC continuous conversion mode: 2257 * - single mode: one conversion per trigger 2258 * - continuous mode: after the first trigger, following 2259 * conversions launched successively automatically. 2260 * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode 2261 * @param ADCx ADC instance 2262 * @retval Returned value can be one of the following values: 2263 * @arg @ref LL_ADC_REG_CONV_SINGLE 2264 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS 2265 */ 2266 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) 2267 { 2268 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); 2269 } 2270 2271 /** 2272 * @brief Set ADC group regular conversion data transfer: no transfer or 2273 * transfer by DMA, and DMA requests mode. 2274 * @note If transfer by DMA selected, specifies the DMA requests 2275 * mode: 2276 * - Limited mode (One shot mode): DMA transfer requests are stopped 2277 * when number of DMA data transfers (number of 2278 * ADC conversions) is reached. 2279 * This ADC mode is intended to be used with DMA mode non-circular. 2280 * - Unlimited mode: DMA transfer requests are unlimited, 2281 * whatever number of DMA data transfers (number of 2282 * ADC conversions). 2283 * This ADC mode is intended to be used with DMA mode circular. 2284 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 2285 * mode non-circular: 2286 * when DMA transfers size will be reached, DMA will stop transfers of 2287 * ADC conversions data ADC will raise an overrun error 2288 * (overrun flag and interruption if enabled). 2289 * @note To configure DMA source address (peripheral address), 2290 * use function @ref LL_ADC_DMA_GetRegAddr(). 2291 * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer 2292 * @param ADCx ADC instance 2293 * @param DMATransfer This parameter can be one of the following values: 2294 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 2295 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 2296 * @retval None 2297 */ 2298 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) 2299 { 2300 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer); 2301 } 2302 2303 /** 2304 * @brief Get ADC group regular conversion data transfer: no transfer or 2305 * transfer by DMA, and DMA requests mode. 2306 * @note If transfer by DMA selected, specifies the DMA requests 2307 * mode: 2308 * - Limited mode (One shot mode): DMA transfer requests are stopped 2309 * when number of DMA data transfers (number of 2310 * ADC conversions) is reached. 2311 * This ADC mode is intended to be used with DMA mode non-circular. 2312 * - Unlimited mode: DMA transfer requests are unlimited, 2313 * whatever number of DMA data transfers (number of 2314 * ADC conversions). 2315 * This ADC mode is intended to be used with DMA mode circular. 2316 * @note If ADC DMA requests mode is set to unlimited and DMA is set to 2317 * mode non-circular: 2318 * when DMA transfers size will be reached, DMA will stop transfers of 2319 * ADC conversions data ADC will raise an overrun error 2320 * (overrun flag and interruption if enabled). 2321 * @note To configure DMA source address (peripheral address), 2322 * use function @ref LL_ADC_DMA_GetRegAddr(). 2323 * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer 2324 * @param ADCx ADC instance 2325 * @retval Returned value can be one of the following values: 2326 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE 2327 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED 2328 */ 2329 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) 2330 { 2331 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA)); 2332 } 2333 2334 /** 2335 * @} 2336 */ 2337 2338 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected 2339 * @{ 2340 */ 2341 2342 /** 2343 * @brief Set ADC group injected conversion trigger source: 2344 * internal (SW start) or from external IP (timer event, 2345 * external interrupt line). 2346 * @note On this STM32 series, external trigger is set with trigger polarity: 2347 * rising edge (only trigger polarity available on this STM32 series). 2348 * @note Availability of parameters of trigger sources from timer 2349 * depends on timers availability on the selected device. 2350 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource 2351 * @param ADCx ADC instance 2352 * @param TriggerSource This parameter can be one of the following values: 2353 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 2354 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) 2355 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) 2356 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) 2357 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) 2358 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) 2359 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) 2360 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) 2361 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) 2362 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) 2363 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) 2364 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) 2365 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) 2366 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) 2367 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) 2368 * 2369 * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n 2370 * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n 2371 * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n 2372 * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). 2373 * @retval None 2374 */ 2375 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) 2376 { 2377 /* Note: On this STM32 series, ADC group injected external trigger edge */ 2378 /* is used to perform a ADC conversion start. */ 2379 /* This function does not set external trigger edge. */ 2380 /* This feature is set using function */ 2381 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ 2382 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); 2383 } 2384 2385 /** 2386 * @brief Get ADC group injected conversion trigger source: 2387 * internal (SW start) or from external IP (timer event, 2388 * external interrupt line). 2389 * @note To determine whether group injected trigger source is 2390 * internal (SW start) or external, without detail 2391 * of which peripheral is selected as external trigger, 2392 * (equivalent to 2393 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") 2394 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. 2395 * @note Availability of parameters of trigger sources from timer 2396 * depends on timers availability on the selected device. 2397 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource 2398 * @param ADCx ADC instance 2399 * @retval Returned value can be one of the following values: 2400 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE 2401 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) 2402 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) 2403 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) 2404 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) 2405 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) 2406 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) 2407 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) 2408 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) 2409 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) 2410 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) 2411 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) 2412 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) 2413 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) 2414 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) 2415 * 2416 * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n 2417 * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n 2418 * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n 2419 * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). 2420 */ 2421 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) 2422 { 2423 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL)); 2424 } 2425 2426 /** 2427 * @brief Get ADC group injected conversion trigger source internal (SW start) 2428 or external 2429 * @note In case of group injected trigger source set to external trigger, 2430 * to determine which peripheral is selected as external trigger, 2431 * use function @ref LL_ADC_INJ_GetTriggerSource. 2432 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart 2433 * @param ADCx ADC instance 2434 * @retval Value "0" if trigger source external trigger 2435 * Value "1" if trigger source SW start. 2436 */ 2437 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) 2438 { 2439 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE); 2440 } 2441 2442 /** 2443 * @brief Set ADC group injected sequencer length and scan direction. 2444 * @note This function performs configuration of: 2445 * - Sequence length: Number of ranks in the scan sequence. 2446 * - Sequence direction: Unless specified in parameters, sequencer 2447 * scan direction is forward (from rank 1 to rank n). 2448 * @note On this STM32 series, group injected sequencer configuration 2449 * is conditioned to ADC instance sequencer mode. 2450 * If ADC instance sequencer mode is disabled, sequencers of 2451 * all groups (group regular, group injected) can be configured 2452 * but their execution is disabled (limited to rank 1). 2453 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 2454 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 2455 * ADC conversion on only 1 channel. 2456 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength 2457 * @param ADCx ADC instance 2458 * @param SequencerNbRanks This parameter can be one of the following values: 2459 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 2460 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 2461 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 2462 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 2463 * @retval None 2464 */ 2465 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) 2466 { 2467 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); 2468 } 2469 2470 /** 2471 * @brief Get ADC group injected sequencer length and scan direction. 2472 * @note This function retrieves: 2473 * - Sequence length: Number of ranks in the scan sequence. 2474 * - Sequence direction: Unless specified in parameters, sequencer 2475 * scan direction is forward (from rank 1 to rank n). 2476 * @note On this STM32 series, group injected sequencer configuration 2477 * is conditioned to ADC instance sequencer mode. 2478 * If ADC instance sequencer mode is disabled, sequencers of 2479 * all groups (group regular, group injected) can be configured 2480 * but their execution is disabled (limited to rank 1). 2481 * Refer to function @ref LL_ADC_SetSequencersScanMode(). 2482 * @note Sequencer disabled is equivalent to sequencer of 1 rank: 2483 * ADC conversion on only 1 channel. 2484 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength 2485 * @param ADCx ADC instance 2486 * @retval Returned value can be one of the following values: 2487 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE 2488 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS 2489 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS 2490 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS 2491 */ 2492 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) 2493 { 2494 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); 2495 } 2496 2497 /** 2498 * @brief Set ADC group injected sequencer discontinuous mode: 2499 * sequence subdivided and scan conversions interrupted every selected 2500 * number of ranks. 2501 * @note It is not possible to enable both ADC group injected 2502 * auto-injected mode and sequencer discontinuous mode. 2503 * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont 2504 * @param ADCx ADC instance 2505 * @param SeqDiscont This parameter can be one of the following values: 2506 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 2507 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 2508 * @retval None 2509 */ 2510 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) 2511 { 2512 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); 2513 } 2514 2515 /** 2516 * @brief Get ADC group injected sequencer discontinuous mode: 2517 * sequence subdivided and scan conversions interrupted every selected 2518 * number of ranks. 2519 * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont 2520 * @param ADCx ADC instance 2521 * @retval Returned value can be one of the following values: 2522 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE 2523 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK 2524 */ 2525 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) 2526 { 2527 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); 2528 } 2529 2530 /** 2531 * @brief Set ADC group injected sequence: channel on the selected 2532 * sequence rank. 2533 * @note Depending on devices and packages, some channels may not be available. 2534 * Refer to device datasheet for channels availability. 2535 * @note On this STM32 series, to measure internal channels (VrefInt, 2536 * TempSensor, ...), measurement paths to internal channels must be 2537 * enabled separately. 2538 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). 2539 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 2540 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 2541 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 2542 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 2543 * @param ADCx ADC instance 2544 * @param Rank This parameter can be one of the following values: 2545 * @arg @ref LL_ADC_INJ_RANK_1 2546 * @arg @ref LL_ADC_INJ_RANK_2 2547 * @arg @ref LL_ADC_INJ_RANK_3 2548 * @arg @ref LL_ADC_INJ_RANK_4 2549 * @param Channel This parameter can be one of the following values: 2550 * @arg @ref LL_ADC_CHANNEL_0 2551 * @arg @ref LL_ADC_CHANNEL_1 2552 * @arg @ref LL_ADC_CHANNEL_2 2553 * @arg @ref LL_ADC_CHANNEL_3 2554 * @arg @ref LL_ADC_CHANNEL_4 2555 * @arg @ref LL_ADC_CHANNEL_5 2556 * @arg @ref LL_ADC_CHANNEL_6 2557 * @arg @ref LL_ADC_CHANNEL_7 2558 * @arg @ref LL_ADC_CHANNEL_8 2559 * @arg @ref LL_ADC_CHANNEL_9 2560 * @arg @ref LL_ADC_CHANNEL_10 2561 * @arg @ref LL_ADC_CHANNEL_11 2562 * @arg @ref LL_ADC_CHANNEL_12 2563 * @arg @ref LL_ADC_CHANNEL_13 2564 * @arg @ref LL_ADC_CHANNEL_14 2565 * @arg @ref LL_ADC_CHANNEL_15 2566 * @arg @ref LL_ADC_CHANNEL_16 2567 * @arg @ref LL_ADC_CHANNEL_17 2568 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2569 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 2570 * 2571 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 2572 * @retval None 2573 */ 2574 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) 2575 { 2576 /* Set bits with content of parameter "Channel" with bits position */ 2577 /* in register depending on parameter "Rank". */ 2578 /* Parameters "Rank" and "Channel" are used with masks because containing */ 2579 /* other bits reserved for other purpose. */ 2580 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; 2581 2582 MODIFY_REG(ADCx->JSQR, 2583 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), 2584 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); 2585 } 2586 2587 /** 2588 * @brief Get ADC group injected sequence: channel on the selected 2589 * sequence rank. 2590 * @note Depending on devices and packages, some channels may not be available. 2591 * Refer to device datasheet for channels availability. 2592 * @note Usage of the returned channel number: 2593 * - To reinject this channel into another function LL_ADC_xxx: 2594 * the returned channel number is only partly formatted on definition 2595 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 2596 * with parts of literals LL_ADC_CHANNEL_x or using 2597 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 2598 * Then the selected literal LL_ADC_CHANNEL_x can be used 2599 * as parameter for another function. 2600 * - To get the channel number in decimal format: 2601 * process the returned value with the helper macro 2602 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 2603 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n 2604 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n 2605 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n 2606 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks 2607 * @param ADCx ADC instance 2608 * @param Rank This parameter can be one of the following values: 2609 * @arg @ref LL_ADC_INJ_RANK_1 2610 * @arg @ref LL_ADC_INJ_RANK_2 2611 * @arg @ref LL_ADC_INJ_RANK_3 2612 * @arg @ref LL_ADC_INJ_RANK_4 2613 * @retval Returned value can be one of the following values: 2614 * @arg @ref LL_ADC_CHANNEL_0 2615 * @arg @ref LL_ADC_CHANNEL_1 2616 * @arg @ref LL_ADC_CHANNEL_2 2617 * @arg @ref LL_ADC_CHANNEL_3 2618 * @arg @ref LL_ADC_CHANNEL_4 2619 * @arg @ref LL_ADC_CHANNEL_5 2620 * @arg @ref LL_ADC_CHANNEL_6 2621 * @arg @ref LL_ADC_CHANNEL_7 2622 * @arg @ref LL_ADC_CHANNEL_8 2623 * @arg @ref LL_ADC_CHANNEL_9 2624 * @arg @ref LL_ADC_CHANNEL_10 2625 * @arg @ref LL_ADC_CHANNEL_11 2626 * @arg @ref LL_ADC_CHANNEL_12 2627 * @arg @ref LL_ADC_CHANNEL_13 2628 * @arg @ref LL_ADC_CHANNEL_14 2629 * @arg @ref LL_ADC_CHANNEL_15 2630 * @arg @ref LL_ADC_CHANNEL_16 2631 * @arg @ref LL_ADC_CHANNEL_17 2632 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2633 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 2634 * 2635 * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n 2636 * (1) For ADC channel read back from ADC register, 2637 * comparison with internal channel parameter to be done 2638 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 2639 */ 2640 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) 2641 { 2642 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; 2643 2644 return (uint32_t)(READ_BIT(ADCx->JSQR, 2645 ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) 2646 >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) 2647 ); 2648 } 2649 2650 /** 2651 * @brief Set ADC group injected conversion trigger: 2652 * independent or from ADC group regular. 2653 * @note This mode can be used to extend number of data registers 2654 * updated after one ADC conversion trigger and with data 2655 * permanently kept (not erased by successive conversions of scan of 2656 * ADC sequencer ranks), up to 5 data registers: 2657 * 1 data register on ADC group regular, 4 data registers 2658 * on ADC group injected. 2659 * @note If ADC group injected injected trigger source is set to an 2660 * external trigger, this feature must be must be set to 2661 * independent trigger. 2662 * ADC group injected automatic trigger is compliant only with 2663 * group injected trigger source set to SW start, without any 2664 * further action on ADC group injected conversion start or stop: 2665 * in this case, ADC group injected is controlled only 2666 * from ADC group regular. 2667 * @note It is not possible to enable both ADC group injected 2668 * auto-injected mode and sequencer discontinuous mode. 2669 * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto 2670 * @param ADCx ADC instance 2671 * @param TrigAuto This parameter can be one of the following values: 2672 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 2673 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 2674 * @retval None 2675 */ 2676 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) 2677 { 2678 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); 2679 } 2680 2681 /** 2682 * @brief Get ADC group injected conversion trigger: 2683 * independent or from ADC group regular. 2684 * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto 2685 * @param ADCx ADC instance 2686 * @retval Returned value can be one of the following values: 2687 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT 2688 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR 2689 */ 2690 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) 2691 { 2692 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); 2693 } 2694 2695 /** 2696 * @brief Set ADC group injected offset. 2697 * @note It sets: 2698 * - ADC group injected rank to which the offset programmed 2699 * will be applied 2700 * - Offset level (offset to be subtracted from the raw 2701 * converted data). 2702 * Caution: Offset format is dependent to ADC resolution: 2703 * offset has to be left-aligned on bit 11, the LSB (right bits) 2704 * are set to 0. 2705 * @note Offset cannot be enabled or disabled. 2706 * To emulate offset disabled, set an offset value equal to 0. 2707 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n 2708 * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n 2709 * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n 2710 * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset 2711 * @param ADCx ADC instance 2712 * @param Rank This parameter can be one of the following values: 2713 * @arg @ref LL_ADC_INJ_RANK_1 2714 * @arg @ref LL_ADC_INJ_RANK_2 2715 * @arg @ref LL_ADC_INJ_RANK_3 2716 * @arg @ref LL_ADC_INJ_RANK_4 2717 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF 2718 * @retval None 2719 */ 2720 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) 2721 { 2722 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 2723 2724 MODIFY_REG(*preg, 2725 ADC_JOFR1_JOFFSET1, 2726 OffsetLevel); 2727 } 2728 2729 /** 2730 * @brief Get ADC group injected offset. 2731 * @note It gives offset level (offset to be subtracted from the raw converted data). 2732 * Caution: Offset format is dependent to ADC resolution: 2733 * offset has to be left-aligned on bit 11, the LSB (right bits) 2734 * are set to 0. 2735 * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n 2736 * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n 2737 * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n 2738 * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset 2739 * @param ADCx ADC instance 2740 * @param Rank This parameter can be one of the following values: 2741 * @arg @ref LL_ADC_INJ_RANK_1 2742 * @arg @ref LL_ADC_INJ_RANK_2 2743 * @arg @ref LL_ADC_INJ_RANK_3 2744 * @arg @ref LL_ADC_INJ_RANK_4 2745 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 2746 */ 2747 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) 2748 { 2749 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); 2750 2751 return (uint32_t)(READ_BIT(*preg, 2752 ADC_JOFR1_JOFFSET1) 2753 ); 2754 } 2755 2756 /** 2757 * @} 2758 */ 2759 2760 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels 2761 * @{ 2762 */ 2763 2764 /** 2765 * @brief Set sampling time of the selected ADC channel 2766 * Unit: ADC clock cycles. 2767 * @note On this device, sampling time is on channel scope: independently 2768 * of channel mapped on ADC group regular or injected. 2769 * @note In case of internal channel (VrefInt, TempSensor, ...) to be 2770 * converted: 2771 * sampling time constraints must be respected (sampling time can be 2772 * adjusted in function of ADC clock frequency and sampling time 2773 * setting). 2774 * Refer to device datasheet for timings values (parameters TS_vrefint, 2775 * TS_temp, ...). 2776 * @note Conversion time is the addition of sampling time and processing time. 2777 * Refer to reference manual for ADC processing time of 2778 * this STM32 series. 2779 * @note In case of ADC conversion of internal channel (VrefInt, 2780 * temperature sensor, ...), a sampling time minimum value 2781 * is required. 2782 * Refer to device datasheet. 2783 * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n 2784 * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n 2785 * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n 2786 * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n 2787 * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n 2788 * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n 2789 * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n 2790 * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n 2791 * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n 2792 * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n 2793 * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n 2794 * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n 2795 * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n 2796 * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n 2797 * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n 2798 * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n 2799 * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n 2800 * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime 2801 * @param ADCx ADC instance 2802 * @param Channel This parameter can be one of the following values: 2803 * @arg @ref LL_ADC_CHANNEL_0 2804 * @arg @ref LL_ADC_CHANNEL_1 2805 * @arg @ref LL_ADC_CHANNEL_2 2806 * @arg @ref LL_ADC_CHANNEL_3 2807 * @arg @ref LL_ADC_CHANNEL_4 2808 * @arg @ref LL_ADC_CHANNEL_5 2809 * @arg @ref LL_ADC_CHANNEL_6 2810 * @arg @ref LL_ADC_CHANNEL_7 2811 * @arg @ref LL_ADC_CHANNEL_8 2812 * @arg @ref LL_ADC_CHANNEL_9 2813 * @arg @ref LL_ADC_CHANNEL_10 2814 * @arg @ref LL_ADC_CHANNEL_11 2815 * @arg @ref LL_ADC_CHANNEL_12 2816 * @arg @ref LL_ADC_CHANNEL_13 2817 * @arg @ref LL_ADC_CHANNEL_14 2818 * @arg @ref LL_ADC_CHANNEL_15 2819 * @arg @ref LL_ADC_CHANNEL_16 2820 * @arg @ref LL_ADC_CHANNEL_17 2821 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2822 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 2823 * 2824 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 2825 * @param SamplingTime This parameter can be one of the following values: 2826 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 2827 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 2828 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 2829 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 2830 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 2831 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 2832 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 2833 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 2834 * @retval None 2835 */ 2836 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) 2837 { 2838 /* Set bits with content of parameter "SamplingTime" with bits position */ 2839 /* in register and register position depending on parameter "Channel". */ 2840 /* Parameter "Channel" is used with masks because containing */ 2841 /* other bits reserved for other purpose. */ 2842 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 2843 2844 MODIFY_REG(*preg, 2845 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), 2846 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); 2847 } 2848 2849 /** 2850 * @brief Get sampling time of the selected ADC channel 2851 * Unit: ADC clock cycles. 2852 * @note On this device, sampling time is on channel scope: independently 2853 * of channel mapped on ADC group regular or injected. 2854 * @note Conversion time is the addition of sampling time and processing time. 2855 * Refer to reference manual for ADC processing time of 2856 * this STM32 series. 2857 * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n 2858 * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n 2859 * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n 2860 * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n 2861 * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n 2862 * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n 2863 * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n 2864 * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n 2865 * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n 2866 * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n 2867 * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n 2868 * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n 2869 * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n 2870 * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n 2871 * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n 2872 * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n 2873 * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n 2874 * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime 2875 * @param ADCx ADC instance 2876 * @param Channel This parameter can be one of the following values: 2877 * @arg @ref LL_ADC_CHANNEL_0 2878 * @arg @ref LL_ADC_CHANNEL_1 2879 * @arg @ref LL_ADC_CHANNEL_2 2880 * @arg @ref LL_ADC_CHANNEL_3 2881 * @arg @ref LL_ADC_CHANNEL_4 2882 * @arg @ref LL_ADC_CHANNEL_5 2883 * @arg @ref LL_ADC_CHANNEL_6 2884 * @arg @ref LL_ADC_CHANNEL_7 2885 * @arg @ref LL_ADC_CHANNEL_8 2886 * @arg @ref LL_ADC_CHANNEL_9 2887 * @arg @ref LL_ADC_CHANNEL_10 2888 * @arg @ref LL_ADC_CHANNEL_11 2889 * @arg @ref LL_ADC_CHANNEL_12 2890 * @arg @ref LL_ADC_CHANNEL_13 2891 * @arg @ref LL_ADC_CHANNEL_14 2892 * @arg @ref LL_ADC_CHANNEL_15 2893 * @arg @ref LL_ADC_CHANNEL_16 2894 * @arg @ref LL_ADC_CHANNEL_17 2895 * @arg @ref LL_ADC_CHANNEL_VREFINT (1) 2896 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) 2897 * 2898 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 2899 * @retval Returned value can be one of the following values: 2900 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 2901 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 2902 * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 2903 * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 2904 * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 2905 * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 2906 * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 2907 * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 2908 */ 2909 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) 2910 { 2911 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); 2912 2913 return (uint32_t)(READ_BIT(*preg, 2914 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) 2915 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) 2916 ); 2917 } 2918 2919 /** 2920 * @} 2921 */ 2922 2923 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog 2924 * @{ 2925 */ 2926 2927 /** 2928 * @brief Set ADC analog watchdog monitored channels: 2929 * a single channel or all channels, 2930 * on ADC groups regular and-or injected. 2931 * @note Once monitored channels are selected, analog watchdog 2932 * is enabled. 2933 * @note In case of need to define a single channel to monitor 2934 * with analog watchdog from sequencer channel definition, 2935 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). 2936 * @note On this STM32 series, there is only 1 kind of analog watchdog 2937 * instance: 2938 * - AWD standard (instance AWD1): 2939 * - channels monitored: can monitor 1 channel or all channels. 2940 * - groups monitored: ADC groups regular and-or injected. 2941 * - resolution: resolution is not limited (corresponds to 2942 * ADC resolution configured). 2943 * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n 2944 * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n 2945 * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels 2946 * @param ADCx ADC instance 2947 * @param AWDChannelGroup This parameter can be one of the following values: 2948 * @arg @ref LL_ADC_AWD_DISABLE 2949 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 2950 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 2951 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 2952 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 2953 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 2954 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 2955 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 2956 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 2957 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 2958 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 2959 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 2960 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 2961 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 2962 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 2963 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 2964 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 2965 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 2966 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 2967 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 2968 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 2969 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 2970 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 2971 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 2972 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 2973 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 2974 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 2975 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 2976 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 2977 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 2978 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 2979 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 2980 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 2981 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 2982 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 2983 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 2984 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 2985 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 2986 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 2987 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 2988 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 2989 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 2990 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 2991 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 2992 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 2993 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 2994 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 2995 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 2996 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 2997 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 2998 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 2999 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 3000 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 3001 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 3002 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 3003 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 3004 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 3005 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 3006 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) 3007 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) 3008 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) 3009 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) 3010 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) 3011 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) 3012 * 3013 * (1) On STM32F1, parameter available only on ADC instance: ADC1. 3014 * @retval None 3015 */ 3016 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) 3017 { 3018 MODIFY_REG(ADCx->CR1, 3019 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), 3020 AWDChannelGroup); 3021 } 3022 3023 /** 3024 * @brief Get ADC analog watchdog monitored channel. 3025 * @note Usage of the returned channel number: 3026 * - To reinject this channel into another function LL_ADC_xxx: 3027 * the returned channel number is only partly formatted on definition 3028 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared 3029 * with parts of literals LL_ADC_CHANNEL_x or using 3030 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 3031 * Then the selected literal LL_ADC_CHANNEL_x can be used 3032 * as parameter for another function. 3033 * - To get the channel number in decimal format: 3034 * process the returned value with the helper macro 3035 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). 3036 * Applicable only when the analog watchdog is set to monitor 3037 * one channel. 3038 * @note On this STM32 series, there is only 1 kind of analog watchdog 3039 * instance: 3040 * - AWD standard (instance AWD1): 3041 * - channels monitored: can monitor 1 channel or all channels. 3042 * - groups monitored: ADC groups regular and-or injected. 3043 * - resolution: resolution is not limited (corresponds to 3044 * ADC resolution configured). 3045 * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n 3046 * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n 3047 * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels 3048 * @param ADCx ADC instance 3049 * @retval Returned value can be one of the following values: 3050 * @arg @ref LL_ADC_AWD_DISABLE 3051 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG 3052 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ 3053 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ 3054 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG 3055 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ 3056 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ 3057 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG 3058 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ 3059 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ 3060 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG 3061 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ 3062 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ 3063 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG 3064 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ 3065 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ 3066 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG 3067 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ 3068 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ 3069 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG 3070 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ 3071 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ 3072 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG 3073 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ 3074 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ 3075 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG 3076 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ 3077 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ 3078 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG 3079 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ 3080 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ 3081 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG 3082 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ 3083 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ 3084 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG 3085 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ 3086 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ 3087 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG 3088 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ 3089 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ 3090 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG 3091 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ 3092 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ 3093 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG 3094 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ 3095 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ 3096 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG 3097 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ 3098 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ 3099 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG 3100 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ 3101 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ 3102 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG 3103 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ 3104 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ 3105 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG 3106 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ 3107 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ 3108 */ 3109 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) 3110 { 3111 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); 3112 } 3113 3114 /** 3115 * @brief Set ADC analog watchdog threshold value of threshold 3116 * high or low. 3117 * @note On this STM32 series, there is only 1 kind of analog watchdog 3118 * instance: 3119 * - AWD standard (instance AWD1): 3120 * - channels monitored: can monitor 1 channel or all channels. 3121 * - groups monitored: ADC groups regular and-or injected. 3122 * - resolution: resolution is not limited (corresponds to 3123 * ADC resolution configured). 3124 * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n 3125 * LTR LT LL_ADC_SetAnalogWDThresholds 3126 * @param ADCx ADC instance 3127 * @param AWDThresholdsHighLow This parameter can be one of the following values: 3128 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 3129 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 3130 * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF 3131 * @retval None 3132 */ 3133 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) 3134 { 3135 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 3136 3137 MODIFY_REG(*preg, 3138 ADC_HTR_HT, 3139 AWDThresholdValue); 3140 } 3141 3142 /** 3143 * @brief Get ADC analog watchdog threshold value of threshold high or 3144 * threshold low. 3145 * @note In case of ADC resolution different of 12 bits, 3146 * analog watchdog thresholds data require a specific shift. 3147 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). 3148 * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n 3149 * LTR LT LL_ADC_GetAnalogWDThresholds 3150 * @param ADCx ADC instance 3151 * @param AWDThresholdsHighLow This parameter can be one of the following values: 3152 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH 3153 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW 3154 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 3155 */ 3156 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) 3157 { 3158 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); 3159 3160 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); 3161 } 3162 3163 /** 3164 * @} 3165 */ 3166 3167 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode 3168 * @{ 3169 */ 3170 3171 #if defined(ADC_MULTIMODE_SUPPORT) 3172 /** 3173 * @brief Set ADC multimode configuration to operate in independent mode 3174 * or multimode (for devices with several ADC instances). 3175 * @note If multimode configuration: the selected ADC instance is 3176 * either master or slave depending on hardware. 3177 * Refer to reference manual. 3178 * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode 3179 * @param ADCxy_COMMON ADC common instance 3180 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3181 * @param Multimode This parameter can be one of the following values: 3182 * @arg @ref LL_ADC_MULTI_INDEPENDENT 3183 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 3184 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST 3185 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW 3186 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 3187 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 3188 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 3189 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 3190 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM 3191 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM 3192 * @retval None 3193 */ 3194 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) 3195 { 3196 MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode); 3197 } 3198 3199 /** 3200 * @brief Get ADC multimode configuration to operate in independent mode 3201 * or multimode (for devices with several ADC instances). 3202 * @note If multimode configuration: the selected ADC instance is 3203 * either master or slave depending on hardware. 3204 * Refer to reference manual. 3205 * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode 3206 * @param ADCxy_COMMON ADC common instance 3207 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3208 * @retval Returned value can be one of the following values: 3209 * @arg @ref LL_ADC_MULTI_INDEPENDENT 3210 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT 3211 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST 3212 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW 3213 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT 3214 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN 3215 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM 3216 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT 3217 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM 3218 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM 3219 */ 3220 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) 3221 { 3222 return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD)); 3223 } 3224 3225 #endif /* ADC_MULTIMODE_SUPPORT */ 3226 3227 /** 3228 * @} 3229 */ 3230 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance 3231 * @{ 3232 */ 3233 3234 /** 3235 * @brief Enable the selected ADC instance. 3236 * @note On this STM32 series, after ADC enable, a delay for 3237 * ADC internal analog stabilization is required before performing a 3238 * ADC conversion start. 3239 * Refer to device datasheet, parameter tSTAB. 3240 * @rmtoll CR2 ADON LL_ADC_Enable 3241 * @param ADCx ADC instance 3242 * @retval None 3243 */ 3244 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) 3245 { 3246 SET_BIT(ADCx->CR2, ADC_CR2_ADON); 3247 } 3248 3249 /** 3250 * @brief Disable the selected ADC instance. 3251 * @rmtoll CR2 ADON LL_ADC_Disable 3252 * @param ADCx ADC instance 3253 * @retval None 3254 */ 3255 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) 3256 { 3257 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); 3258 } 3259 3260 /** 3261 * @brief Get the selected ADC instance enable state. 3262 * @rmtoll CR2 ADON LL_ADC_IsEnabled 3263 * @param ADCx ADC instance 3264 * @retval 0: ADC is disabled, 1: ADC is enabled. 3265 */ 3266 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) 3267 { 3268 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); 3269 } 3270 3271 /** 3272 * @brief Start ADC calibration in the mode single-ended 3273 * or differential (for devices with differential mode available). 3274 * @note On this STM32 series, before starting a calibration, 3275 * ADC must be disabled. 3276 * A minimum number of ADC clock cycles are required 3277 * between ADC disable state and calibration start. 3278 * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES. 3279 * @note On this STM32 series, hardware prerequisite before starting a calibration: 3280 the ADC must have been in power-on state for at least 3281 two ADC clock cycles. 3282 * @rmtoll CR2 CAL LL_ADC_StartCalibration 3283 * @param ADCx ADC instance 3284 * @retval None 3285 */ 3286 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) 3287 { 3288 SET_BIT(ADCx->CR2, ADC_CR2_CAL); 3289 } 3290 3291 /** 3292 * @brief Get ADC calibration state. 3293 * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing 3294 * @param ADCx ADC instance 3295 * @retval 0: calibration complete, 1: calibration in progress. 3296 */ 3297 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) 3298 { 3299 return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL)); 3300 } 3301 3302 /** 3303 * @} 3304 */ 3305 3306 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular 3307 * @{ 3308 */ 3309 3310 /** 3311 * @brief Start ADC group regular conversion. 3312 * @note On this STM32 series, this function is relevant only for 3313 * internal trigger (SW start), not for external trigger: 3314 * - If ADC trigger has been set to software start, ADC conversion 3315 * starts immediately. 3316 * - If ADC trigger has been set to external trigger, ADC conversion 3317 * start must be performed using function 3318 * @ref LL_ADC_REG_StartConversionExtTrig(). 3319 * (if external trigger edge would have been set during ADC other 3320 * settings, ADC conversion would start at trigger event 3321 * as soon as ADC is enabled). 3322 * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart 3323 * @param ADCx ADC instance 3324 * @retval None 3325 */ 3326 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) 3327 { 3328 SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); 3329 } 3330 3331 /** 3332 * @brief Start ADC group regular conversion from external trigger. 3333 * @note ADC conversion will start at next trigger event (on the selected 3334 * trigger edge) following the ADC start conversion command. 3335 * @note On this STM32 series, this function is relevant for 3336 * ADC conversion start from external trigger. 3337 * If internal trigger (SW start) is needed, perform ADC conversion 3338 * start using function @ref LL_ADC_REG_StartConversionSWStart(). 3339 * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig 3340 * @param ExternalTriggerEdge This parameter can be one of the following values: 3341 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING 3342 * @param ADCx ADC instance 3343 * @retval None 3344 */ 3345 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 3346 { 3347 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 3348 } 3349 3350 /** 3351 * @brief Stop ADC group regular conversion from external trigger. 3352 * @note No more ADC conversion will start at next trigger event 3353 * following the ADC stop conversion command. 3354 * If a conversion is on-going, it will be completed. 3355 * @note On this STM32 series, there is no specific command 3356 * to stop a conversion on-going or to stop ADC converting 3357 * in continuous mode. These actions can be performed 3358 * using function @ref LL_ADC_Disable(). 3359 * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig 3360 * @param ADCx ADC instance 3361 * @retval None 3362 */ 3363 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) 3364 { 3365 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTTRIG); 3366 } 3367 3368 /** 3369 * @brief Get ADC group regular conversion data, range fit for 3370 * all ADC configurations: all ADC resolutions and 3371 * all oversampling increased data width (for devices 3372 * with feature oversampling). 3373 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 3374 * @param ADCx ADC instance 3375 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 3376 */ 3377 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) 3378 { 3379 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 3380 } 3381 3382 /** 3383 * @brief Get ADC group regular conversion data, range fit for 3384 * ADC resolution 12 bits. 3385 * @note For devices with feature oversampling: Oversampling 3386 * can increase data width, function for extended range 3387 * may be needed: @ref LL_ADC_REG_ReadConversionData32. 3388 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 3389 * @param ADCx ADC instance 3390 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 3391 */ 3392 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) 3393 { 3394 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); 3395 } 3396 3397 #if defined(ADC_MULTIMODE_SUPPORT) 3398 /** 3399 * @brief Get ADC multimode conversion data of ADC master, ADC slave 3400 * or raw data with ADC master and slave concatenated. 3401 * @note If raw data with ADC master and slave concatenated is retrieved, 3402 * a macro is available to get the conversion data of 3403 * ADC master or ADC slave: see helper macro 3404 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). 3405 * (however this macro is mainly intended for multimode 3406 * transfer by DMA, because this function can do the same 3407 * by getting multimode conversion data of ADC master or ADC slave 3408 * separately). 3409 * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n 3410 * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32 3411 * @param ADCx ADC instance 3412 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3413 * @param ConversionData This parameter can be one of the following values: 3414 * @arg @ref LL_ADC_MULTI_MASTER 3415 * @arg @ref LL_ADC_MULTI_SLAVE 3416 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE 3417 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 3418 */ 3419 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData) 3420 { 3421 return (uint32_t)(READ_BIT(ADCx->DR, 3422 ADC_DR_ADC2DATA) 3423 >> POSITION_VAL(ConversionData) 3424 ); 3425 } 3426 #endif /* ADC_MULTIMODE_SUPPORT */ 3427 3428 /** 3429 * @} 3430 */ 3431 3432 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected 3433 * @{ 3434 */ 3435 3436 /** 3437 * @brief Start ADC group injected conversion. 3438 * @note On this STM32 series, this function is relevant only for 3439 * internal trigger (SW start), not for external trigger: 3440 * - If ADC trigger has been set to software start, ADC conversion 3441 * starts immediately. 3442 * - If ADC trigger has been set to external trigger, ADC conversion 3443 * start must be performed using function 3444 * @ref LL_ADC_INJ_StartConversionExtTrig(). 3445 * (if external trigger edge would have been set during ADC other 3446 * settings, ADC conversion would start at trigger event 3447 * as soon as ADC is enabled). 3448 * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart 3449 * @param ADCx ADC instance 3450 * @retval None 3451 */ 3452 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) 3453 { 3454 SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); 3455 } 3456 3457 /** 3458 * @brief Start ADC group injected conversion from external trigger. 3459 * @note ADC conversion will start at next trigger event (on the selected 3460 * trigger edge) following the ADC start conversion command. 3461 * @note On this STM32 series, this function is relevant for 3462 * ADC conversion start from external trigger. 3463 * If internal trigger (SW start) is needed, perform ADC conversion 3464 * start using function @ref LL_ADC_INJ_StartConversionSWStart(). 3465 * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig 3466 * @param ExternalTriggerEdge This parameter can be one of the following values: 3467 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING 3468 * @param ADCx ADC instance 3469 * @retval None 3470 */ 3471 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) 3472 { 3473 SET_BIT(ADCx->CR2, ExternalTriggerEdge); 3474 } 3475 3476 /** 3477 * @brief Stop ADC group injected conversion from external trigger. 3478 * @note No more ADC conversion will start at next trigger event 3479 * following the ADC stop conversion command. 3480 * If a conversion is on-going, it will be completed. 3481 * @note On this STM32 series, there is no specific command 3482 * to stop a conversion on-going or to stop ADC converting 3483 * in continuous mode. These actions can be performed 3484 * using function @ref LL_ADC_Disable(). 3485 * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig 3486 * @param ADCx ADC instance 3487 * @retval None 3488 */ 3489 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) 3490 { 3491 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTTRIG); 3492 } 3493 3494 /** 3495 * @brief Get ADC group regular conversion data, range fit for 3496 * all ADC configurations: all ADC resolutions and 3497 * all oversampling increased data width (for devices 3498 * with feature oversampling). 3499 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n 3500 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n 3501 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n 3502 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 3503 * @param ADCx ADC instance 3504 * @param Rank This parameter can be one of the following values: 3505 * @arg @ref LL_ADC_INJ_RANK_1 3506 * @arg @ref LL_ADC_INJ_RANK_2 3507 * @arg @ref LL_ADC_INJ_RANK_3 3508 * @arg @ref LL_ADC_INJ_RANK_4 3509 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 3510 */ 3511 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) 3512 { 3513 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 3514 3515 return (uint32_t)(READ_BIT(*preg, 3516 ADC_JDR1_JDATA) 3517 ); 3518 } 3519 3520 /** 3521 * @brief Get ADC group injected conversion data, range fit for 3522 * ADC resolution 12 bits. 3523 * @note For devices with feature oversampling: Oversampling 3524 * can increase data width, function for extended range 3525 * may be needed: @ref LL_ADC_INJ_ReadConversionData32. 3526 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n 3527 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n 3528 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n 3529 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 3530 * @param ADCx ADC instance 3531 * @param Rank This parameter can be one of the following values: 3532 * @arg @ref LL_ADC_INJ_RANK_1 3533 * @arg @ref LL_ADC_INJ_RANK_2 3534 * @arg @ref LL_ADC_INJ_RANK_3 3535 * @arg @ref LL_ADC_INJ_RANK_4 3536 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 3537 */ 3538 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) 3539 { 3540 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); 3541 3542 return (uint16_t)(READ_BIT(*preg, 3543 ADC_JDR1_JDATA) 3544 ); 3545 } 3546 3547 /** 3548 * @} 3549 */ 3550 3551 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management 3552 * @{ 3553 */ 3554 3555 /** 3556 * @brief Get flag ADC group regular end of sequence conversions. 3557 * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS 3558 * @param ADCx ADC instance 3559 * @retval State of bit (1 or 0). 3560 */ 3561 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) 3562 { 3563 /* Note: on this STM32 series, there is no flag ADC group regular */ 3564 /* end of unitary conversion. */ 3565 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 3566 /* in other STM32 families). */ 3567 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); 3568 } 3569 3570 3571 /** 3572 * @brief Get flag ADC group injected end of sequence conversions. 3573 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS 3574 * @param ADCx ADC instance 3575 * @retval State of bit (1 or 0). 3576 */ 3577 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) 3578 { 3579 /* Note: on this STM32 series, there is no flag ADC group injected */ 3580 /* end of unitary conversion. */ 3581 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 3582 /* in other STM32 families). */ 3583 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); 3584 } 3585 3586 /** 3587 * @brief Get flag ADC analog watchdog 1 flag 3588 * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 3589 * @param ADCx ADC instance 3590 * @retval State of bit (1 or 0). 3591 */ 3592 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) 3593 { 3594 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 3595 } 3596 3597 /** 3598 * @brief Clear flag ADC group regular end of sequence conversions. 3599 * @rmtoll SR EOC LL_ADC_ClearFlag_EOS 3600 * @param ADCx ADC instance 3601 * @retval None 3602 */ 3603 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) 3604 { 3605 /* Note: on this STM32 series, there is no flag ADC group regular */ 3606 /* end of unitary conversion. */ 3607 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 3608 /* in other STM32 families). */ 3609 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS); 3610 } 3611 3612 3613 /** 3614 * @brief Clear flag ADC group injected end of sequence conversions. 3615 * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS 3616 * @param ADCx ADC instance 3617 * @retval None 3618 */ 3619 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) 3620 { 3621 /* Note: on this STM32 series, there is no flag ADC group injected */ 3622 /* end of unitary conversion. */ 3623 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 3624 /* in other STM32 families). */ 3625 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); 3626 } 3627 3628 /** 3629 * @brief Clear flag ADC analog watchdog 1. 3630 * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 3631 * @param ADCx ADC instance 3632 * @retval None 3633 */ 3634 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) 3635 { 3636 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); 3637 } 3638 3639 #if defined(ADC_MULTIMODE_SUPPORT) 3640 /** 3641 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. 3642 * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS 3643 * @param ADCxy_COMMON ADC common instance 3644 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3645 * @retval State of bit (1 or 0). 3646 */ 3647 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) 3648 { 3649 /* Note: on this STM32 series, there is no flag ADC group regular */ 3650 /* end of unitary conversion. */ 3651 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 3652 /* in other STM32 families). */ 3653 return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC)); 3654 } 3655 3656 /** 3657 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. 3658 * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS 3659 * @param ADCxy_COMMON ADC common instance 3660 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3661 * @retval State of bit (1 or 0). 3662 */ 3663 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) 3664 { 3665 /* Note: on this STM32 series, there is no flag ADC group regular */ 3666 /* end of unitary conversion. */ 3667 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 3668 /* in other STM32 families). */ 3669 3670 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); 3671 3672 return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); 3673 } 3674 3675 3676 /** 3677 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. 3678 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS 3679 * @param ADCxy_COMMON ADC common instance 3680 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3681 * @retval State of bit (1 or 0). 3682 */ 3683 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 3684 { 3685 /* Note: on this STM32 series, there is no flag ADC group injected */ 3686 /* end of unitary conversion. */ 3687 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 3688 /* in other STM32 families). */ 3689 return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_JEOC) == (ADC_SR_JEOC)); 3690 } 3691 3692 /** 3693 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. 3694 * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS 3695 * @param ADCxy_COMMON ADC common instance 3696 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3697 * @retval State of bit (1 or 0). 3698 */ 3699 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) 3700 { 3701 /* Note: on this STM32 series, there is no flag ADC group injected */ 3702 /* end of unitary conversion. */ 3703 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 3704 /* in other STM32 families). */ 3705 3706 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); 3707 3708 return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); 3709 } 3710 3711 /** 3712 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. 3713 * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1 3714 * @param ADCxy_COMMON ADC common instance 3715 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3716 * @retval State of bit (1 or 0). 3717 */ 3718 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 3719 { 3720 return (READ_BIT(ADCxy_COMMON->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 3721 } 3722 3723 /** 3724 * @brief Get flag multimode analog watchdog 1 of the ADC slave. 3725 * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1 3726 * @param ADCxy_COMMON ADC common instance 3727 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 3728 * @retval State of bit (1 or 0). 3729 */ 3730 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) 3731 { 3732 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); 3733 3734 return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); 3735 } 3736 3737 #endif /* ADC_MULTIMODE_SUPPORT */ 3738 3739 /** 3740 * @} 3741 */ 3742 3743 /** @defgroup ADC_LL_EF_IT_Management ADC IT management 3744 * @{ 3745 */ 3746 3747 /** 3748 * @brief Enable interruption ADC group regular end of sequence conversions. 3749 * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS 3750 * @param ADCx ADC instance 3751 * @retval None 3752 */ 3753 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) 3754 { 3755 /* Note: on this STM32 series, there is no flag ADC group regular */ 3756 /* end of unitary conversion. */ 3757 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 3758 /* in other STM32 families). */ 3759 SET_BIT(ADCx->CR1, ADC_CR1_EOCIE); 3760 } 3761 3762 3763 /** 3764 * @brief Enable interruption ADC group injected end of sequence conversions. 3765 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 3766 * @param ADCx ADC instance 3767 * @retval None 3768 */ 3769 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) 3770 { 3771 /* Note: on this STM32 series, there is no flag ADC group injected */ 3772 /* end of unitary conversion. */ 3773 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 3774 /* in other STM32 families). */ 3775 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 3776 } 3777 3778 /** 3779 * @brief Enable interruption ADC analog watchdog 1. 3780 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 3781 * @param ADCx ADC instance 3782 * @retval None 3783 */ 3784 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) 3785 { 3786 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 3787 } 3788 3789 /** 3790 * @brief Disable interruption ADC group regular end of sequence conversions. 3791 * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS 3792 * @param ADCx ADC instance 3793 * @retval None 3794 */ 3795 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) 3796 { 3797 /* Note: on this STM32 series, there is no flag ADC group regular */ 3798 /* end of unitary conversion. */ 3799 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 3800 /* in other STM32 families). */ 3801 CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE); 3802 } 3803 3804 3805 /** 3806 * @brief Disable interruption ADC group injected end of sequence conversions. 3807 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 3808 * @param ADCx ADC instance 3809 * @retval None 3810 */ 3811 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) 3812 { 3813 /* Note: on this STM32 series, there is no flag ADC group injected */ 3814 /* end of unitary conversion. */ 3815 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 3816 /* in other STM32 families). */ 3817 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); 3818 } 3819 3820 /** 3821 * @brief Disable interruption ADC analog watchdog 1. 3822 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 3823 * @param ADCx ADC instance 3824 * @retval None 3825 */ 3826 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) 3827 { 3828 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); 3829 } 3830 3831 /** 3832 * @brief Get state of interruption ADC group regular end of sequence conversions 3833 * (0: interrupt disabled, 1: interrupt enabled). 3834 * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS 3835 * @param ADCx ADC instance 3836 * @retval State of bit (1 or 0). 3837 */ 3838 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) 3839 { 3840 /* Note: on this STM32 series, there is no flag ADC group regular */ 3841 /* end of unitary conversion. */ 3842 /* Flag noted as "EOC" is corresponding to flag "EOS" */ 3843 /* in other STM32 families). */ 3844 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); 3845 } 3846 3847 3848 /** 3849 * @brief Get state of interruption ADC group injected end of sequence conversions 3850 * (0: interrupt disabled, 1: interrupt enabled). 3851 * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS 3852 * @param ADCx ADC instance 3853 * @retval State of bit (1 or 0). 3854 */ 3855 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) 3856 { 3857 /* Note: on this STM32 series, there is no flag ADC group injected */ 3858 /* end of unitary conversion. */ 3859 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ 3860 /* in other STM32 families). */ 3861 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); 3862 } 3863 3864 /** 3865 * @brief Get state of interruption ADC analog watchdog 1 3866 * (0: interrupt disabled, 1: interrupt enabled). 3867 * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 3868 * @param ADCx ADC instance 3869 * @retval State of bit (1 or 0). 3870 */ 3871 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) 3872 { 3873 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); 3874 } 3875 3876 /** 3877 * @} 3878 */ 3879 3880 #if defined(USE_FULL_LL_DRIVER) 3881 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions 3882 * @{ 3883 */ 3884 3885 /* Initialization of some features of ADC common parameters and multimode */ 3886 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); 3887 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 3888 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); 3889 3890 /* De-initialization of ADC instance, ADC group regular and ADC group injected */ 3891 /* (availability of ADC group injected depends on STM32 families) */ 3892 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); 3893 3894 /* Initialization of some features of ADC instance */ 3895 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); 3896 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); 3897 3898 /* Initialization of some features of ADC instance and ADC group regular */ 3899 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 3900 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); 3901 3902 /* Initialization of some features of ADC instance and ADC group injected */ 3903 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 3904 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); 3905 3906 /** 3907 * @} 3908 */ 3909 #endif /* USE_FULL_LL_DRIVER */ 3910 3911 /** 3912 * @} 3913 */ 3914 3915 /** 3916 * @} 3917 */ 3918 3919 #endif /* ADC1 || ADC2 || ADC3 */ 3920 3921 /** 3922 * @} 3923 */ 3924 3925 #ifdef __cplusplus 3926 } 3927 #endif 3928 3929 #endif /* __STM32F1xx_LL_ADC_H */