Drivers/CMSIS/Include/core_armv8mbl.h (97995B)
1 /**************************************************************************//** 2 * @file core_armv8mbl.h 3 * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File 4 * @version V5.0.7 5 * @date 22. June 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_ARMV8MBL_H_GENERIC 32 #define __CORE_ARMV8MBL_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 55 /******************************************************************************* 56 * CMSIS definitions 57 ******************************************************************************/ 58 /** 59 \ingroup Cortex_ARMv8MBL 60 @{ 61 */ 62 63 #include "cmsis_version.h" 64 65 /* CMSIS definitions */ 66 #define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 67 #define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 68 #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ 69 __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 70 71 #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ 72 73 /** __FPU_USED indicates whether an FPU is used or not. 74 This core does not support an FPU at all 75 */ 76 #define __FPU_USED 0U 77 78 #if defined ( __CC_ARM ) 79 #if defined __TARGET_FPU_VFP 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 81 #endif 82 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 84 #if defined __ARM_PCS_VFP 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 86 #endif 87 88 #elif defined ( __GNUC__ ) 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 91 #endif 92 93 #elif defined ( __ICCARM__ ) 94 #if defined __ARMVFP__ 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 96 #endif 97 98 #elif defined ( __TI_ARM__ ) 99 #if defined __TI_VFP_SUPPORT__ 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 101 #endif 102 103 #elif defined ( __TASKING__ ) 104 #if defined __FPU_VFP__ 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 106 #endif 107 108 #elif defined ( __CSMC__ ) 109 #if ( __CSMC__ & 0x400U) 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 111 #endif 112 113 #endif 114 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 116 117 118 #ifdef __cplusplus 119 } 120 #endif 121 122 #endif /* __CORE_ARMV8MBL_H_GENERIC */ 123 124 #ifndef __CMSIS_GENERIC 125 126 #ifndef __CORE_ARMV8MBL_H_DEPENDANT 127 #define __CORE_ARMV8MBL_H_DEPENDANT 128 129 #ifdef __cplusplus 130 extern "C" { 131 #endif 132 133 /* check device defines and use defaults */ 134 #if defined __CHECK_DEVICE_DEFINES 135 #ifndef __ARMv8MBL_REV 136 #define __ARMv8MBL_REV 0x0000U 137 #warning "__ARMv8MBL_REV not defined in device header file; using default!" 138 #endif 139 140 #ifndef __FPU_PRESENT 141 #define __FPU_PRESENT 0U 142 #warning "__FPU_PRESENT not defined in device header file; using default!" 143 #endif 144 145 #ifndef __MPU_PRESENT 146 #define __MPU_PRESENT 0U 147 #warning "__MPU_PRESENT not defined in device header file; using default!" 148 #endif 149 150 #ifndef __SAUREGION_PRESENT 151 #define __SAUREGION_PRESENT 0U 152 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 153 #endif 154 155 #ifndef __VTOR_PRESENT 156 #define __VTOR_PRESENT 0U 157 #warning "__VTOR_PRESENT not defined in device header file; using default!" 158 #endif 159 160 #ifndef __NVIC_PRIO_BITS 161 #define __NVIC_PRIO_BITS 2U 162 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 163 #endif 164 165 #ifndef __Vendor_SysTickConfig 166 #define __Vendor_SysTickConfig 0U 167 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 168 #endif 169 170 #ifndef __ETM_PRESENT 171 #define __ETM_PRESENT 0U 172 #warning "__ETM_PRESENT not defined in device header file; using default!" 173 #endif 174 175 #ifndef __MTB_PRESENT 176 #define __MTB_PRESENT 0U 177 #warning "__MTB_PRESENT not defined in device header file; using default!" 178 #endif 179 180 #endif 181 182 /* IO definitions (access restrictions to peripheral registers) */ 183 /** 184 \defgroup CMSIS_glob_defs CMSIS Global Defines 185 186 <strong>IO Type Qualifiers</strong> are used 187 \li to specify the access to peripheral variables. 188 \li for automatic generation of peripheral register debug information. 189 */ 190 #ifdef __cplusplus 191 #define __I volatile /*!< Defines 'read only' permissions */ 192 #else 193 #define __I volatile const /*!< Defines 'read only' permissions */ 194 #endif 195 #define __O volatile /*!< Defines 'write only' permissions */ 196 #define __IO volatile /*!< Defines 'read / write' permissions */ 197 198 /* following defines should be used for structure members */ 199 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 200 #define __OM volatile /*! Defines 'write only' structure member permissions */ 201 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 202 203 /*@} end of group ARMv8MBL */ 204 205 206 207 /******************************************************************************* 208 * Register Abstraction 209 Core Register contain: 210 - Core Register 211 - Core NVIC Register 212 - Core SCB Register 213 - Core SysTick Register 214 - Core Debug Register 215 - Core MPU Register 216 - Core SAU Register 217 ******************************************************************************/ 218 /** 219 \defgroup CMSIS_core_register Defines and Type Definitions 220 \brief Type definitions and defines for Cortex-M processor based devices. 221 */ 222 223 /** 224 \ingroup CMSIS_core_register 225 \defgroup CMSIS_CORE Status and Control Registers 226 \brief Core Register type definitions. 227 @{ 228 */ 229 230 /** 231 \brief Union type to access the Application Program Status Register (APSR). 232 */ 233 typedef union 234 { 235 struct 236 { 237 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 238 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 239 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 240 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 241 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 242 } b; /*!< Structure used for bit access */ 243 uint32_t w; /*!< Type used for word access */ 244 } APSR_Type; 245 246 /* APSR Register Definitions */ 247 #define APSR_N_Pos 31U /*!< APSR: N Position */ 248 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 249 250 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 251 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 252 253 #define APSR_C_Pos 29U /*!< APSR: C Position */ 254 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 255 256 #define APSR_V_Pos 28U /*!< APSR: V Position */ 257 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 258 259 260 /** 261 \brief Union type to access the Interrupt Program Status Register (IPSR). 262 */ 263 typedef union 264 { 265 struct 266 { 267 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 268 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 269 } b; /*!< Structure used for bit access */ 270 uint32_t w; /*!< Type used for word access */ 271 } IPSR_Type; 272 273 /* IPSR Register Definitions */ 274 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 275 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 276 277 278 /** 279 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 280 */ 281 typedef union 282 { 283 struct 284 { 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 288 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 289 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 290 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 291 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 292 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 293 } b; /*!< Structure used for bit access */ 294 uint32_t w; /*!< Type used for word access */ 295 } xPSR_Type; 296 297 /* xPSR Register Definitions */ 298 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 299 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 300 301 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 302 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 303 304 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 305 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 306 307 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 308 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 309 310 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 311 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 312 313 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 314 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 315 316 317 /** 318 \brief Union type to access the Control Registers (CONTROL). 319 */ 320 typedef union 321 { 322 struct 323 { 324 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 325 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ 326 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 327 } b; /*!< Structure used for bit access */ 328 uint32_t w; /*!< Type used for word access */ 329 } CONTROL_Type; 330 331 /* CONTROL Register Definitions */ 332 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 333 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 334 335 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 336 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 337 338 /*@} end of group CMSIS_CORE */ 339 340 341 /** 342 \ingroup CMSIS_core_register 343 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 344 \brief Type definitions for the NVIC Registers 345 @{ 346 */ 347 348 /** 349 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 350 */ 351 typedef struct 352 { 353 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 354 uint32_t RESERVED0[16U]; 355 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 356 uint32_t RSERVED1[16U]; 357 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 358 uint32_t RESERVED2[16U]; 359 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 360 uint32_t RESERVED3[16U]; 361 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 362 uint32_t RESERVED4[16U]; 363 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 364 uint32_t RESERVED5[16U]; 365 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 366 } NVIC_Type; 367 368 /*@} end of group CMSIS_NVIC */ 369 370 371 /** 372 \ingroup CMSIS_core_register 373 \defgroup CMSIS_SCB System Control Block (SCB) 374 \brief Type definitions for the System Control Block Registers 375 @{ 376 */ 377 378 /** 379 \brief Structure type to access the System Control Block (SCB). 380 */ 381 typedef struct 382 { 383 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 384 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 385 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 386 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 387 #else 388 uint32_t RESERVED0; 389 #endif 390 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 391 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 392 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 393 uint32_t RESERVED1; 394 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 395 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 396 } SCB_Type; 397 398 /* SCB CPUID Register Definitions */ 399 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 401 402 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 404 405 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 407 408 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 410 411 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 413 414 /* SCB Interrupt Control State Register Definitions */ 415 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 416 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 417 418 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 419 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 420 421 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 422 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 423 424 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 425 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 426 427 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 428 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 429 430 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 431 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 432 433 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 434 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 435 436 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 437 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 438 439 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 440 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 441 442 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 443 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 444 445 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 446 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 447 448 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 449 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 450 451 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 453 454 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 455 /* SCB Vector Table Offset Register Definitions */ 456 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 457 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 458 #endif 459 460 /* SCB Application Interrupt and Reset Control Register Definitions */ 461 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 462 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 463 464 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 465 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 466 467 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 468 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 469 470 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 471 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 472 473 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 474 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 475 476 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 477 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 478 479 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 480 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 481 482 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 483 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 484 485 /* SCB System Control Register Definitions */ 486 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 487 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 488 489 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 490 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 491 492 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 493 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 494 495 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 496 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 497 498 /* SCB Configuration Control Register Definitions */ 499 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 500 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 501 502 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 503 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 504 505 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 506 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 507 508 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 509 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 510 511 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 512 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 513 514 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 515 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 516 517 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 518 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 519 520 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 521 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 522 523 /* SCB System Handler Control and State Register Definitions */ 524 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 525 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 526 527 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 528 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 529 530 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 531 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 532 533 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 534 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 535 536 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 537 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 538 539 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 540 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 541 542 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 543 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 544 545 /*@} end of group CMSIS_SCB */ 546 547 548 /** 549 \ingroup CMSIS_core_register 550 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 551 \brief Type definitions for the System Timer Registers. 552 @{ 553 */ 554 555 /** 556 \brief Structure type to access the System Timer (SysTick). 557 */ 558 typedef struct 559 { 560 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 561 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 562 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 563 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 564 } SysTick_Type; 565 566 /* SysTick Control / Status Register Definitions */ 567 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 568 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 569 570 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 571 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 572 573 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 574 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 575 576 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 577 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 578 579 /* SysTick Reload Register Definitions */ 580 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 581 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 582 583 /* SysTick Current Register Definitions */ 584 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 585 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 586 587 /* SysTick Calibration Register Definitions */ 588 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 589 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 590 591 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 592 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 593 594 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 595 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 596 597 /*@} end of group CMSIS_SysTick */ 598 599 600 /** 601 \ingroup CMSIS_core_register 602 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 603 \brief Type definitions for the Data Watchpoint and Trace (DWT) 604 @{ 605 */ 606 607 /** 608 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 609 */ 610 typedef struct 611 { 612 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 613 uint32_t RESERVED0[6U]; 614 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 615 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 616 uint32_t RESERVED1[1U]; 617 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 618 uint32_t RESERVED2[1U]; 619 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 620 uint32_t RESERVED3[1U]; 621 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 622 uint32_t RESERVED4[1U]; 623 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 624 uint32_t RESERVED5[1U]; 625 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 626 uint32_t RESERVED6[1U]; 627 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 628 uint32_t RESERVED7[1U]; 629 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 630 uint32_t RESERVED8[1U]; 631 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 632 uint32_t RESERVED9[1U]; 633 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 634 uint32_t RESERVED10[1U]; 635 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 636 uint32_t RESERVED11[1U]; 637 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 638 uint32_t RESERVED12[1U]; 639 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 640 uint32_t RESERVED13[1U]; 641 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 642 uint32_t RESERVED14[1U]; 643 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 644 uint32_t RESERVED15[1U]; 645 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 646 uint32_t RESERVED16[1U]; 647 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 648 uint32_t RESERVED17[1U]; 649 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 650 uint32_t RESERVED18[1U]; 651 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 652 uint32_t RESERVED19[1U]; 653 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 654 uint32_t RESERVED20[1U]; 655 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 656 uint32_t RESERVED21[1U]; 657 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 658 uint32_t RESERVED22[1U]; 659 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 660 uint32_t RESERVED23[1U]; 661 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 662 uint32_t RESERVED24[1U]; 663 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 664 uint32_t RESERVED25[1U]; 665 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 666 uint32_t RESERVED26[1U]; 667 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 668 uint32_t RESERVED27[1U]; 669 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 670 uint32_t RESERVED28[1U]; 671 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 672 uint32_t RESERVED29[1U]; 673 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 674 uint32_t RESERVED30[1U]; 675 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 676 uint32_t RESERVED31[1U]; 677 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 678 } DWT_Type; 679 680 /* DWT Control Register Definitions */ 681 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 683 684 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 686 687 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 689 690 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 692 693 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 695 696 /* DWT Comparator Function Register Definitions */ 697 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 698 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 699 700 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 701 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 702 703 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 704 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 705 706 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 707 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 708 709 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 710 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 711 712 /*@}*/ /* end of group CMSIS_DWT */ 713 714 715 /** 716 \ingroup CMSIS_core_register 717 \defgroup CMSIS_TPI Trace Port Interface (TPI) 718 \brief Type definitions for the Trace Port Interface (TPI) 719 @{ 720 */ 721 722 /** 723 \brief Structure type to access the Trace Port Interface Register (TPI). 724 */ 725 typedef struct 726 { 727 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ 728 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ 729 uint32_t RESERVED0[2U]; 730 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 731 uint32_t RESERVED1[55U]; 732 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 733 uint32_t RESERVED2[131U]; 734 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 735 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 736 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 737 uint32_t RESERVED3[809U]; 738 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ 739 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ 740 uint32_t RESERVED4[4U]; 741 __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ 742 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ 743 } TPI_Type; 744 745 /* TPI Asynchronous Clock Prescaler Register Definitions */ 746 #define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ 747 #define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ 748 749 /* TPI Selected Pin Protocol Register Definitions */ 750 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 751 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 752 753 /* TPI Formatter and Flush Status Register Definitions */ 754 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 755 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 756 757 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 758 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 759 760 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 761 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 762 763 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 764 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 765 766 /* TPI Formatter and Flush Control Register Definitions */ 767 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 768 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 769 770 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 771 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 772 773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 775 776 /* TPI Periodic Synchronization Control Register Definitions */ 777 #define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ 778 #define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ 779 780 /* TPI Software Lock Status Register Definitions */ 781 #define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ 782 #define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ 783 784 #define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ 785 #define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ 786 787 #define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ 788 #define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ 789 790 /* TPI DEVID Register Definitions */ 791 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 792 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 793 794 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 795 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 796 797 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 798 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 799 800 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ 801 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ 802 803 /* TPI DEVTYPE Register Definitions */ 804 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 805 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 806 807 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 808 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 809 810 /*@}*/ /* end of group CMSIS_TPI */ 811 812 813 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 814 /** 815 \ingroup CMSIS_core_register 816 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 817 \brief Type definitions for the Memory Protection Unit (MPU) 818 @{ 819 */ 820 821 /** 822 \brief Structure type to access the Memory Protection Unit (MPU). 823 */ 824 typedef struct 825 { 826 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 827 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 828 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 829 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 830 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 831 uint32_t RESERVED0[7U]; 832 union { 833 __IOM uint32_t MAIR[2]; 834 struct { 835 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 836 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 837 }; 838 }; 839 } MPU_Type; 840 841 #define MPU_TYPE_RALIASES 1U 842 843 /* MPU Type Register Definitions */ 844 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 845 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 846 847 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 848 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 849 850 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 851 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 852 853 /* MPU Control Register Definitions */ 854 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 855 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 856 857 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 858 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 859 860 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 861 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 862 863 /* MPU Region Number Register Definitions */ 864 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 865 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 866 867 /* MPU Region Base Address Register Definitions */ 868 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 869 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 870 871 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 872 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 873 874 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 875 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 876 877 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 878 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 879 880 /* MPU Region Limit Address Register Definitions */ 881 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 882 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 883 884 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 885 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 886 887 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ 888 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ 889 890 /* MPU Memory Attribute Indirection Register 0 Definitions */ 891 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 892 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 893 894 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 895 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 896 897 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 898 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 899 900 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 901 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 902 903 /* MPU Memory Attribute Indirection Register 1 Definitions */ 904 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 905 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 906 907 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 908 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 909 910 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 911 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 912 913 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 914 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 915 916 /*@} end of group CMSIS_MPU */ 917 #endif 918 919 920 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 921 /** 922 \ingroup CMSIS_core_register 923 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 924 \brief Type definitions for the Security Attribution Unit (SAU) 925 @{ 926 */ 927 928 /** 929 \brief Structure type to access the Security Attribution Unit (SAU). 930 */ 931 typedef struct 932 { 933 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 934 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 935 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 936 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 937 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 938 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 939 #endif 940 } SAU_Type; 941 942 /* SAU Control Register Definitions */ 943 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 944 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 945 946 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 947 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 948 949 /* SAU Type Register Definitions */ 950 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 951 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 952 953 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 954 /* SAU Region Number Register Definitions */ 955 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 956 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 957 958 /* SAU Region Base Address Register Definitions */ 959 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 960 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 961 962 /* SAU Region Limit Address Register Definitions */ 963 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 964 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 965 966 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 967 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 968 969 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 970 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 971 972 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 973 974 /*@} end of group CMSIS_SAU */ 975 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 976 977 978 /** 979 \ingroup CMSIS_core_register 980 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 981 \brief Type definitions for the Core Debug Registers 982 @{ 983 */ 984 985 /** 986 \brief Structure type to access the Core Debug Register (CoreDebug). 987 */ 988 typedef struct 989 { 990 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 991 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 992 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 993 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 994 uint32_t RESERVED4[1U]; 995 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 996 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 997 } CoreDebug_Type; 998 999 /* Debug Halting Control and Status Register Definitions */ 1000 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 1001 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1002 1003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 1004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 1005 1006 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1007 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1008 1009 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1010 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1011 1012 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1013 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1014 1015 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 1016 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1017 1018 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 1019 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1020 1021 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 1022 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1023 1024 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1025 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1026 1027 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 1028 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1029 1030 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 1031 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1032 1033 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1034 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1035 1036 /* Debug Core Register Selector Register Definitions */ 1037 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 1038 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1039 1040 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 1041 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 1042 1043 /* Debug Exception and Monitor Control Register */ 1044 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ 1045 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ 1046 1047 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1048 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1049 1050 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1051 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1052 1053 /* Debug Authentication Control Register Definitions */ 1054 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 1055 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 1056 1057 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 1058 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 1059 1060 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 1061 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 1062 1063 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 1064 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 1065 1066 /* Debug Security Control and Status Register Definitions */ 1067 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 1068 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 1069 1070 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 1071 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 1072 1073 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 1074 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 1075 1076 /*@} end of group CMSIS_CoreDebug */ 1077 1078 1079 /** 1080 \ingroup CMSIS_core_register 1081 \defgroup CMSIS_core_bitfield Core register bit field macros 1082 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1083 @{ 1084 */ 1085 1086 /** 1087 \brief Mask and shift a bit field value for use in a register bit range. 1088 \param[in] field Name of the register bit field. 1089 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1090 \return Masked and shifted value. 1091 */ 1092 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1093 1094 /** 1095 \brief Mask and shift a register value to extract a bit filed value. 1096 \param[in] field Name of the register bit field. 1097 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1098 \return Masked and shifted bit field value. 1099 */ 1100 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1101 1102 /*@} end of group CMSIS_core_bitfield */ 1103 1104 1105 /** 1106 \ingroup CMSIS_core_register 1107 \defgroup CMSIS_core_base Core Definitions 1108 \brief Definitions for base addresses, unions, and structures. 1109 @{ 1110 */ 1111 1112 /* Memory mapping of Core Hardware */ 1113 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1114 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1115 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1116 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1117 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1118 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1119 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1120 1121 1122 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1123 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1124 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1125 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1126 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1127 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 1128 1129 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1130 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1131 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1132 #endif 1133 1134 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1135 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 1136 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 1137 #endif 1138 1139 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1140 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 1141 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 1142 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 1143 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 1144 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 1145 1146 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 1147 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 1148 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 1149 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 1150 1151 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1152 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 1153 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 1154 #endif 1155 1156 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1157 /*@} */ 1158 1159 1160 1161 /******************************************************************************* 1162 * Hardware Abstraction Layer 1163 Core Function Interface contains: 1164 - Core NVIC Functions 1165 - Core SysTick Functions 1166 - Core Register Access Functions 1167 ******************************************************************************/ 1168 /** 1169 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1170 */ 1171 1172 1173 1174 /* ########################## NVIC functions #################################### */ 1175 /** 1176 \ingroup CMSIS_Core_FunctionInterface 1177 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1178 \brief Functions that manage interrupts and exceptions via the NVIC. 1179 @{ 1180 */ 1181 1182 #ifdef CMSIS_NVIC_VIRTUAL 1183 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1184 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1185 #endif 1186 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1187 #else 1188 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1189 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1190 #define NVIC_EnableIRQ __NVIC_EnableIRQ 1191 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1192 #define NVIC_DisableIRQ __NVIC_DisableIRQ 1193 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1194 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1195 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1196 #define NVIC_GetActive __NVIC_GetActive 1197 #define NVIC_SetPriority __NVIC_SetPriority 1198 #define NVIC_GetPriority __NVIC_GetPriority 1199 #define NVIC_SystemReset __NVIC_SystemReset 1200 #endif /* CMSIS_NVIC_VIRTUAL */ 1201 1202 #ifdef CMSIS_VECTAB_VIRTUAL 1203 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1204 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1205 #endif 1206 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1207 #else 1208 #define NVIC_SetVector __NVIC_SetVector 1209 #define NVIC_GetVector __NVIC_GetVector 1210 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1211 1212 #define NVIC_USER_IRQ_OFFSET 16 1213 1214 1215 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 1216 1217 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 1218 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 1219 1220 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 1221 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 1222 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 1223 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 1224 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 1225 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 1226 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ 1227 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 1228 1229 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 1230 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 1231 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 1232 #else 1233 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 1234 #endif 1235 1236 1237 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 1238 /* The following MACROS handle generation of the register offset and byte masks */ 1239 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 1240 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 1241 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 1242 1243 #define __NVIC_SetPriorityGrouping(X) (void)(X) 1244 #define __NVIC_GetPriorityGrouping() (0U) 1245 1246 /** 1247 \brief Enable Interrupt 1248 \details Enables a device specific interrupt in the NVIC interrupt controller. 1249 \param [in] IRQn Device specific interrupt number. 1250 \note IRQn must not be negative. 1251 */ 1252 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1253 { 1254 if ((int32_t)(IRQn) >= 0) 1255 { 1256 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1257 } 1258 } 1259 1260 1261 /** 1262 \brief Get Interrupt Enable status 1263 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1264 \param [in] IRQn Device specific interrupt number. 1265 \return 0 Interrupt is not enabled. 1266 \return 1 Interrupt is enabled. 1267 \note IRQn must not be negative. 1268 */ 1269 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1270 { 1271 if ((int32_t)(IRQn) >= 0) 1272 { 1273 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1274 } 1275 else 1276 { 1277 return(0U); 1278 } 1279 } 1280 1281 1282 /** 1283 \brief Disable Interrupt 1284 \details Disables a device specific interrupt in the NVIC interrupt controller. 1285 \param [in] IRQn Device specific interrupt number. 1286 \note IRQn must not be negative. 1287 */ 1288 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1289 { 1290 if ((int32_t)(IRQn) >= 0) 1291 { 1292 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1293 __DSB(); 1294 __ISB(); 1295 } 1296 } 1297 1298 1299 /** 1300 \brief Get Pending Interrupt 1301 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 1302 \param [in] IRQn Device specific interrupt number. 1303 \return 0 Interrupt status is not pending. 1304 \return 1 Interrupt status is pending. 1305 \note IRQn must not be negative. 1306 */ 1307 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1308 { 1309 if ((int32_t)(IRQn) >= 0) 1310 { 1311 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1312 } 1313 else 1314 { 1315 return(0U); 1316 } 1317 } 1318 1319 1320 /** 1321 \brief Set Pending Interrupt 1322 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1323 \param [in] IRQn Device specific interrupt number. 1324 \note IRQn must not be negative. 1325 */ 1326 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1327 { 1328 if ((int32_t)(IRQn) >= 0) 1329 { 1330 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1331 } 1332 } 1333 1334 1335 /** 1336 \brief Clear Pending Interrupt 1337 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1338 \param [in] IRQn Device specific interrupt number. 1339 \note IRQn must not be negative. 1340 */ 1341 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1342 { 1343 if ((int32_t)(IRQn) >= 0) 1344 { 1345 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1346 } 1347 } 1348 1349 1350 /** 1351 \brief Get Active Interrupt 1352 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 1353 \param [in] IRQn Device specific interrupt number. 1354 \return 0 Interrupt status is not active. 1355 \return 1 Interrupt status is active. 1356 \note IRQn must not be negative. 1357 */ 1358 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1359 { 1360 if ((int32_t)(IRQn) >= 0) 1361 { 1362 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1363 } 1364 else 1365 { 1366 return(0U); 1367 } 1368 } 1369 1370 1371 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1372 /** 1373 \brief Get Interrupt Target State 1374 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1375 \param [in] IRQn Device specific interrupt number. 1376 \return 0 if interrupt is assigned to Secure 1377 \return 1 if interrupt is assigned to Non Secure 1378 \note IRQn must not be negative. 1379 */ 1380 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 1381 { 1382 if ((int32_t)(IRQn) >= 0) 1383 { 1384 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1385 } 1386 else 1387 { 1388 return(0U); 1389 } 1390 } 1391 1392 1393 /** 1394 \brief Set Interrupt Target State 1395 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1396 \param [in] IRQn Device specific interrupt number. 1397 \return 0 if interrupt is assigned to Secure 1398 1 if interrupt is assigned to Non Secure 1399 \note IRQn must not be negative. 1400 */ 1401 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 1402 { 1403 if ((int32_t)(IRQn) >= 0) 1404 { 1405 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 1406 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1407 } 1408 else 1409 { 1410 return(0U); 1411 } 1412 } 1413 1414 1415 /** 1416 \brief Clear Interrupt Target State 1417 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1418 \param [in] IRQn Device specific interrupt number. 1419 \return 0 if interrupt is assigned to Secure 1420 1 if interrupt is assigned to Non Secure 1421 \note IRQn must not be negative. 1422 */ 1423 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 1424 { 1425 if ((int32_t)(IRQn) >= 0) 1426 { 1427 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 1428 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1429 } 1430 else 1431 { 1432 return(0U); 1433 } 1434 } 1435 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1436 1437 1438 /** 1439 \brief Set Interrupt Priority 1440 \details Sets the priority of a device specific interrupt or a processor exception. 1441 The interrupt number can be positive to specify a device specific interrupt, 1442 or negative to specify a processor exception. 1443 \param [in] IRQn Interrupt number. 1444 \param [in] priority Priority to set. 1445 \note The priority cannot be set for every processor exception. 1446 */ 1447 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1448 { 1449 if ((int32_t)(IRQn) >= 0) 1450 { 1451 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1452 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1453 } 1454 else 1455 { 1456 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1457 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1458 } 1459 } 1460 1461 1462 /** 1463 \brief Get Interrupt Priority 1464 \details Reads the priority of a device specific interrupt or a processor exception. 1465 The interrupt number can be positive to specify a device specific interrupt, 1466 or negative to specify a processor exception. 1467 \param [in] IRQn Interrupt number. 1468 \return Interrupt Priority. 1469 Value is aligned automatically to the implemented priority bits of the microcontroller. 1470 */ 1471 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1472 { 1473 1474 if ((int32_t)(IRQn) >= 0) 1475 { 1476 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1477 } 1478 else 1479 { 1480 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1481 } 1482 } 1483 1484 1485 /** 1486 \brief Encode Priority 1487 \details Encodes the priority for an interrupt with the given priority group, 1488 preemptive priority value, and subpriority value. 1489 In case of a conflict between priority grouping and available 1490 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1491 \param [in] PriorityGroup Used priority group. 1492 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1493 \param [in] SubPriority Subpriority value (starting from 0). 1494 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1495 */ 1496 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 1497 { 1498 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1499 uint32_t PreemptPriorityBits; 1500 uint32_t SubPriorityBits; 1501 1502 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 1503 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1504 1505 return ( 1506 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 1507 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 1508 ); 1509 } 1510 1511 1512 /** 1513 \brief Decode Priority 1514 \details Decodes an interrupt priority value with a given priority group to 1515 preemptive priority value and subpriority value. 1516 In case of a conflict between priority grouping and available 1517 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1518 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1519 \param [in] PriorityGroup Used priority group. 1520 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1521 \param [out] pSubPriority Subpriority value (starting from 0). 1522 */ 1523 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 1524 { 1525 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 1526 uint32_t PreemptPriorityBits; 1527 uint32_t SubPriorityBits; 1528 1529 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 1530 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 1531 1532 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 1533 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 1534 } 1535 1536 1537 /** 1538 \brief Set Interrupt Vector 1539 \details Sets an interrupt vector in SRAM based interrupt vector table. 1540 The interrupt number can be positive to specify a device specific interrupt, 1541 or negative to specify a processor exception. 1542 VTOR must been relocated to SRAM before. 1543 If VTOR is not present address 0 must be mapped to SRAM. 1544 \param [in] IRQn Interrupt number 1545 \param [in] vector Address of interrupt handler function 1546 */ 1547 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 1548 { 1549 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 1550 uint32_t *vectors = (uint32_t *)SCB->VTOR; 1551 #else 1552 uint32_t *vectors = (uint32_t *)0x0U; 1553 #endif 1554 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 1555 } 1556 1557 1558 /** 1559 \brief Get Interrupt Vector 1560 \details Reads an interrupt vector from interrupt vector table. 1561 The interrupt number can be positive to specify a device specific interrupt, 1562 or negative to specify a processor exception. 1563 \param [in] IRQn Interrupt number. 1564 \return Address of interrupt handler function 1565 */ 1566 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 1567 { 1568 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 1569 uint32_t *vectors = (uint32_t *)SCB->VTOR; 1570 #else 1571 uint32_t *vectors = (uint32_t *)0x0U; 1572 #endif 1573 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 1574 } 1575 1576 1577 /** 1578 \brief System Reset 1579 \details Initiates a system reset request to reset the MCU. 1580 */ 1581 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 1582 { 1583 __DSB(); /* Ensure all outstanding memory accesses included 1584 buffered write are completed before reset */ 1585 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1586 SCB_AIRCR_SYSRESETREQ_Msk); 1587 __DSB(); /* Ensure completion of memory access */ 1588 1589 for(;;) /* wait until reset */ 1590 { 1591 __NOP(); 1592 } 1593 } 1594 1595 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1596 /** 1597 \brief Enable Interrupt (non-secure) 1598 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 1599 \param [in] IRQn Device specific interrupt number. 1600 \note IRQn must not be negative. 1601 */ 1602 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 1603 { 1604 if ((int32_t)(IRQn) >= 0) 1605 { 1606 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1607 } 1608 } 1609 1610 1611 /** 1612 \brief Get Interrupt Enable status (non-secure) 1613 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 1614 \param [in] IRQn Device specific interrupt number. 1615 \return 0 Interrupt is not enabled. 1616 \return 1 Interrupt is enabled. 1617 \note IRQn must not be negative. 1618 */ 1619 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 1620 { 1621 if ((int32_t)(IRQn) >= 0) 1622 { 1623 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1624 } 1625 else 1626 { 1627 return(0U); 1628 } 1629 } 1630 1631 1632 /** 1633 \brief Disable Interrupt (non-secure) 1634 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 1635 \param [in] IRQn Device specific interrupt number. 1636 \note IRQn must not be negative. 1637 */ 1638 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 1639 { 1640 if ((int32_t)(IRQn) >= 0) 1641 { 1642 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1643 } 1644 } 1645 1646 1647 /** 1648 \brief Get Pending Interrupt (non-secure) 1649 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 1650 \param [in] IRQn Device specific interrupt number. 1651 \return 0 Interrupt status is not pending. 1652 \return 1 Interrupt status is pending. 1653 \note IRQn must not be negative. 1654 */ 1655 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 1656 { 1657 if ((int32_t)(IRQn) >= 0) 1658 { 1659 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1660 } 1661 else 1662 { 1663 return(0U); 1664 } 1665 } 1666 1667 1668 /** 1669 \brief Set Pending Interrupt (non-secure) 1670 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 1671 \param [in] IRQn Device specific interrupt number. 1672 \note IRQn must not be negative. 1673 */ 1674 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 1675 { 1676 if ((int32_t)(IRQn) >= 0) 1677 { 1678 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1679 } 1680 } 1681 1682 1683 /** 1684 \brief Clear Pending Interrupt (non-secure) 1685 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 1686 \param [in] IRQn Device specific interrupt number. 1687 \note IRQn must not be negative. 1688 */ 1689 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 1690 { 1691 if ((int32_t)(IRQn) >= 0) 1692 { 1693 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1694 } 1695 } 1696 1697 1698 /** 1699 \brief Get Active Interrupt (non-secure) 1700 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 1701 \param [in] IRQn Device specific interrupt number. 1702 \return 0 Interrupt status is not active. 1703 \return 1 Interrupt status is active. 1704 \note IRQn must not be negative. 1705 */ 1706 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 1707 { 1708 if ((int32_t)(IRQn) >= 0) 1709 { 1710 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1711 } 1712 else 1713 { 1714 return(0U); 1715 } 1716 } 1717 1718 1719 /** 1720 \brief Set Interrupt Priority (non-secure) 1721 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 1722 The interrupt number can be positive to specify a device specific interrupt, 1723 or negative to specify a processor exception. 1724 \param [in] IRQn Interrupt number. 1725 \param [in] priority Priority to set. 1726 \note The priority cannot be set for every non-secure processor exception. 1727 */ 1728 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 1729 { 1730 if ((int32_t)(IRQn) >= 0) 1731 { 1732 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1733 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1734 } 1735 else 1736 { 1737 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1738 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1739 } 1740 } 1741 1742 1743 /** 1744 \brief Get Interrupt Priority (non-secure) 1745 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 1746 The interrupt number can be positive to specify a device specific interrupt, 1747 or negative to specify a processor exception. 1748 \param [in] IRQn Interrupt number. 1749 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 1750 */ 1751 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 1752 { 1753 1754 if ((int32_t)(IRQn) >= 0) 1755 { 1756 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1757 } 1758 else 1759 { 1760 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1761 } 1762 } 1763 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 1764 1765 /*@} end of CMSIS_Core_NVICFunctions */ 1766 1767 /* ########################## MPU functions #################################### */ 1768 1769 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1770 1771 #include "mpu_armv8.h" 1772 1773 #endif 1774 1775 /* ########################## FPU functions #################################### */ 1776 /** 1777 \ingroup CMSIS_Core_FunctionInterface 1778 \defgroup CMSIS_Core_FpuFunctions FPU Functions 1779 \brief Function that provides FPU type. 1780 @{ 1781 */ 1782 1783 /** 1784 \brief get FPU type 1785 \details returns the FPU type 1786 \returns 1787 - \b 0: No FPU 1788 - \b 1: Single precision FPU 1789 - \b 2: Double + Single precision FPU 1790 */ 1791 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 1792 { 1793 return 0U; /* No FPU */ 1794 } 1795 1796 1797 /*@} end of CMSIS_Core_FpuFunctions */ 1798 1799 1800 1801 /* ########################## SAU functions #################################### */ 1802 /** 1803 \ingroup CMSIS_Core_FunctionInterface 1804 \defgroup CMSIS_Core_SAUFunctions SAU Functions 1805 \brief Functions that configure the SAU. 1806 @{ 1807 */ 1808 1809 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1810 1811 /** 1812 \brief Enable SAU 1813 \details Enables the Security Attribution Unit (SAU). 1814 */ 1815 __STATIC_INLINE void TZ_SAU_Enable(void) 1816 { 1817 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 1818 } 1819 1820 1821 1822 /** 1823 \brief Disable SAU 1824 \details Disables the Security Attribution Unit (SAU). 1825 */ 1826 __STATIC_INLINE void TZ_SAU_Disable(void) 1827 { 1828 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 1829 } 1830 1831 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1832 1833 /*@} end of CMSIS_Core_SAUFunctions */ 1834 1835 1836 1837 1838 /* ################################## SysTick function ############################################ */ 1839 /** 1840 \ingroup CMSIS_Core_FunctionInterface 1841 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 1842 \brief Functions that configure the System. 1843 @{ 1844 */ 1845 1846 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 1847 1848 /** 1849 \brief System Tick Configuration 1850 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 1851 Counter is in free running mode to generate periodic interrupts. 1852 \param [in] ticks Number of ticks between two interrupts. 1853 \return 0 Function succeeded. 1854 \return 1 Function failed. 1855 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1856 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 1857 must contain a vendor-specific implementation of this function. 1858 */ 1859 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 1860 { 1861 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1862 { 1863 return (1UL); /* Reload value impossible */ 1864 } 1865 1866 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1867 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1868 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 1869 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1870 SysTick_CTRL_TICKINT_Msk | 1871 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1872 return (0UL); /* Function successful */ 1873 } 1874 1875 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1876 /** 1877 \brief System Tick Configuration (non-secure) 1878 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 1879 Counter is in free running mode to generate periodic interrupts. 1880 \param [in] ticks Number of ticks between two interrupts. 1881 \return 0 Function succeeded. 1882 \return 1 Function failed. 1883 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1884 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 1885 must contain a vendor-specific implementation of this function. 1886 1887 */ 1888 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 1889 { 1890 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1891 { 1892 return (1UL); /* Reload value impossible */ 1893 } 1894 1895 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1896 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1897 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 1898 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1899 SysTick_CTRL_TICKINT_Msk | 1900 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1901 return (0UL); /* Function successful */ 1902 } 1903 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1904 1905 #endif 1906 1907 /*@} end of CMSIS_Core_SysTickFunctions */ 1908 1909 1910 1911 1912 #ifdef __cplusplus 1913 } 1914 #endif 1915 1916 #endif /* __CORE_ARMV8MBL_H_DEPENDANT */ 1917 1918 #endif /* __CMSIS_GENERIC */