Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h (17754B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F1xx_HAL_DMA_H 21 #define __STM32F1xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f1xx_hal_def.h" 29 30 /** @addtogroup STM32F1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 50 from memory to memory or from peripheral to memory. 51 This parameter can be a value of @ref DMA_Data_transfer_direction */ 52 53 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 54 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 55 56 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 58 59 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 60 This parameter can be a value of @ref DMA_Peripheral_data_size */ 61 62 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 63 This parameter can be a value of @ref DMA_Memory_data_size */ 64 65 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 66 This parameter can be a value of @ref DMA_mode 67 @note The circular buffer mode cannot be used if the memory-to-memory 68 data transfer is configured on the selected Channel */ 69 70 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 71 This parameter can be a value of @ref DMA_Priority_level */ 72 } DMA_InitTypeDef; 73 74 /** 75 * @brief HAL DMA State structures definition 76 */ 77 typedef enum 78 { 79 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 80 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 81 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 82 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ 83 }HAL_DMA_StateTypeDef; 84 85 /** 86 * @brief HAL DMA Error Code structure definition 87 */ 88 typedef enum 89 { 90 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 91 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 92 }HAL_DMA_LevelCompleteTypeDef; 93 94 /** 95 * @brief HAL DMA Callback ID structure definition 96 */ 97 typedef enum 98 { 99 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 100 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 101 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 102 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 103 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 104 105 }HAL_DMA_CallbackIDTypeDef; 106 107 /** 108 * @brief DMA handle Structure definition 109 */ 110 typedef struct __DMA_HandleTypeDef 111 { 112 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 113 114 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 115 116 HAL_LockTypeDef Lock; /*!< DMA locking object */ 117 118 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 119 120 void *Parent; /*!< Parent object state */ 121 122 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 123 124 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 125 126 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 127 128 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 129 130 __IO uint32_t ErrorCode; /*!< DMA Error code */ 131 132 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 133 134 uint32_t ChannelIndex; /*!< DMA Channel Index */ 135 136 } DMA_HandleTypeDef; 137 /** 138 * @} 139 */ 140 141 /* Exported constants --------------------------------------------------------*/ 142 143 /** @defgroup DMA_Exported_Constants DMA Exported Constants 144 * @{ 145 */ 146 147 /** @defgroup DMA_Error_Code DMA Error Code 148 * @{ 149 */ 150 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 151 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 152 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ 153 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 154 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 155 /** 156 * @} 157 */ 158 159 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 160 * @{ 161 */ 162 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 163 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ 164 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ 165 166 /** 167 * @} 168 */ 169 170 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 171 * @{ 172 */ 173 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ 174 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 175 /** 176 * @} 177 */ 178 179 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 180 * @{ 181 */ 182 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ 183 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 184 /** 185 * @} 186 */ 187 188 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 189 * @{ 190 */ 191 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 192 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 193 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 194 /** 195 * @} 196 */ 197 198 /** @defgroup DMA_Memory_data_size DMA Memory data size 199 * @{ 200 */ 201 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 202 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 203 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ 204 /** 205 * @} 206 */ 207 208 /** @defgroup DMA_mode DMA mode 209 * @{ 210 */ 211 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 212 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ 213 /** 214 * @} 215 */ 216 217 /** @defgroup DMA_Priority_level DMA Priority level 218 * @{ 219 */ 220 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 221 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ 222 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ 223 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ 224 /** 225 * @} 226 */ 227 228 229 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 230 * @{ 231 */ 232 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) 233 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) 234 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) 235 /** 236 * @} 237 */ 238 239 /** @defgroup DMA_flag_definitions DMA flag definitions 240 * @{ 241 */ 242 #define DMA_FLAG_GL1 0x00000001U 243 #define DMA_FLAG_TC1 0x00000002U 244 #define DMA_FLAG_HT1 0x00000004U 245 #define DMA_FLAG_TE1 0x00000008U 246 #define DMA_FLAG_GL2 0x00000010U 247 #define DMA_FLAG_TC2 0x00000020U 248 #define DMA_FLAG_HT2 0x00000040U 249 #define DMA_FLAG_TE2 0x00000080U 250 #define DMA_FLAG_GL3 0x00000100U 251 #define DMA_FLAG_TC3 0x00000200U 252 #define DMA_FLAG_HT3 0x00000400U 253 #define DMA_FLAG_TE3 0x00000800U 254 #define DMA_FLAG_GL4 0x00001000U 255 #define DMA_FLAG_TC4 0x00002000U 256 #define DMA_FLAG_HT4 0x00004000U 257 #define DMA_FLAG_TE4 0x00008000U 258 #define DMA_FLAG_GL5 0x00010000U 259 #define DMA_FLAG_TC5 0x00020000U 260 #define DMA_FLAG_HT5 0x00040000U 261 #define DMA_FLAG_TE5 0x00080000U 262 #define DMA_FLAG_GL6 0x00100000U 263 #define DMA_FLAG_TC6 0x00200000U 264 #define DMA_FLAG_HT6 0x00400000U 265 #define DMA_FLAG_TE6 0x00800000U 266 #define DMA_FLAG_GL7 0x01000000U 267 #define DMA_FLAG_TC7 0x02000000U 268 #define DMA_FLAG_HT7 0x04000000U 269 #define DMA_FLAG_TE7 0x08000000U 270 /** 271 * @} 272 */ 273 274 /** 275 * @} 276 */ 277 278 279 /* Exported macros -----------------------------------------------------------*/ 280 /** @defgroup DMA_Exported_Macros DMA Exported Macros 281 * @{ 282 */ 283 284 /** @brief Reset DMA handle state. 285 * @param __HANDLE__: DMA handle 286 * @retval None 287 */ 288 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 289 290 /** 291 * @brief Enable the specified DMA Channel. 292 * @param __HANDLE__: DMA handle 293 * @retval None 294 */ 295 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) 296 297 /** 298 * @brief Disable the specified DMA Channel. 299 * @param __HANDLE__: DMA handle 300 * @retval None 301 */ 302 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) 303 304 305 /* Interrupt & Flag management */ 306 307 /** 308 * @brief Enables the specified DMA Channel interrupts. 309 * @param __HANDLE__: DMA handle 310 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 311 * This parameter can be any combination of the following values: 312 * @arg DMA_IT_TC: Transfer complete interrupt mask 313 * @arg DMA_IT_HT: Half transfer complete interrupt mask 314 * @arg DMA_IT_TE: Transfer error interrupt mask 315 * @retval None 316 */ 317 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) 318 319 /** 320 * @brief Disable the specified DMA Channel interrupts. 321 * @param __HANDLE__: DMA handle 322 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 323 * This parameter can be any combination of the following values: 324 * @arg DMA_IT_TC: Transfer complete interrupt mask 325 * @arg DMA_IT_HT: Half transfer complete interrupt mask 326 * @arg DMA_IT_TE: Transfer error interrupt mask 327 * @retval None 328 */ 329 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) 330 331 /** 332 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 333 * @param __HANDLE__: DMA handle 334 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 335 * This parameter can be one of the following values: 336 * @arg DMA_IT_TC: Transfer complete interrupt mask 337 * @arg DMA_IT_HT: Half transfer complete interrupt mask 338 * @arg DMA_IT_TE: Transfer error interrupt mask 339 * @retval The state of DMA_IT (SET or RESET). 340 */ 341 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 342 343 /** 344 * @brief Return the number of remaining data units in the current DMA Channel transfer. 345 * @param __HANDLE__: DMA handle 346 * @retval The number of remaining data units in the current DMA Channel transfer. 347 */ 348 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 349 350 /** 351 * @} 352 */ 353 354 /* Include DMA HAL Extension module */ 355 #include "stm32f1xx_hal_dma_ex.h" 356 357 /* Exported functions --------------------------------------------------------*/ 358 /** @addtogroup DMA_Exported_Functions 359 * @{ 360 */ 361 362 /** @addtogroup DMA_Exported_Functions_Group1 363 * @{ 364 */ 365 /* Initialization and de-initialization functions *****************************/ 366 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 367 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 368 /** 369 * @} 370 */ 371 372 /** @addtogroup DMA_Exported_Functions_Group2 373 * @{ 374 */ 375 /* IO operation functions *****************************************************/ 376 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 377 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 378 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 379 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 380 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); 381 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 382 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 383 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 384 385 /** 386 * @} 387 */ 388 389 /** @addtogroup DMA_Exported_Functions_Group3 390 * @{ 391 */ 392 /* Peripheral State and Error functions ***************************************/ 393 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 394 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 395 /** 396 * @} 397 */ 398 399 /** 400 * @} 401 */ 402 403 /* Private macros ------------------------------------------------------------*/ 404 /** @defgroup DMA_Private_Macros DMA Private Macros 405 * @{ 406 */ 407 408 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 409 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 410 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 411 412 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 413 414 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 415 ((STATE) == DMA_PINC_DISABLE)) 416 417 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 418 ((STATE) == DMA_MINC_DISABLE)) 419 420 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 421 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 422 ((SIZE) == DMA_PDATAALIGN_WORD)) 423 424 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 425 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 426 ((SIZE) == DMA_MDATAALIGN_WORD )) 427 428 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 429 ((MODE) == DMA_CIRCULAR)) 430 431 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 432 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 433 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 434 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 435 436 /** 437 * @} 438 */ 439 440 /* Private functions ---------------------------------------------------------*/ 441 442 /** 443 * @} 444 */ 445 446 /** 447 * @} 448 */ 449 450 #ifdef __cplusplus 451 } 452 #endif 453 454 #endif /* __STM32F1xx_HAL_DMA_H */ 455