Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c (19745B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_pwr.c 4 * @author MCD Application Team 5 * @brief PWR HAL module driver. 6 * 7 * This file provides firmware functions to manage the following 8 * functionalities of the Power Controller (PWR) peripheral: 9 * + Initialization/de-initialization functions 10 * + Peripheral Control functions 11 * 12 ****************************************************************************** 13 * @attention 14 * 15 * Copyright (c) 2016 STMicroelectronics. 16 * All rights reserved. 17 * 18 * This software is licensed under terms that can be found in the LICENSE file 19 * in the root directory of this software component. 20 * If no LICENSE file comes with this software, it is provided AS-IS. 21 * 22 ****************************************************************************** 23 */ 24 25 /* Includes ------------------------------------------------------------------*/ 26 #include "stm32f1xx_hal.h" 27 28 /** @addtogroup STM32F1xx_HAL_Driver 29 * @{ 30 */ 31 32 /** @defgroup PWR PWR 33 * @brief PWR HAL module driver 34 * @{ 35 */ 36 37 #ifdef HAL_PWR_MODULE_ENABLED 38 39 /* Private typedef -----------------------------------------------------------*/ 40 /* Private define ------------------------------------------------------------*/ 41 42 /** @defgroup PWR_Private_Constants PWR Private Constants 43 * @{ 44 */ 45 46 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask 47 * @{ 48 */ 49 #define PVD_MODE_IT 0x00010000U 50 #define PVD_MODE_EVT 0x00020000U 51 #define PVD_RISING_EDGE 0x00000001U 52 #define PVD_FALLING_EDGE 0x00000002U 53 /** 54 * @} 55 */ 56 57 /** @defgroup PWR_register_alias_address PWR Register alias address 58 * @{ 59 */ 60 /* ------------- PWR registers bit address in the alias region ---------------*/ 61 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 62 #define PWR_CR_OFFSET 0x00U 63 #define PWR_CSR_OFFSET 0x04U 64 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) 65 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) 66 /** 67 * @} 68 */ 69 70 /** @defgroup PWR_CR_register_alias PWR CR Register alias address 71 * @{ 72 */ 73 /* --- CR Register ---*/ 74 /* Alias word address of LPSDSR bit */ 75 #define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos 76 #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) 77 78 /* Alias word address of DBP bit */ 79 #define DBP_BIT_NUMBER PWR_CR_DBP_Pos 80 #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) 81 82 /* Alias word address of PVDE bit */ 83 #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos 84 #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) 85 86 /** 87 * @} 88 */ 89 90 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address 91 * @{ 92 */ 93 94 /* --- CSR Register ---*/ 95 /* Alias word address of EWUP1 bit */ 96 #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) 97 /** 98 * @} 99 */ 100 101 /** 102 * @} 103 */ 104 105 /* Private variables ---------------------------------------------------------*/ 106 /* Private function prototypes -----------------------------------------------*/ 107 /** @defgroup PWR_Private_Functions PWR Private Functions 108 * brief WFE cortex command overloaded for HAL_PWR_EnterSTOPMode usage only (see Workaround section) 109 * @{ 110 */ 111 static void PWR_OverloadWfe(void); 112 113 /* Private functions ---------------------------------------------------------*/ 114 __NOINLINE 115 static void PWR_OverloadWfe(void) 116 { 117 __asm volatile( "wfe" ); 118 __asm volatile( "nop" ); 119 } 120 121 /** 122 * @} 123 */ 124 125 /** @defgroup PWR_Exported_Functions PWR Exported Functions 126 * @{ 127 */ 128 129 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 130 * @brief Initialization and de-initialization functions 131 * 132 @verbatim 133 =============================================================================== 134 ##### Initialization and de-initialization functions ##### 135 =============================================================================== 136 [..] 137 After reset, the backup domain (RTC registers, RTC backup data 138 registers) is protected against possible unwanted 139 write accesses. 140 To enable access to the RTC Domain and RTC registers, proceed as follows: 141 (+) Enable the Power Controller (PWR) APB1 interface clock using the 142 __HAL_RCC_PWR_CLK_ENABLE() macro. 143 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. 144 145 @endverbatim 146 * @{ 147 */ 148 149 /** 150 * @brief Deinitializes the PWR peripheral registers to their default reset values. 151 * @retval None 152 */ 153 void HAL_PWR_DeInit(void) 154 { 155 __HAL_RCC_PWR_FORCE_RESET(); 156 __HAL_RCC_PWR_RELEASE_RESET(); 157 } 158 159 /** 160 * @brief Enables access to the backup domain (RTC registers, RTC 161 * backup data registers ). 162 * @note If the HSE divided by 128 is used as the RTC clock, the 163 * Backup Domain Access should be kept enabled. 164 * @retval None 165 */ 166 void HAL_PWR_EnableBkUpAccess(void) 167 { 168 /* Enable access to RTC and backup registers */ 169 *(__IO uint32_t*) CR_DBP_BB = (uint32_t) ENABLE; 170 } 171 172 /** 173 * @brief Disables access to the backup domain (RTC registers, RTC 174 * backup data registers). 175 * @note If the HSE divided by 128 is used as the RTC clock, the 176 * Backup Domain Access should be kept enabled. 177 * @retval None 178 */ 179 void HAL_PWR_DisableBkUpAccess(void) 180 { 181 /* Disable access to RTC and backup registers */ 182 *(__IO uint32_t*) CR_DBP_BB = (uint32_t) DISABLE; 183 } 184 185 /** 186 * @} 187 */ 188 189 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 190 * @brief Low Power modes configuration functions 191 * 192 @verbatim 193 =============================================================================== 194 ##### Peripheral Control functions ##### 195 =============================================================================== 196 197 *** PVD configuration *** 198 ========================= 199 [..] 200 (+) The PVD is used to monitor the VDD power supply by comparing it to a 201 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 202 203 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 204 than the PVD threshold. This event is internally connected to the EXTI 205 line16 and can generate an interrupt if enabled. This is done through 206 __HAL_PVD_EXTI_ENABLE_IT() macro. 207 (+) The PVD is stopped in Standby mode. 208 209 *** WakeUp pin configuration *** 210 ================================ 211 [..] 212 (+) WakeUp pin is used to wake up the system from Standby mode. This pin is 213 forced in input pull-down configuration and is active on rising edges. 214 (+) There is one WakeUp pin: 215 WakeUp Pin 1 on PA.00. 216 217 [..] 218 219 *** Low Power modes configuration *** 220 ===================================== 221 [..] 222 The device features 3 low-power modes: 223 (+) Sleep mode: CPU clock off, all peripherals including Cortex-M3 core peripherals like 224 NVIC, SysTick, etc. are kept running 225 (+) Stop mode: All clocks are stopped 226 (+) Standby mode: 1.8V domain powered off 227 228 229 *** Sleep mode *** 230 ================== 231 [..] 232 (+) Entry: 233 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) 234 functions with 235 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 236 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 237 238 (+) Exit: 239 (++) WFI entry mode, Any peripheral interrupt acknowledged by the nested vectored interrupt 240 controller (NVIC) can wake up the device from Sleep mode. 241 (++) WFE entry mode, Any wakeup event can wake up the device from Sleep mode. 242 (+++) Any peripheral interrupt w/o NVIC configuration & SEVONPEND bit set in the Cortex (HAL_PWR_EnableSEVOnPend) 243 (+++) Any EXTI Line (Internal or External) configured in Event mode 244 245 *** Stop mode *** 246 ================= 247 [..] 248 The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral 249 clock gating. The voltage regulator can be configured either in normal or low-power mode. 250 In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC 251 oscillators are disabled. SRAM and register contents are preserved. 252 In Stop mode, all I/O pins keep the same state as in Run mode. 253 254 (+) Entry: 255 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPENTRY_WFx ) 256 function with: 257 (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON. 258 (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON. 259 (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction 260 (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction 261 (+) Exit: 262 (++) WFI entry mode, Any EXTI Line (Internal or External) configured in Interrupt mode with NVIC configured 263 (++) WFE entry mode, Any EXTI Line (Internal or External) configured in Event mode. 264 265 *** Standby mode *** 266 ==================== 267 [..] 268 The Standby mode allows to achieve the lowest power consumption. It is based on the 269 Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is 270 consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also 271 switched off. SRAM and register contents are lost except for registers in the Backup domain 272 and Standby circuitry 273 274 (+) Entry: 275 (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. 276 (+) Exit: 277 (++) WKUP pin rising edge, RTC alarm event rising edge, external Reset in 278 NRSTpin, IWDG Reset 279 280 *** Auto-wakeup (AWU) from low-power mode *** 281 ============================================= 282 [..] 283 284 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, 285 without depending on an external interrupt (Auto-wakeup mode). 286 287 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes 288 289 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 290 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. 291 292 *** PWR Workarounds linked to Silicon Limitation *** 293 ==================================================== 294 [..] 295 Below the list of all silicon limitations known on STM32F1xx prouct. 296 297 (#)Workarounds Implemented inside PWR HAL Driver 298 (##)Debugging Stop mode with WFE entry - overloaded the WFE by an internal function 299 300 @endverbatim 301 * @{ 302 */ 303 304 /** 305 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 306 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration 307 * information for the PVD. 308 * @note Refer to the electrical characteristics of your device datasheet for 309 * more details about the voltage threshold corresponding to each 310 * detection level. 311 * @retval None 312 */ 313 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 314 { 315 /* Check the parameters */ 316 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 317 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 318 319 /* Set PLS[7:5] bits according to PVDLevel value */ 320 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 321 322 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 323 __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 324 __HAL_PWR_PVD_EXTI_DISABLE_IT(); 325 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 326 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); 327 328 /* Configure interrupt mode */ 329 if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { 330 __HAL_PWR_PVD_EXTI_ENABLE_IT(); 331 } 332 333 /* Configure event mode */ 334 if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { 335 __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 336 } 337 338 /* Configure the edge */ 339 if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { 340 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 341 } 342 343 if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) { 344 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 345 } 346 } 347 348 /** 349 * @brief Enables the Power Voltage Detector(PVD). 350 * @retval None 351 */ 352 void HAL_PWR_EnablePVD(void) 353 { 354 /* Enable the power voltage detector */ 355 *(__IO uint32_t*) CR_PVDE_BB = (uint32_t) ENABLE; 356 } 357 358 /** 359 * @brief Disables the Power Voltage Detector(PVD). 360 * @retval None 361 */ 362 void HAL_PWR_DisablePVD(void) 363 { 364 /* Disable the power voltage detector */ 365 *(__IO uint32_t*) CR_PVDE_BB = (uint32_t) DISABLE; 366 } 367 368 /** 369 * @brief Enables the WakeUp PINx functionality. 370 * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. 371 * This parameter can be one of the following values: 372 * @arg PWR_WAKEUP_PIN1 373 * @retval None 374 */ 375 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) 376 { 377 /* Check the parameter */ 378 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 379 /* Enable the EWUPx pin */ 380 *(__IO uint32_t*) CSR_EWUP_BB(WakeUpPinx) = (uint32_t) ENABLE; 381 } 382 383 /** 384 * @brief Disables the WakeUp PINx functionality. 385 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. 386 * This parameter can be one of the following values: 387 * @arg PWR_WAKEUP_PIN1 388 * @retval None 389 */ 390 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) 391 { 392 /* Check the parameter */ 393 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 394 /* Disable the EWUPx pin */ 395 *(__IO uint32_t*) CSR_EWUP_BB(WakeUpPinx) = (uint32_t) DISABLE; 396 } 397 398 /** 399 * @brief Enters Sleep mode. 400 * @note In Sleep mode, all I/O pins keep the same state as in Run mode. 401 * @param Regulator: Regulator state as no effect in SLEEP mode - allows to support portability from legacy software 402 * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. 403 * When WFI entry is used, tick interrupt have to be disabled if not desired as 404 * the interrupt wake up source. 405 * This parameter can be one of the following values: 406 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 407 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 408 * @retval None 409 */ 410 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) 411 { 412 /* Check the parameters */ 413 /* No check on Regulator because parameter not used in SLEEP mode */ 414 /* Prevent unused argument(s) compilation warning */ 415 UNUSED(Regulator); 416 417 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); 418 419 /* Clear SLEEPDEEP bit of Cortex System Control Register */ 420 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 421 422 /* Select SLEEP mode entry -------------------------------------------------*/ 423 if (SLEEPEntry == PWR_SLEEPENTRY_WFI) { 424 /* Request Wait For Interrupt */ 425 __WFI(); 426 } else { 427 /* Request Wait For Event */ 428 __SEV(); 429 __WFE(); 430 __WFE(); 431 } 432 } 433 434 /** 435 * @brief Enters Stop mode. 436 * @note In Stop mode, all I/O pins keep the same state as in Run mode. 437 * @note When exiting Stop mode by using an interrupt or a wakeup event, 438 * HSI RC oscillator is selected as system clock. 439 * @note When the voltage regulator operates in low power mode, an additional 440 * startup delay is incurred when waking up from Stop mode. 441 * By keeping the internal regulator ON during Stop mode, the consumption 442 * is higher although the startup time is reduced. 443 * @param Regulator: Specifies the regulator state in Stop mode. 444 * This parameter can be one of the following values: 445 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON 446 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON 447 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. 448 * This parameter can be one of the following values: 449 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction 450 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction 451 * @retval None 452 */ 453 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) 454 { 455 /* Check the parameters */ 456 assert_param(IS_PWR_REGULATOR(Regulator)); 457 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 458 459 /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */ 460 CLEAR_BIT(PWR->CR, PWR_CR_PDDS); 461 462 /* Select the voltage regulator mode by setting LPDS bit in PWR register according to Regulator parameter value */ 463 MODIFY_REG(PWR->CR, PWR_CR_LPDS, Regulator); 464 465 /* Set SLEEPDEEP bit of Cortex System Control Register */ 466 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 467 468 /* Select Stop mode entry --------------------------------------------------*/ 469 if (STOPEntry == PWR_STOPENTRY_WFI) { 470 /* Request Wait For Interrupt */ 471 __WFI(); 472 } else { 473 /* Request Wait For Event */ 474 __SEV(); 475 PWR_OverloadWfe(); /* WFE redefine locally */ 476 PWR_OverloadWfe(); /* WFE redefine locally */ 477 } 478 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 479 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 480 } 481 482 /** 483 * @brief Enters Standby mode. 484 * @note In Standby mode, all I/O pins are high impedance except for: 485 * - Reset pad (still available) 486 * - TAMPER pin if configured for tamper or calibration out. 487 * - WKUP pin (PA0) if enabled. 488 * @retval None 489 */ 490 void HAL_PWR_EnterSTANDBYMode(void) 491 { 492 /* Select Standby mode */ 493 SET_BIT(PWR->CR, PWR_CR_PDDS); 494 495 /* Set SLEEPDEEP bit of Cortex System Control Register */ 496 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 497 498 /* This option is used to ensure that store operations are completed */ 499 #if defined ( __CC_ARM) 500 __force_stores(); 501 #endif 502 /* Request Wait For Interrupt */ 503 __WFI(); 504 } 505 506 /** 507 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 508 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 509 * re-enters SLEEP mode when an interruption handling is over. 510 * Setting this bit is useful when the processor is expected to run only on 511 * interruptions handling. 512 * @retval None 513 */ 514 void HAL_PWR_EnableSleepOnExit(void) 515 { 516 /* Set SLEEPONEXIT bit of Cortex System Control Register */ 517 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 518 } 519 520 /** 521 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 522 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 523 * re-enters SLEEP mode when an interruption handling is over. 524 * @retval None 525 */ 526 void HAL_PWR_DisableSleepOnExit(void) 527 { 528 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 529 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 530 } 531 532 /** 533 * @brief Enables CORTEX M3 SEVONPEND bit. 534 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 535 * WFE to wake up when an interrupt moves from inactive to pended. 536 * @retval None 537 */ 538 void HAL_PWR_EnableSEVOnPend(void) 539 { 540 /* Set SEVONPEND bit of Cortex System Control Register */ 541 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 542 } 543 544 /** 545 * @brief Disables CORTEX M3 SEVONPEND bit. 546 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 547 * WFE to wake up when an interrupt moves from inactive to pended. 548 * @retval None 549 */ 550 void HAL_PWR_DisableSEVOnPend(void) 551 { 552 /* Clear SEVONPEND bit of Cortex System Control Register */ 553 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 554 } 555 556 /** 557 * @brief This function handles the PWR PVD interrupt request. 558 * @note This API should be called under the PVD_IRQHandler(). 559 * @retval None 560 */ 561 void HAL_PWR_PVD_IRQHandler(void) 562 { 563 /* Check PWR exti flag */ 564 if (__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) { 565 /* PWR PVD interrupt user callback */ 566 HAL_PWR_PVDCallback(); 567 568 /* Clear PWR Exti pending bit */ 569 __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 570 } 571 } 572 573 /** 574 * @brief PWR PVD interrupt callback 575 * @retval None 576 */ 577 __weak void HAL_PWR_PVDCallback(void) 578 { 579 /* NOTE : This function Should not be modified, when the callback is needed, 580 the HAL_PWR_PVDCallback could be implemented in the user file 581 */ 582 } 583 584 /** 585 * @} 586 */ 587 588 /** 589 * @} 590 */ 591 592 #endif /* HAL_PWR_MODULE_ENABLED */ 593 /** 594 * @} 595 */ 596 597 /** 598 * @} 599 */