Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h (84505B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F1xx_LL_RCC_H 20 #define __STM32F1xx_LL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f1xx.h" 28 29 /** @addtogroup STM32F1xx_LL_Driver 30 * @{ 31 */ 32 33 #if defined(RCC) 34 35 /** @defgroup RCC_LL RCC 36 * @{ 37 */ 38 39 /* Private types -------------------------------------------------------------*/ 40 /* Private variables ---------------------------------------------------------*/ 41 /* Private constants ---------------------------------------------------------*/ 42 /* Private macros ------------------------------------------------------------*/ 43 #if defined(USE_FULL_LL_DRIVER) 44 /** @defgroup RCC_LL_Private_Macros RCC Private Macros 45 * @{ 46 */ 47 /** 48 * @} 49 */ 50 #endif /*USE_FULL_LL_DRIVER*/ 51 /* Exported types ------------------------------------------------------------*/ 52 #if defined(USE_FULL_LL_DRIVER) 53 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 54 * @{ 55 */ 56 57 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 58 * @{ 59 */ 60 61 /** 62 * @brief RCC Clocks Frequency Structure 63 */ 64 typedef struct 65 { 66 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ 67 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ 68 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ 69 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ 70 }LL_RCC_ClocksTypeDef; 71 72 /** 73 * @} 74 */ 75 76 /** 77 * @} 78 */ 79 #endif /* USE_FULL_LL_DRIVER */ 80 81 /* Exported constants --------------------------------------------------------*/ 82 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 83 * @{ 84 */ 85 86 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 87 * @brief Defines used to adapt values of different oscillators 88 * @note These values could be modified in the user environment according to 89 * HW set-up. 90 * @{ 91 */ 92 #if !defined (HSE_VALUE) 93 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ 94 #endif /* HSE_VALUE */ 95 96 #if !defined (HSI_VALUE) 97 #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ 98 #endif /* HSI_VALUE */ 99 100 #if !defined (LSE_VALUE) 101 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ 102 #endif /* LSE_VALUE */ 103 104 #if !defined (LSI_VALUE) 105 #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ 106 #endif /* LSI_VALUE */ 107 /** 108 * @} 109 */ 110 111 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines 112 * @brief Flags defines which can be used with LL_RCC_WriteReg function 113 * @{ 114 */ 115 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ 116 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ 117 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ 118 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ 119 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ 120 #define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */ 121 #define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */ 122 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ 123 /** 124 * @} 125 */ 126 127 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines 128 * @brief Flags defines which can be used with LL_RCC_ReadReg function 129 * @{ 130 */ 131 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ 132 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ 133 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ 134 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ 135 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ 136 #define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */ 137 #define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ 138 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ 139 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ 140 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ 141 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ 142 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 143 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 144 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ 145 /** 146 * @} 147 */ 148 149 /** @defgroup RCC_LL_EC_IT IT Defines 150 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions 151 * @{ 152 */ 153 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ 154 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ 155 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ 156 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ 157 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ 158 #define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */ 159 #define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */ 160 /** 161 * @} 162 */ 163 164 #if defined(RCC_CFGR2_PREDIV2) 165 /** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor 166 * @{ 167 */ 168 #define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ 169 #define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ 170 #define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ 171 #define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ 172 #define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ 173 #define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ 174 #define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ 175 #define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ 176 #define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ 177 #define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ 178 #define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ 179 #define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ 180 #define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ 181 #define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ 182 #define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ 183 #define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ 184 /** 185 * @} 186 */ 187 188 #endif /* RCC_CFGR2_PREDIV2 */ 189 190 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 191 * @{ 192 */ 193 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 194 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 195 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 196 /** 197 * @} 198 */ 199 200 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 201 * @{ 202 */ 203 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 204 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 205 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 206 /** 207 * @} 208 */ 209 210 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler 211 * @{ 212 */ 213 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 214 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 215 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 216 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 217 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 218 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 219 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 220 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 221 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 227 * @{ 228 */ 229 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 230 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 231 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 232 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 233 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) 239 * @{ 240 */ 241 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ 242 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ 243 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ 244 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ 245 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ 246 /** 247 * @} 248 */ 249 250 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection 251 * @{ 252 */ 253 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK /*!< MCO output disabled, no clock on MCO */ 254 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK /*!< SYSCLK selection as MCO source */ 255 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI /*!< HSI selection as MCO source */ 256 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE /*!< HSE selection as MCO source */ 257 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!< PLL clock divided by 2*/ 258 #if defined(RCC_CFGR_MCO_PLL2CLK) 259 #define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCO_PLL2CLK /*!< PLL2 clock selected as MCO source*/ 260 #endif /* RCC_CFGR_MCO_PLL2CLK */ 261 #if defined(RCC_CFGR_MCO_PLL3CLK_DIV2) 262 #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/ 263 #endif /* RCC_CFGR_MCO_PLL3CLK_DIV2 */ 264 #if defined(RCC_CFGR_MCO_EXT_HSE) 265 #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCO_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ 266 #endif /* RCC_CFGR_MCO_EXT_HSE */ 267 #if defined(RCC_CFGR_MCO_PLL3CLK) 268 #define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCO_PLL3CLK /*!< PLLI2S clock selected as MCO source */ 269 #endif /* RCC_CFGR_MCO_PLL3CLK */ 270 /** 271 * @} 272 */ 273 274 #if defined(USE_FULL_LL_DRIVER) 275 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 276 * @{ 277 */ 278 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ 279 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 280 /** 281 * @} 282 */ 283 #endif /* USE_FULL_LL_DRIVER */ 284 285 #if defined(RCC_CFGR2_I2S2SRC) 286 /** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection 287 * @{ 288 */ 289 #define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */ 290 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */ 291 #define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */ 292 #define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */ 293 /** 294 * @} 295 */ 296 #endif /* RCC_CFGR2_I2S2SRC */ 297 298 #if defined(USB_OTG_FS) || defined(USB) 299 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 300 * @{ 301 */ 302 #if defined(RCC_CFGR_USBPRE) 303 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ 304 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */ 305 #endif /*RCC_CFGR_USBPRE*/ 306 #if defined(RCC_CFGR_OTGFSPRE) 307 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ 308 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */ 309 #endif /*RCC_CFGR_OTGFSPRE*/ 310 /** 311 * @} 312 */ 313 #endif /* USB_OTG_FS || USB */ 314 315 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection 316 * @{ 317 */ 318 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/ 319 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/ 320 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/ 321 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/ 322 /** 323 * @} 324 */ 325 326 #if defined(RCC_CFGR2_I2S2SRC) 327 /** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source 328 * @{ 329 */ 330 #define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */ 331 #define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */ 332 /** 333 * @} 334 */ 335 336 #endif /* RCC_CFGR2_I2S2SRC */ 337 338 #if defined(USB_OTG_FS) || defined(USB) 339 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 340 * @{ 341 */ 342 #define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */ 343 /** 344 * @} 345 */ 346 347 #endif /* USB_OTG_FS || USB */ 348 349 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source 350 * @{ 351 */ 352 #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ 353 /** 354 * @} 355 */ 356 357 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 358 * @{ 359 */ 360 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 361 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 362 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 363 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ 364 /** 365 * @} 366 */ 367 368 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor 369 * @{ 370 */ 371 #if defined(RCC_CFGR_PLLMULL2) 372 #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */ 373 #endif /*RCC_CFGR_PLLMULL2*/ 374 #if defined(RCC_CFGR_PLLMULL3) 375 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */ 376 #endif /*RCC_CFGR_PLLMULL3*/ 377 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */ 378 #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */ 379 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */ 380 #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */ 381 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */ 382 #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */ 383 #if defined(RCC_CFGR_PLLMULL6_5) 384 #define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */ 385 #else 386 #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */ 387 #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */ 388 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */ 389 #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */ 390 #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */ 391 #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */ 392 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */ 393 #endif /*RCC_CFGR_PLLMULL6_5*/ 394 /** 395 * @} 396 */ 397 398 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE 399 * @{ 400 */ 401 #define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ 402 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */ 403 #if defined(RCC_CFGR2_PREDIV1SRC) 404 #define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */ 405 #endif /*RCC_CFGR2_PREDIV1SRC*/ 406 407 #if defined(RCC_CFGR2_PREDIV1) 408 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */ 409 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ 410 #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ 411 #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ 412 #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ 413 #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ 414 #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ 415 #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ 416 #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ 417 #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ 418 #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ 419 #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ 420 #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ 421 #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ 422 #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ 423 #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ 424 #if defined(RCC_CFGR2_PREDIV1SRC) 425 #define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */ 426 #define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */ 427 #define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */ 428 #define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */ 429 #define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */ 430 #define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */ 431 #define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */ 432 #define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */ 433 #define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */ 434 #define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */ 435 #define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */ 436 #define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */ 437 #define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */ 438 #define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */ 439 #define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */ 440 #define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */ 441 #endif /*RCC_CFGR2_PREDIV1SRC*/ 442 #else 443 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */ 444 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */ 445 #endif /*RCC_CFGR2_PREDIV1*/ 446 /** 447 * @} 448 */ 449 450 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor 451 * @{ 452 */ 453 #if defined(RCC_CFGR2_PREDIV1) 454 #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */ 455 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */ 456 #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */ 457 #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */ 458 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */ 459 #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */ 460 #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */ 461 #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */ 462 #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */ 463 #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */ 464 #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */ 465 #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */ 466 #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */ 467 #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */ 468 #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */ 469 #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */ 470 #else 471 #define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */ 472 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */ 473 #endif /*RCC_CFGR2_PREDIV1*/ 474 /** 475 * @} 476 */ 477 478 #if defined(RCC_PLLI2S_SUPPORT) 479 /** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL 480 * @{ 481 */ 482 #define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ 483 #define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ 484 #define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ 485 #define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ 486 #define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ 487 #define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ 488 #define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ 489 #define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ 490 #define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ 491 /** 492 * @} 493 */ 494 495 #endif /* RCC_PLLI2S_SUPPORT */ 496 497 #if defined(RCC_PLL2_SUPPORT) 498 /** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL 499 * @{ 500 */ 501 #define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ 502 #define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ 503 #define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ 504 #define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ 505 #define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ 506 #define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ 507 #define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ 508 #define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ 509 #define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ 510 /** 511 * @} 512 */ 513 514 #endif /* RCC_PLL2_SUPPORT */ 515 516 /** 517 * @} 518 */ 519 520 /* Exported macro ------------------------------------------------------------*/ 521 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 522 * @{ 523 */ 524 525 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 526 * @{ 527 */ 528 529 /** 530 * @brief Write a value in RCC register 531 * @param __REG__ Register to be written 532 * @param __VALUE__ Value to be written in the register 533 * @retval None 534 */ 535 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 536 537 /** 538 * @brief Read a value in RCC register 539 * @param __REG__ Register to be read 540 * @retval Register value 541 */ 542 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 543 /** 544 * @} 545 */ 546 547 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 548 * @{ 549 */ 550 551 #if defined(RCC_CFGR_PLLMULL6_5) 552 /** 553 * @brief Helper macro to calculate the PLLCLK frequency 554 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); 555 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1) 556 * @param __PLLMUL__: This parameter can be one of the following values: 557 * @arg @ref LL_RCC_PLL_MUL_4 558 * @arg @ref LL_RCC_PLL_MUL_5 559 * @arg @ref LL_RCC_PLL_MUL_6 560 * @arg @ref LL_RCC_PLL_MUL_7 561 * @arg @ref LL_RCC_PLL_MUL_8 562 * @arg @ref LL_RCC_PLL_MUL_9 563 * @arg @ref LL_RCC_PLL_MUL_6_5 564 * @retval PLL clock frequency (in Hz) 565 */ 566 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ 567 (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \ 568 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\ 569 (((__INPUTFREQ__) * 13U) / 2U)) 570 571 #else 572 /** 573 * @brief Helper macro to calculate the PLLCLK frequency 574 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ()); 575 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2) 576 * @param __PLLMUL__: This parameter can be one of the following values: 577 * @arg @ref LL_RCC_PLL_MUL_2 578 * @arg @ref LL_RCC_PLL_MUL_3 579 * @arg @ref LL_RCC_PLL_MUL_4 580 * @arg @ref LL_RCC_PLL_MUL_5 581 * @arg @ref LL_RCC_PLL_MUL_6 582 * @arg @ref LL_RCC_PLL_MUL_7 583 * @arg @ref LL_RCC_PLL_MUL_8 584 * @arg @ref LL_RCC_PLL_MUL_9 585 * @arg @ref LL_RCC_PLL_MUL_10 586 * @arg @ref LL_RCC_PLL_MUL_11 587 * @arg @ref LL_RCC_PLL_MUL_12 588 * @arg @ref LL_RCC_PLL_MUL_13 589 * @arg @ref LL_RCC_PLL_MUL_14 590 * @arg @ref LL_RCC_PLL_MUL_15 591 * @arg @ref LL_RCC_PLL_MUL_16 592 * @retval PLL clock frequency (in Hz) 593 */ 594 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U)) 595 #endif /* RCC_CFGR_PLLMULL6_5 */ 596 597 #if defined(RCC_PLLI2S_SUPPORT) 598 /** 599 * @brief Helper macro to calculate the PLLI2S frequency 600 * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); 601 * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value) 602 * @param __PLLI2SMUL__: This parameter can be one of the following values: 603 * @arg @ref LL_RCC_PLLI2S_MUL_8 604 * @arg @ref LL_RCC_PLLI2S_MUL_9 605 * @arg @ref LL_RCC_PLLI2S_MUL_10 606 * @arg @ref LL_RCC_PLLI2S_MUL_11 607 * @arg @ref LL_RCC_PLLI2S_MUL_12 608 * @arg @ref LL_RCC_PLLI2S_MUL_13 609 * @arg @ref LL_RCC_PLLI2S_MUL_14 610 * @arg @ref LL_RCC_PLLI2S_MUL_16 611 * @arg @ref LL_RCC_PLLI2S_MUL_20 612 * @param __PLLI2SDIV__: This parameter can be one of the following values: 613 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 614 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 615 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 616 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 617 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 618 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 619 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 620 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 621 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 622 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 623 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 624 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 625 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 626 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 627 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 628 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 629 * @retval PLLI2S clock frequency (in Hz) 630 */ 631 #define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) 632 #endif /* RCC_PLLI2S_SUPPORT */ 633 634 #if defined(RCC_PLL2_SUPPORT) 635 /** 636 * @brief Helper macro to calculate the PLL2 frequency 637 * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); 638 * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value) 639 * @param __PLL2MUL__: This parameter can be one of the following values: 640 * @arg @ref LL_RCC_PLL2_MUL_8 641 * @arg @ref LL_RCC_PLL2_MUL_9 642 * @arg @ref LL_RCC_PLL2_MUL_10 643 * @arg @ref LL_RCC_PLL2_MUL_11 644 * @arg @ref LL_RCC_PLL2_MUL_12 645 * @arg @ref LL_RCC_PLL2_MUL_13 646 * @arg @ref LL_RCC_PLL2_MUL_14 647 * @arg @ref LL_RCC_PLL2_MUL_16 648 * @arg @ref LL_RCC_PLL2_MUL_20 649 * @param __PLL2DIV__: This parameter can be one of the following values: 650 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 651 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 652 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 653 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 654 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 655 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 656 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 657 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 658 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 659 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 660 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 661 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 662 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 663 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 664 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 665 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 666 * @retval PLL2 clock frequency (in Hz) 667 */ 668 #define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) 669 #endif /* RCC_PLL2_SUPPORT */ 670 671 /** 672 * @brief Helper macro to calculate the HCLK frequency 673 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler 674 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) 675 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) 676 * @param __AHBPRESCALER__: This parameter can be one of the following values: 677 * @arg @ref LL_RCC_SYSCLK_DIV_1 678 * @arg @ref LL_RCC_SYSCLK_DIV_2 679 * @arg @ref LL_RCC_SYSCLK_DIV_4 680 * @arg @ref LL_RCC_SYSCLK_DIV_8 681 * @arg @ref LL_RCC_SYSCLK_DIV_16 682 * @arg @ref LL_RCC_SYSCLK_DIV_64 683 * @arg @ref LL_RCC_SYSCLK_DIV_128 684 * @arg @ref LL_RCC_SYSCLK_DIV_256 685 * @arg @ref LL_RCC_SYSCLK_DIV_512 686 * @retval HCLK clock frequency (in Hz) 687 */ 688 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) 689 690 /** 691 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 692 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler 693 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) 694 * @param __HCLKFREQ__ HCLK frequency 695 * @param __APB1PRESCALER__: This parameter can be one of the following values: 696 * @arg @ref LL_RCC_APB1_DIV_1 697 * @arg @ref LL_RCC_APB1_DIV_2 698 * @arg @ref LL_RCC_APB1_DIV_4 699 * @arg @ref LL_RCC_APB1_DIV_8 700 * @arg @ref LL_RCC_APB1_DIV_16 701 * @retval PCLK1 clock frequency (in Hz) 702 */ 703 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) 704 705 /** 706 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 707 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler 708 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) 709 * @param __HCLKFREQ__ HCLK frequency 710 * @param __APB2PRESCALER__: This parameter can be one of the following values: 711 * @arg @ref LL_RCC_APB2_DIV_1 712 * @arg @ref LL_RCC_APB2_DIV_2 713 * @arg @ref LL_RCC_APB2_DIV_4 714 * @arg @ref LL_RCC_APB2_DIV_8 715 * @arg @ref LL_RCC_APB2_DIV_16 716 * @retval PCLK2 clock frequency (in Hz) 717 */ 718 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) 719 720 /** 721 * @} 722 */ 723 724 /** 725 * @} 726 */ 727 728 /* Exported functions --------------------------------------------------------*/ 729 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 730 * @{ 731 */ 732 733 /** @defgroup RCC_LL_EF_HSE HSE 734 * @{ 735 */ 736 737 /** 738 * @brief Enable the Clock Security System. 739 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS 740 * @retval None 741 */ 742 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 743 { 744 SET_BIT(RCC->CR, RCC_CR_CSSON); 745 } 746 747 /** 748 * @brief Enable HSE external oscillator (HSE Bypass) 749 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 750 * @retval None 751 */ 752 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 753 { 754 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 755 } 756 757 /** 758 * @brief Disable HSE external oscillator (HSE Bypass) 759 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 760 * @retval None 761 */ 762 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 763 { 764 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 765 } 766 767 /** 768 * @brief Enable HSE crystal oscillator (HSE ON) 769 * @rmtoll CR HSEON LL_RCC_HSE_Enable 770 * @retval None 771 */ 772 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 773 { 774 SET_BIT(RCC->CR, RCC_CR_HSEON); 775 } 776 777 /** 778 * @brief Disable HSE crystal oscillator (HSE ON) 779 * @rmtoll CR HSEON LL_RCC_HSE_Disable 780 * @retval None 781 */ 782 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 783 { 784 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 785 } 786 787 /** 788 * @brief Check if HSE oscillator Ready 789 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 790 * @retval State of bit (1 or 0). 791 */ 792 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 793 { 794 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); 795 } 796 797 #if defined(RCC_CFGR2_PREDIV2) 798 /** 799 * @brief Get PREDIV2 division factor 800 * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2 801 * @retval Returned value can be one of the following values: 802 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 803 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 804 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 805 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 806 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 807 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 808 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 809 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 810 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 811 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 812 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 813 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 814 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 815 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 816 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 817 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 818 */ 819 __STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void) 820 { 821 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); 822 } 823 #endif /* RCC_CFGR2_PREDIV2 */ 824 825 /** 826 * @} 827 */ 828 829 /** @defgroup RCC_LL_EF_HSI HSI 830 * @{ 831 */ 832 833 /** 834 * @brief Enable HSI oscillator 835 * @rmtoll CR HSION LL_RCC_HSI_Enable 836 * @retval None 837 */ 838 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 839 { 840 SET_BIT(RCC->CR, RCC_CR_HSION); 841 } 842 843 /** 844 * @brief Disable HSI oscillator 845 * @rmtoll CR HSION LL_RCC_HSI_Disable 846 * @retval None 847 */ 848 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 849 { 850 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 851 } 852 853 /** 854 * @brief Check if HSI clock is ready 855 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 856 * @retval State of bit (1 or 0). 857 */ 858 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 859 { 860 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); 861 } 862 863 /** 864 * @brief Get HSI Calibration value 865 * @note When HSITRIM is written, HSICAL is updated with the sum of 866 * HSITRIM and the factory trim value 867 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration 868 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF 869 */ 870 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 871 { 872 return (uint32_t) (READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); 873 } 874 875 /** 876 * @brief Set HSI Calibration trimming 877 * @note user-programmable trimming value that is added to the HSICAL 878 * @note Default value is 16, which, when added to the HSICAL value, 879 * should trim the HSI to 16 MHz +/- 1 % 880 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming 881 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F 882 * @retval None 883 */ 884 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 885 { 886 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); 887 } 888 889 /** 890 * @brief Get HSI Calibration trimming 891 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming 892 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F 893 */ 894 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 895 { 896 return (uint32_t) (READ_BIT(RCC->CR, RCC_CR_HSITRIM) 897 >> RCC_CR_HSITRIM_Pos); 898 } 899 900 /** 901 * @} 902 */ 903 904 /** @defgroup RCC_LL_EF_LSE LSE 905 * @{ 906 */ 907 908 /** 909 * @brief Enable Low Speed External (LSE) crystal. 910 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 911 * @retval None 912 */ 913 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 914 { 915 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 916 } 917 918 /** 919 * @brief Disable Low Speed External (LSE) crystal. 920 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 921 * @retval None 922 */ 923 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 924 { 925 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 926 } 927 928 /** 929 * @brief Enable external clock source (LSE bypass). 930 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 931 * @retval None 932 */ 933 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 934 { 935 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 936 } 937 938 /** 939 * @brief Disable external clock source (LSE bypass). 940 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 941 * @retval None 942 */ 943 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 944 { 945 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 946 } 947 948 /** 949 * @brief Check if LSE oscillator Ready 950 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 951 * @retval State of bit (1 or 0). 952 */ 953 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 954 { 955 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); 956 } 957 958 /** 959 * @} 960 */ 961 962 /** @defgroup RCC_LL_EF_LSI LSI 963 * @{ 964 */ 965 966 /** 967 * @brief Enable LSI Oscillator 968 * @rmtoll CSR LSION LL_RCC_LSI_Enable 969 * @retval None 970 */ 971 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 972 { 973 SET_BIT(RCC->CSR, RCC_CSR_LSION); 974 } 975 976 /** 977 * @brief Disable LSI Oscillator 978 * @rmtoll CSR LSION LL_RCC_LSI_Disable 979 * @retval None 980 */ 981 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 982 { 983 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 984 } 985 986 /** 987 * @brief Check if LSI is Ready 988 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady 989 * @retval State of bit (1 or 0). 990 */ 991 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 992 { 993 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); 994 } 995 996 /** 997 * @} 998 */ 999 1000 /** @defgroup RCC_LL_EF_System System 1001 * @{ 1002 */ 1003 1004 /** 1005 * @brief Configure the system clock source 1006 * @rmtoll CFGR SW LL_RCC_SetSysClkSource 1007 * @param Source This parameter can be one of the following values: 1008 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 1009 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 1010 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL 1011 * @retval None 1012 */ 1013 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 1014 { 1015 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 1016 } 1017 1018 /** 1019 * @brief Get the system clock source 1020 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource 1021 * @retval Returned value can be one of the following values: 1022 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 1023 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 1024 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL 1025 */ 1026 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 1027 { 1028 return (uint32_t) (READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 1029 } 1030 1031 /** 1032 * @brief Set AHB prescaler 1033 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler 1034 * @param Prescaler This parameter can be one of the following values: 1035 * @arg @ref LL_RCC_SYSCLK_DIV_1 1036 * @arg @ref LL_RCC_SYSCLK_DIV_2 1037 * @arg @ref LL_RCC_SYSCLK_DIV_4 1038 * @arg @ref LL_RCC_SYSCLK_DIV_8 1039 * @arg @ref LL_RCC_SYSCLK_DIV_16 1040 * @arg @ref LL_RCC_SYSCLK_DIV_64 1041 * @arg @ref LL_RCC_SYSCLK_DIV_128 1042 * @arg @ref LL_RCC_SYSCLK_DIV_256 1043 * @arg @ref LL_RCC_SYSCLK_DIV_512 1044 * @retval None 1045 */ 1046 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 1047 { 1048 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 1049 } 1050 1051 /** 1052 * @brief Set APB1 prescaler 1053 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler 1054 * @param Prescaler This parameter can be one of the following values: 1055 * @arg @ref LL_RCC_APB1_DIV_1 1056 * @arg @ref LL_RCC_APB1_DIV_2 1057 * @arg @ref LL_RCC_APB1_DIV_4 1058 * @arg @ref LL_RCC_APB1_DIV_8 1059 * @arg @ref LL_RCC_APB1_DIV_16 1060 * @retval None 1061 */ 1062 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 1063 { 1064 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 1065 } 1066 1067 /** 1068 * @brief Set APB2 prescaler 1069 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler 1070 * @param Prescaler This parameter can be one of the following values: 1071 * @arg @ref LL_RCC_APB2_DIV_1 1072 * @arg @ref LL_RCC_APB2_DIV_2 1073 * @arg @ref LL_RCC_APB2_DIV_4 1074 * @arg @ref LL_RCC_APB2_DIV_8 1075 * @arg @ref LL_RCC_APB2_DIV_16 1076 * @retval None 1077 */ 1078 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 1079 { 1080 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 1081 } 1082 1083 /** 1084 * @brief Get AHB prescaler 1085 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler 1086 * @retval Returned value can be one of the following values: 1087 * @arg @ref LL_RCC_SYSCLK_DIV_1 1088 * @arg @ref LL_RCC_SYSCLK_DIV_2 1089 * @arg @ref LL_RCC_SYSCLK_DIV_4 1090 * @arg @ref LL_RCC_SYSCLK_DIV_8 1091 * @arg @ref LL_RCC_SYSCLK_DIV_16 1092 * @arg @ref LL_RCC_SYSCLK_DIV_64 1093 * @arg @ref LL_RCC_SYSCLK_DIV_128 1094 * @arg @ref LL_RCC_SYSCLK_DIV_256 1095 * @arg @ref LL_RCC_SYSCLK_DIV_512 1096 */ 1097 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 1098 { 1099 return (uint32_t) (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 1100 } 1101 1102 /** 1103 * @brief Get APB1 prescaler 1104 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler 1105 * @retval Returned value can be one of the following values: 1106 * @arg @ref LL_RCC_APB1_DIV_1 1107 * @arg @ref LL_RCC_APB1_DIV_2 1108 * @arg @ref LL_RCC_APB1_DIV_4 1109 * @arg @ref LL_RCC_APB1_DIV_8 1110 * @arg @ref LL_RCC_APB1_DIV_16 1111 */ 1112 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 1113 { 1114 return (uint32_t) (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 1115 } 1116 1117 /** 1118 * @brief Get APB2 prescaler 1119 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler 1120 * @retval Returned value can be one of the following values: 1121 * @arg @ref LL_RCC_APB2_DIV_1 1122 * @arg @ref LL_RCC_APB2_DIV_2 1123 * @arg @ref LL_RCC_APB2_DIV_4 1124 * @arg @ref LL_RCC_APB2_DIV_8 1125 * @arg @ref LL_RCC_APB2_DIV_16 1126 */ 1127 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 1128 { 1129 return (uint32_t) (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 1130 } 1131 1132 /** 1133 * @} 1134 */ 1135 1136 /** @defgroup RCC_LL_EF_MCO MCO 1137 * @{ 1138 */ 1139 1140 /** 1141 * @brief Configure MCOx 1142 * @rmtoll CFGR MCO LL_RCC_ConfigMCO 1143 * @param MCOxSource This parameter can be one of the following values: 1144 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK 1145 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK 1146 * @arg @ref LL_RCC_MCO1SOURCE_HSI 1147 * @arg @ref LL_RCC_MCO1SOURCE_HSE 1148 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 1149 * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*) 1150 * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*) 1151 * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*) 1152 * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*) 1153 * 1154 * (*) value not defined in all devices 1155 * @retval None 1156 */ 1157 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource) 1158 { 1159 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); 1160 } 1161 1162 /** 1163 * @} 1164 */ 1165 1166 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 1167 * @{ 1168 */ 1169 1170 #if defined(RCC_CFGR2_I2S2SRC) 1171 /** 1172 * @brief Configure I2Sx clock source 1173 * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n 1174 * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource 1175 * @param I2SxSource This parameter can be one of the following values: 1176 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK 1177 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO 1178 * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK 1179 * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO 1180 * @retval None 1181 */ 1182 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) 1183 { 1184 MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); 1185 } 1186 #endif /* RCC_CFGR2_I2S2SRC */ 1187 1188 #if defined(USB_OTG_FS) || defined(USB) 1189 /** 1190 * @brief Configure USB clock source 1191 * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n 1192 * CFGR USBPRE LL_RCC_SetUSBClockSource 1193 * @param USBxSource This parameter can be one of the following values: 1194 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) 1195 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) 1196 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) 1197 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) 1198 * 1199 * (*) value not defined in all devices 1200 * @retval None 1201 */ 1202 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) 1203 { 1204 #if defined(RCC_CFGR_USBPRE) 1205 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); 1206 #else /*RCC_CFGR_OTGFSPRE*/ 1207 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource); 1208 #endif /*RCC_CFGR_USBPRE*/ 1209 } 1210 #endif /* USB_OTG_FS || USB */ 1211 1212 /** 1213 * @brief Configure ADC clock source 1214 * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource 1215 * @param ADCxSource This parameter can be one of the following values: 1216 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 1217 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 1218 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 1219 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 1220 * @retval None 1221 */ 1222 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) 1223 { 1224 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); 1225 } 1226 1227 #if defined(RCC_CFGR2_I2S2SRC) 1228 /** 1229 * @brief Get I2Sx clock source 1230 * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n 1231 * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource 1232 * @param I2Sx This parameter can be one of the following values: 1233 * @arg @ref LL_RCC_I2S2_CLKSOURCE 1234 * @arg @ref LL_RCC_I2S3_CLKSOURCE 1235 * @retval Returned value can be one of the following values: 1236 * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK 1237 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO 1238 * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK 1239 * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO 1240 */ 1241 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) 1242 { 1243 return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); 1244 } 1245 #endif /* RCC_CFGR2_I2S2SRC */ 1246 1247 #if defined(USB_OTG_FS) || defined(USB) 1248 /** 1249 * @brief Get USBx clock source 1250 * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n 1251 * CFGR USBPRE LL_RCC_GetUSBClockSource 1252 * @param USBx This parameter can be one of the following values: 1253 * @arg @ref LL_RCC_USB_CLKSOURCE 1254 * @retval Returned value can be one of the following values: 1255 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) 1256 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) 1257 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) 1258 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) 1259 * 1260 * (*) value not defined in all devices 1261 */ 1262 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) 1263 { 1264 return (uint32_t) (READ_BIT(RCC->CFGR, USBx)); 1265 } 1266 #endif /* USB_OTG_FS || USB */ 1267 1268 /** 1269 * @brief Get ADCx clock source 1270 * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource 1271 * @param ADCx This parameter can be one of the following values: 1272 * @arg @ref LL_RCC_ADC_CLKSOURCE 1273 * @retval Returned value can be one of the following values: 1274 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 1275 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 1276 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 1277 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 1278 */ 1279 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) 1280 { 1281 return (uint32_t) (READ_BIT(RCC->CFGR, ADCx)); 1282 } 1283 1284 /** 1285 * @} 1286 */ 1287 1288 /** @defgroup RCC_LL_EF_RTC RTC 1289 * @{ 1290 */ 1291 1292 /** 1293 * @brief Set RTC Clock Source 1294 * @note Once the RTC clock source has been selected, it cannot be changed any more unless 1295 * the Backup domain is reset. The BDRST bit can be used to reset them. 1296 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 1297 * @param Source This parameter can be one of the following values: 1298 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 1299 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 1300 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 1301 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 1302 * @retval None 1303 */ 1304 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 1305 { 1306 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 1307 } 1308 1309 /** 1310 * @brief Get RTC Clock Source 1311 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 1312 * @retval Returned value can be one of the following values: 1313 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 1314 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 1315 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 1316 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 1317 */ 1318 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 1319 { 1320 return (uint32_t) (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 1321 } 1322 1323 /** 1324 * @brief Enable RTC 1325 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 1326 * @retval None 1327 */ 1328 __STATIC_INLINE void LL_RCC_EnableRTC(void) 1329 { 1330 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 1331 } 1332 1333 /** 1334 * @brief Disable RTC 1335 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 1336 * @retval None 1337 */ 1338 __STATIC_INLINE void LL_RCC_DisableRTC(void) 1339 { 1340 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 1341 } 1342 1343 /** 1344 * @brief Check if RTC has been enabled or not 1345 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 1346 * @retval State of bit (1 or 0). 1347 */ 1348 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 1349 { 1350 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); 1351 } 1352 1353 /** 1354 * @brief Force the Backup domain reset 1355 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset 1356 * @retval None 1357 */ 1358 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 1359 { 1360 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 1361 } 1362 1363 /** 1364 * @brief Release the Backup domain reset 1365 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset 1366 * @retval None 1367 */ 1368 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 1369 { 1370 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 1371 } 1372 1373 /** 1374 * @} 1375 */ 1376 1377 /** @defgroup RCC_LL_EF_PLL PLL 1378 * @{ 1379 */ 1380 1381 /** 1382 * @brief Enable PLL 1383 * @rmtoll CR PLLON LL_RCC_PLL_Enable 1384 * @retval None 1385 */ 1386 __STATIC_INLINE void LL_RCC_PLL_Enable(void) 1387 { 1388 SET_BIT(RCC->CR, RCC_CR_PLLON); 1389 } 1390 1391 /** 1392 * @brief Disable PLL 1393 * @note Cannot be disabled if the PLL clock is used as the system clock 1394 * @rmtoll CR PLLON LL_RCC_PLL_Disable 1395 * @retval None 1396 */ 1397 __STATIC_INLINE void LL_RCC_PLL_Disable(void) 1398 { 1399 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 1400 } 1401 1402 /** 1403 * @brief Check if PLL Ready 1404 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady 1405 * @retval State of bit (1 or 0). 1406 */ 1407 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) 1408 { 1409 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); 1410 } 1411 1412 /** 1413 * @brief Configure PLL used for SYSCLK Domain 1414 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n 1415 * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n 1416 * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n 1417 * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n 1418 * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS 1419 * @param Source This parameter can be one of the following values: 1420 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 1421 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 1422 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*) 1423 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*) 1424 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*) 1425 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*) 1426 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*) 1427 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*) 1428 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*) 1429 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*) 1430 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*) 1431 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*) 1432 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*) 1433 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*) 1434 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*) 1435 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*) 1436 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*) 1437 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*) 1438 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*) 1439 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*) 1440 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*) 1441 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*) 1442 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*) 1443 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*) 1444 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*) 1445 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*) 1446 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*) 1447 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*) 1448 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*) 1449 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*) 1450 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*) 1451 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*) 1452 * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*) 1453 * 1454 * (*) value not defined in all devices 1455 * @param PLLMul This parameter can be one of the following values: 1456 * @arg @ref LL_RCC_PLL_MUL_2 (*) 1457 * @arg @ref LL_RCC_PLL_MUL_3 (*) 1458 * @arg @ref LL_RCC_PLL_MUL_4 1459 * @arg @ref LL_RCC_PLL_MUL_5 1460 * @arg @ref LL_RCC_PLL_MUL_6 1461 * @arg @ref LL_RCC_PLL_MUL_7 1462 * @arg @ref LL_RCC_PLL_MUL_8 1463 * @arg @ref LL_RCC_PLL_MUL_9 1464 * @arg @ref LL_RCC_PLL_MUL_6_5 (*) 1465 * @arg @ref LL_RCC_PLL_MUL_10 (*) 1466 * @arg @ref LL_RCC_PLL_MUL_11 (*) 1467 * @arg @ref LL_RCC_PLL_MUL_12 (*) 1468 * @arg @ref LL_RCC_PLL_MUL_13 (*) 1469 * @arg @ref LL_RCC_PLL_MUL_14 (*) 1470 * @arg @ref LL_RCC_PLL_MUL_15 (*) 1471 * @arg @ref LL_RCC_PLL_MUL_16 (*) 1472 * 1473 * (*) value not defined in all devices 1474 * @retval None 1475 */ 1476 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, 1477 uint32_t PLLMul) 1478 { 1479 MODIFY_REG(RCC->CFGR, 1480 RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL, 1481 (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul); 1482 #if defined(RCC_CFGR2_PREDIV1) 1483 #if defined(RCC_CFGR2_PREDIV1SRC) 1484 MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), 1485 (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); 1486 #else 1487 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); 1488 #endif /*RCC_CFGR2_PREDIV1SRC*/ 1489 #endif /*RCC_CFGR2_PREDIV1*/ 1490 } 1491 1492 /** 1493 * @brief Configure PLL clock source 1494 * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n 1495 * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource 1496 * @param PLLSource This parameter can be one of the following values: 1497 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 1498 * @arg @ref LL_RCC_PLLSOURCE_HSE 1499 * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) 1500 * @retval None 1501 */ 1502 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) 1503 { 1504 #if defined(RCC_CFGR2_PREDIV1SRC) 1505 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); 1506 #endif /* RCC_CFGR2_PREDIV1SRC */ 1507 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); 1508 } 1509 1510 /** 1511 * @brief Get the oscillator used as PLL clock source. 1512 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n 1513 * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource 1514 * @retval Returned value can be one of the following values: 1515 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 1516 * @arg @ref LL_RCC_PLLSOURCE_HSE 1517 * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) 1518 * 1519 * (*) value not defined in all devices 1520 */ 1521 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) 1522 { 1523 #if defined(RCC_CFGR2_PREDIV1SRC) 1524 uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); 1525 uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); 1526 return (uint32_t)(pllsrc | predivsrc); 1527 #else 1528 return (uint32_t) (READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); 1529 #endif /*RCC_CFGR2_PREDIV1SRC*/ 1530 } 1531 1532 /** 1533 * @brief Get PLL multiplication Factor 1534 * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator 1535 * @retval Returned value can be one of the following values: 1536 * @arg @ref LL_RCC_PLL_MUL_2 (*) 1537 * @arg @ref LL_RCC_PLL_MUL_3 (*) 1538 * @arg @ref LL_RCC_PLL_MUL_4 1539 * @arg @ref LL_RCC_PLL_MUL_5 1540 * @arg @ref LL_RCC_PLL_MUL_6 1541 * @arg @ref LL_RCC_PLL_MUL_7 1542 * @arg @ref LL_RCC_PLL_MUL_8 1543 * @arg @ref LL_RCC_PLL_MUL_9 1544 * @arg @ref LL_RCC_PLL_MUL_6_5 (*) 1545 * @arg @ref LL_RCC_PLL_MUL_10 (*) 1546 * @arg @ref LL_RCC_PLL_MUL_11 (*) 1547 * @arg @ref LL_RCC_PLL_MUL_12 (*) 1548 * @arg @ref LL_RCC_PLL_MUL_13 (*) 1549 * @arg @ref LL_RCC_PLL_MUL_14 (*) 1550 * @arg @ref LL_RCC_PLL_MUL_15 (*) 1551 * @arg @ref LL_RCC_PLL_MUL_16 (*) 1552 * 1553 * (*) value not defined in all devices 1554 */ 1555 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) 1556 { 1557 return (uint32_t) (READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL)); 1558 } 1559 1560 /** 1561 * @brief Get PREDIV1 division factor for the main PLL 1562 * @note They can be written only when the PLL is disabled 1563 * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n 1564 * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv 1565 * @retval Returned value can be one of the following values: 1566 * @arg @ref LL_RCC_PREDIV_DIV_1 1567 * @arg @ref LL_RCC_PREDIV_DIV_2 1568 * @arg @ref LL_RCC_PREDIV_DIV_3 (*) 1569 * @arg @ref LL_RCC_PREDIV_DIV_4 (*) 1570 * @arg @ref LL_RCC_PREDIV_DIV_5 (*) 1571 * @arg @ref LL_RCC_PREDIV_DIV_6 (*) 1572 * @arg @ref LL_RCC_PREDIV_DIV_7 (*) 1573 * @arg @ref LL_RCC_PREDIV_DIV_8 (*) 1574 * @arg @ref LL_RCC_PREDIV_DIV_9 (*) 1575 * @arg @ref LL_RCC_PREDIV_DIV_10 (*) 1576 * @arg @ref LL_RCC_PREDIV_DIV_11 (*) 1577 * @arg @ref LL_RCC_PREDIV_DIV_12 (*) 1578 * @arg @ref LL_RCC_PREDIV_DIV_13 (*) 1579 * @arg @ref LL_RCC_PREDIV_DIV_14 (*) 1580 * @arg @ref LL_RCC_PREDIV_DIV_15 (*) 1581 * @arg @ref LL_RCC_PREDIV_DIV_16 (*) 1582 * 1583 * (*) value not defined in all devices 1584 */ 1585 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) 1586 { 1587 #if defined(RCC_CFGR2_PREDIV1) 1588 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); 1589 #else 1590 return (uint32_t) (READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) 1591 >> RCC_CFGR_PLLXTPRE_Pos); 1592 #endif /*RCC_CFGR2_PREDIV1*/ 1593 } 1594 1595 /** 1596 * @} 1597 */ 1598 1599 #if defined(RCC_PLLI2S_SUPPORT) 1600 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S 1601 * @{ 1602 */ 1603 1604 /** 1605 * @brief Enable PLLI2S 1606 * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable 1607 * @retval None 1608 */ 1609 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) 1610 { 1611 SET_BIT(RCC->CR, RCC_CR_PLL3ON); 1612 } 1613 1614 /** 1615 * @brief Disable PLLI2S 1616 * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable 1617 * @retval None 1618 */ 1619 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) 1620 { 1621 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); 1622 } 1623 1624 /** 1625 * @brief Check if PLLI2S Ready 1626 * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady 1627 * @retval State of bit (1 or 0). 1628 */ 1629 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) 1630 { 1631 return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)); 1632 } 1633 1634 /** 1635 * @brief Configure PLLI2S used for I2S Domain 1636 * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n 1637 * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S 1638 * @param Divider This parameter can be one of the following values: 1639 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 1640 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 1641 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 1642 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 1643 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 1644 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 1645 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 1646 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 1647 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 1648 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 1649 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 1650 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 1651 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 1652 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 1653 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 1654 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 1655 * @param Multiplicator This parameter can be one of the following values: 1656 * @arg @ref LL_RCC_PLLI2S_MUL_8 1657 * @arg @ref LL_RCC_PLLI2S_MUL_9 1658 * @arg @ref LL_RCC_PLLI2S_MUL_10 1659 * @arg @ref LL_RCC_PLLI2S_MUL_11 1660 * @arg @ref LL_RCC_PLLI2S_MUL_12 1661 * @arg @ref LL_RCC_PLLI2S_MUL_13 1662 * @arg @ref LL_RCC_PLLI2S_MUL_14 1663 * @arg @ref LL_RCC_PLLI2S_MUL_16 1664 * @arg @ref LL_RCC_PLLI2S_MUL_20 1665 * @retval None 1666 */ 1667 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator) 1668 { 1669 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); 1670 } 1671 1672 /** 1673 * @brief Get PLLI2S Multiplication Factor 1674 * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator 1675 * @retval Returned value can be one of the following values: 1676 * @arg @ref LL_RCC_PLLI2S_MUL_8 1677 * @arg @ref LL_RCC_PLLI2S_MUL_9 1678 * @arg @ref LL_RCC_PLLI2S_MUL_10 1679 * @arg @ref LL_RCC_PLLI2S_MUL_11 1680 * @arg @ref LL_RCC_PLLI2S_MUL_12 1681 * @arg @ref LL_RCC_PLLI2S_MUL_13 1682 * @arg @ref LL_RCC_PLLI2S_MUL_14 1683 * @arg @ref LL_RCC_PLLI2S_MUL_16 1684 * @arg @ref LL_RCC_PLLI2S_MUL_20 1685 */ 1686 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void) 1687 { 1688 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); 1689 } 1690 1691 /** 1692 * @} 1693 */ 1694 #endif /* RCC_PLLI2S_SUPPORT */ 1695 1696 #if defined(RCC_PLL2_SUPPORT) 1697 /** @defgroup RCC_LL_EF_PLL2 PLL2 1698 * @{ 1699 */ 1700 1701 /** 1702 * @brief Enable PLL2 1703 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable 1704 * @retval None 1705 */ 1706 __STATIC_INLINE void LL_RCC_PLL2_Enable(void) 1707 { 1708 SET_BIT(RCC->CR, RCC_CR_PLL2ON); 1709 } 1710 1711 /** 1712 * @brief Disable PLL2 1713 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable 1714 * @retval None 1715 */ 1716 __STATIC_INLINE void LL_RCC_PLL2_Disable(void) 1717 { 1718 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); 1719 } 1720 1721 /** 1722 * @brief Check if PLL2 Ready 1723 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady 1724 * @retval State of bit (1 or 0). 1725 */ 1726 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) 1727 { 1728 return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)); 1729 } 1730 1731 /** 1732 * @brief Configure PLL2 used for PLL2 Domain 1733 * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n 1734 * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2 1735 * @param Divider This parameter can be one of the following values: 1736 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 1737 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 1738 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 1739 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 1740 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 1741 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 1742 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 1743 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 1744 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 1745 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 1746 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 1747 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 1748 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 1749 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 1750 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 1751 * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 1752 * @param Multiplicator This parameter can be one of the following values: 1753 * @arg @ref LL_RCC_PLL2_MUL_8 1754 * @arg @ref LL_RCC_PLL2_MUL_9 1755 * @arg @ref LL_RCC_PLL2_MUL_10 1756 * @arg @ref LL_RCC_PLL2_MUL_11 1757 * @arg @ref LL_RCC_PLL2_MUL_12 1758 * @arg @ref LL_RCC_PLL2_MUL_13 1759 * @arg @ref LL_RCC_PLL2_MUL_14 1760 * @arg @ref LL_RCC_PLL2_MUL_16 1761 * @arg @ref LL_RCC_PLL2_MUL_20 1762 * @retval None 1763 */ 1764 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator) 1765 { 1766 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator); 1767 } 1768 1769 /** 1770 * @brief Get PLL2 Multiplication Factor 1771 * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator 1772 * @retval Returned value can be one of the following values: 1773 * @arg @ref LL_RCC_PLL2_MUL_8 1774 * @arg @ref LL_RCC_PLL2_MUL_9 1775 * @arg @ref LL_RCC_PLL2_MUL_10 1776 * @arg @ref LL_RCC_PLL2_MUL_11 1777 * @arg @ref LL_RCC_PLL2_MUL_12 1778 * @arg @ref LL_RCC_PLL2_MUL_13 1779 * @arg @ref LL_RCC_PLL2_MUL_14 1780 * @arg @ref LL_RCC_PLL2_MUL_16 1781 * @arg @ref LL_RCC_PLL2_MUL_20 1782 */ 1783 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void) 1784 { 1785 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL)); 1786 } 1787 1788 /** 1789 * @} 1790 */ 1791 #endif /* RCC_PLL2_SUPPORT */ 1792 1793 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 1794 * @{ 1795 */ 1796 1797 /** 1798 * @brief Clear LSI ready interrupt flag 1799 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY 1800 * @retval None 1801 */ 1802 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 1803 { 1804 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); 1805 } 1806 1807 /** 1808 * @brief Clear LSE ready interrupt flag 1809 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY 1810 * @retval None 1811 */ 1812 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 1813 { 1814 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); 1815 } 1816 1817 /** 1818 * @brief Clear HSI ready interrupt flag 1819 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY 1820 * @retval None 1821 */ 1822 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 1823 { 1824 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); 1825 } 1826 1827 /** 1828 * @brief Clear HSE ready interrupt flag 1829 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY 1830 * @retval None 1831 */ 1832 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 1833 { 1834 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); 1835 } 1836 1837 /** 1838 * @brief Clear PLL ready interrupt flag 1839 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY 1840 * @retval None 1841 */ 1842 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) 1843 { 1844 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); 1845 } 1846 1847 #if defined(RCC_PLLI2S_SUPPORT) 1848 /** 1849 * @brief Clear PLLI2S ready interrupt flag 1850 * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY 1851 * @retval None 1852 */ 1853 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) 1854 { 1855 SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC); 1856 } 1857 #endif /* RCC_PLLI2S_SUPPORT */ 1858 1859 #if defined(RCC_PLL2_SUPPORT) 1860 /** 1861 * @brief Clear PLL2 ready interrupt flag 1862 * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY 1863 * @retval None 1864 */ 1865 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) 1866 { 1867 SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC); 1868 } 1869 #endif /* RCC_PLL2_SUPPORT */ 1870 1871 /** 1872 * @brief Clear Clock security system interrupt flag 1873 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS 1874 * @retval None 1875 */ 1876 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 1877 { 1878 SET_BIT(RCC->CIR, RCC_CIR_CSSC); 1879 } 1880 1881 /** 1882 * @brief Check if LSI ready interrupt occurred or not 1883 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 1884 * @retval State of bit (1 or 0). 1885 */ 1886 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 1887 { 1888 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); 1889 } 1890 1891 /** 1892 * @brief Check if LSE ready interrupt occurred or not 1893 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY 1894 * @retval State of bit (1 or 0). 1895 */ 1896 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 1897 { 1898 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); 1899 } 1900 1901 /** 1902 * @brief Check if HSI ready interrupt occurred or not 1903 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 1904 * @retval State of bit (1 or 0). 1905 */ 1906 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 1907 { 1908 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); 1909 } 1910 1911 /** 1912 * @brief Check if HSE ready interrupt occurred or not 1913 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY 1914 * @retval State of bit (1 or 0). 1915 */ 1916 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 1917 { 1918 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); 1919 } 1920 1921 /** 1922 * @brief Check if PLL ready interrupt occurred or not 1923 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY 1924 * @retval State of bit (1 or 0). 1925 */ 1926 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) 1927 { 1928 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); 1929 } 1930 1931 #if defined(RCC_PLLI2S_SUPPORT) 1932 /** 1933 * @brief Check if PLLI2S ready interrupt occurred or not 1934 * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY 1935 * @retval State of bit (1 or 0). 1936 */ 1937 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) 1938 { 1939 return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF)); 1940 } 1941 #endif /* RCC_PLLI2S_SUPPORT */ 1942 1943 #if defined(RCC_PLL2_SUPPORT) 1944 /** 1945 * @brief Check if PLL2 ready interrupt occurred or not 1946 * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY 1947 * @retval State of bit (1 or 0). 1948 */ 1949 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) 1950 { 1951 return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF)); 1952 } 1953 #endif /* RCC_PLL2_SUPPORT */ 1954 1955 /** 1956 * @brief Check if Clock security system interrupt occurred or not 1957 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS 1958 * @retval State of bit (1 or 0). 1959 */ 1960 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 1961 { 1962 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); 1963 } 1964 1965 /** 1966 * @brief Check if RCC flag Independent Watchdog reset is set or not. 1967 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST 1968 * @retval State of bit (1 or 0). 1969 */ 1970 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) 1971 { 1972 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); 1973 } 1974 1975 /** 1976 * @brief Check if RCC flag Low Power reset is set or not. 1977 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST 1978 * @retval State of bit (1 or 0). 1979 */ 1980 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 1981 { 1982 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); 1983 } 1984 1985 /** 1986 * @brief Check if RCC flag Pin reset is set or not. 1987 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST 1988 * @retval State of bit (1 or 0). 1989 */ 1990 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 1991 { 1992 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); 1993 } 1994 1995 /** 1996 * @brief Check if RCC flag POR/PDR reset is set or not. 1997 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST 1998 * @retval State of bit (1 or 0). 1999 */ 2000 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) 2001 { 2002 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); 2003 } 2004 2005 /** 2006 * @brief Check if RCC flag Software reset is set or not. 2007 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST 2008 * @retval State of bit (1 or 0). 2009 */ 2010 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 2011 { 2012 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); 2013 } 2014 2015 /** 2016 * @brief Check if RCC flag Window Watchdog reset is set or not. 2017 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST 2018 * @retval State of bit (1 or 0). 2019 */ 2020 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) 2021 { 2022 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); 2023 } 2024 2025 /** 2026 * @brief Set RMVF bit to clear the reset flags. 2027 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags 2028 * @retval None 2029 */ 2030 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 2031 { 2032 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 2033 } 2034 2035 /** 2036 * @} 2037 */ 2038 2039 /** @defgroup RCC_LL_EF_IT_Management IT Management 2040 * @{ 2041 */ 2042 2043 /** 2044 * @brief Enable LSI ready interrupt 2045 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY 2046 * @retval None 2047 */ 2048 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 2049 { 2050 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); 2051 } 2052 2053 /** 2054 * @brief Enable LSE ready interrupt 2055 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY 2056 * @retval None 2057 */ 2058 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 2059 { 2060 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); 2061 } 2062 2063 /** 2064 * @brief Enable HSI ready interrupt 2065 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY 2066 * @retval None 2067 */ 2068 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 2069 { 2070 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); 2071 } 2072 2073 /** 2074 * @brief Enable HSE ready interrupt 2075 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY 2076 * @retval None 2077 */ 2078 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 2079 { 2080 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); 2081 } 2082 2083 /** 2084 * @brief Enable PLL ready interrupt 2085 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY 2086 * @retval None 2087 */ 2088 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) 2089 { 2090 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); 2091 } 2092 2093 #if defined(RCC_PLLI2S_SUPPORT) 2094 /** 2095 * @brief Enable PLLI2S ready interrupt 2096 * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY 2097 * @retval None 2098 */ 2099 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) 2100 { 2101 SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); 2102 } 2103 #endif /* RCC_PLLI2S_SUPPORT */ 2104 2105 #if defined(RCC_PLL2_SUPPORT) 2106 /** 2107 * @brief Enable PLL2 ready interrupt 2108 * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY 2109 * @retval None 2110 */ 2111 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) 2112 { 2113 SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); 2114 } 2115 #endif /* RCC_PLL2_SUPPORT */ 2116 2117 /** 2118 * @brief Disable LSI ready interrupt 2119 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY 2120 * @retval None 2121 */ 2122 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 2123 { 2124 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); 2125 } 2126 2127 /** 2128 * @brief Disable LSE ready interrupt 2129 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY 2130 * @retval None 2131 */ 2132 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 2133 { 2134 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); 2135 } 2136 2137 /** 2138 * @brief Disable HSI ready interrupt 2139 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY 2140 * @retval None 2141 */ 2142 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 2143 { 2144 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); 2145 } 2146 2147 /** 2148 * @brief Disable HSE ready interrupt 2149 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY 2150 * @retval None 2151 */ 2152 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 2153 { 2154 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); 2155 } 2156 2157 /** 2158 * @brief Disable PLL ready interrupt 2159 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY 2160 * @retval None 2161 */ 2162 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) 2163 { 2164 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); 2165 } 2166 2167 #if defined(RCC_PLLI2S_SUPPORT) 2168 /** 2169 * @brief Disable PLLI2S ready interrupt 2170 * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY 2171 * @retval None 2172 */ 2173 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) 2174 { 2175 CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); 2176 } 2177 #endif /* RCC_PLLI2S_SUPPORT */ 2178 2179 #if defined(RCC_PLL2_SUPPORT) 2180 /** 2181 * @brief Disable PLL2 ready interrupt 2182 * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY 2183 * @retval None 2184 */ 2185 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) 2186 { 2187 CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); 2188 } 2189 #endif /* RCC_PLL2_SUPPORT */ 2190 2191 /** 2192 * @brief Checks if LSI ready interrupt source is enabled or disabled. 2193 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY 2194 * @retval State of bit (1 or 0). 2195 */ 2196 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) 2197 { 2198 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); 2199 } 2200 2201 /** 2202 * @brief Checks if LSE ready interrupt source is enabled or disabled. 2203 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY 2204 * @retval State of bit (1 or 0). 2205 */ 2206 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) 2207 { 2208 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); 2209 } 2210 2211 /** 2212 * @brief Checks if HSI ready interrupt source is enabled or disabled. 2213 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY 2214 * @retval State of bit (1 or 0). 2215 */ 2216 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) 2217 { 2218 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); 2219 } 2220 2221 /** 2222 * @brief Checks if HSE ready interrupt source is enabled or disabled. 2223 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY 2224 * @retval State of bit (1 or 0). 2225 */ 2226 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) 2227 { 2228 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); 2229 } 2230 2231 /** 2232 * @brief Checks if PLL ready interrupt source is enabled or disabled. 2233 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY 2234 * @retval State of bit (1 or 0). 2235 */ 2236 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) 2237 { 2238 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); 2239 } 2240 2241 #if defined(RCC_PLLI2S_SUPPORT) 2242 /** 2243 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. 2244 * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY 2245 * @retval State of bit (1 or 0). 2246 */ 2247 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) 2248 { 2249 return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE)); 2250 } 2251 #endif /* RCC_PLLI2S_SUPPORT */ 2252 2253 #if defined(RCC_PLL2_SUPPORT) 2254 /** 2255 * @brief Checks if PLL2 ready interrupt source is enabled or disabled. 2256 * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY 2257 * @retval State of bit (1 or 0). 2258 */ 2259 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) 2260 { 2261 return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE)); 2262 } 2263 #endif /* RCC_PLL2_SUPPORT */ 2264 2265 /** 2266 * @} 2267 */ 2268 2269 #if defined(USE_FULL_LL_DRIVER) 2270 /** @defgroup RCC_LL_EF_Init De-initialization function 2271 * @{ 2272 */ 2273 ErrorStatus LL_RCC_DeInit(void); 2274 /** 2275 * @} 2276 */ 2277 2278 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 2279 * @{ 2280 */ 2281 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 2282 #if defined(RCC_CFGR2_I2S2SRC) 2283 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); 2284 #endif /* RCC_CFGR2_I2S2SRC */ 2285 #if defined(USB_OTG_FS) || defined(USB) 2286 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 2287 #endif /* USB_OTG_FS || USB */ 2288 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); 2289 /** 2290 * @} 2291 */ 2292 #endif /* USE_FULL_LL_DRIVER */ 2293 2294 /** 2295 * @} 2296 */ 2297 2298 /** 2299 * @} 2300 */ 2301 2302 #endif /* RCC */ 2303 2304 /** 2305 * @} 2306 */ 2307 2308 #ifdef __cplusplus 2309 } 2310 #endif 2311 2312 #endif /* __STM32F1xx_LL_RCC_H */ 2313