Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h (91502B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_ll_gpio.h 4 * @author MCD Application Team 5 * @brief Header file of GPIO LL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F1xx_LL_GPIO_H 21 #define STM32F1xx_LL_GPIO_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f1xx.h" 29 30 /** @addtogroup STM32F1xx_LL_Driver 31 * @{ 32 */ 33 34 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) 35 36 /** @defgroup GPIO_LL GPIO 37 * @{ 38 */ 39 40 /* Private types -------------------------------------------------------------*/ 41 /* Private variables ---------------------------------------------------------*/ 42 /* Private constants ---------------------------------------------------------*/ 43 44 /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants 45 * @{ 46 */ 47 /* Defines used for Pin Mask Initialization */ 48 #define GPIO_PIN_MASK_POS 8U 49 #define GPIO_PIN_NB 16U 50 /** 51 * @} 52 */ 53 54 /* Private macros ------------------------------------------------------------*/ 55 #if defined(USE_FULL_LL_DRIVER) 56 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros 57 * @{ 58 */ 59 60 /** 61 * @} 62 */ 63 #endif /*USE_FULL_LL_DRIVER*/ 64 65 /* Exported types ------------------------------------------------------------*/ 66 #if defined(USE_FULL_LL_DRIVER) 67 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures 68 * @{ 69 */ 70 71 /** 72 * @brief LL GPIO Init Structure definition 73 */ 74 typedef struct 75 { 76 uint32_t Pin; /*!< Specifies the GPIO pins to be configured. 77 This parameter can be any value of @ref GPIO_LL_EC_PIN */ 78 79 uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 80 This parameter can be a value of @ref GPIO_LL_EC_MODE. 81 82 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ 83 84 uint32_t Speed; /*!< Specifies the speed for the selected pins. 85 This parameter can be a value of @ref GPIO_LL_EC_SPEED. 86 87 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ 88 89 uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. 90 This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. 91 92 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ 93 94 uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. 95 This parameter can be a value of @ref GPIO_LL_EC_PULL. 96 97 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ 98 }LL_GPIO_InitTypeDef; 99 100 /** 101 * @} 102 */ 103 #endif /* USE_FULL_LL_DRIVER */ 104 105 /* Exported constants --------------------------------------------------------*/ 106 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants 107 * @{ 108 */ 109 110 /** @defgroup GPIO_LL_EC_PIN PIN 111 * @{ 112 */ 113 #define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */ 114 #define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */ 115 #define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */ 116 #define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */ 117 #define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */ 118 #define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */ 119 #define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */ 120 #define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */ 121 #define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */ 122 #define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */ 123 #define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */ 124 #define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */ 125 #define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */ 126 #define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */ 127 #define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */ 128 #define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */ 129 #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ 130 LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ 131 LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ 132 LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ 133 LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ 134 LL_GPIO_PIN_15) /*!< Select all pins */ 135 /** 136 * @} 137 */ 138 139 /** @defgroup GPIO_LL_EC_MODE Mode 140 * @{ 141 */ 142 #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */ 143 #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */ 144 #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */ 145 #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */ 146 #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */ 147 /** 148 * @} 149 */ 150 151 /** @defgroup GPIO_LL_EC_OUTPUT Output Type 152 * @{ 153 */ 154 #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */ 155 #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */ 156 /** 157 * @} 158 */ 159 160 /** @defgroup GPIO_LL_EC_SPEED Output Speed 161 * @{ 162 */ 163 #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */ 164 #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */ 165 #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */ 166 /** 167 * @} 168 */ 169 170 #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */ 171 #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */ 172 #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */ 173 174 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down 175 * @{ 176 */ 177 #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */ 178 #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */ 179 180 /** 181 * @} 182 */ 183 184 /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin 185 * @{ 186 */ 187 188 #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ 189 #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ 190 #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ 191 #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ 192 #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ 193 #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ 194 #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ 195 #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ 196 #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ 197 #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ 198 #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ 199 #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ 200 #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ 201 #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ 202 #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ 203 #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ 204 205 /** 206 * @} 207 */ 208 209 /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port 210 * @{ 211 */ 212 213 #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ 214 #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ 215 #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ 216 #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ 217 #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ 218 219 /** 220 * @} 221 */ 222 223 /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT 224 * @{ 225 */ 226 #define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */ 227 #define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */ 228 #define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */ 229 #define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */ 230 #define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */ 231 #define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */ 232 #define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */ 233 /** 234 * @} 235 */ 236 237 /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE 238 * @{ 239 */ 240 #define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ 241 #define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ 242 #define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ 243 #define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ 244 #define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ 245 #define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ 246 #define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ 247 #define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ 248 #define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ 249 #define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ 250 #define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ 251 #define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ 252 #define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ 253 #define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ 254 #define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ 255 #define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ 256 /** 257 * @} 258 */ 259 260 /** 261 * @} 262 */ 263 264 /* Exported macro ------------------------------------------------------------*/ 265 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros 266 * @{ 267 */ 268 269 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros 270 * @{ 271 */ 272 273 /** 274 * @brief Write a value in GPIO register 275 * @param __INSTANCE__ GPIO Instance 276 * @param __REG__ Register to be written 277 * @param __VALUE__ Value to be written in the register 278 * @retval None 279 */ 280 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 281 282 /** 283 * @brief Read a value in GPIO register 284 * @param __INSTANCE__ GPIO Instance 285 * @param __REG__ Register to be read 286 * @retval Register value 287 */ 288 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 289 /** 290 * @} 291 */ 292 293 /** 294 * @} 295 */ 296 297 /* Exported functions --------------------------------------------------------*/ 298 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions 299 * @{ 300 */ 301 302 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration 303 * @{ 304 */ 305 306 /** 307 * @brief Configure gpio mode for a dedicated pin on dedicated port. 308 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, 309 * Alternate function Output. 310 * @note Warning: only one pin can be passed as parameter. 311 * @rmtoll CRL CNFy LL_GPIO_SetPinMode 312 * @rmtoll CRL MODEy LL_GPIO_SetPinMode 313 * @rmtoll CRH CNFy LL_GPIO_SetPinMode 314 * @rmtoll CRH MODEy LL_GPIO_SetPinMode 315 * @param GPIOx GPIO Port 316 * @param Pin This parameter can be one of the following values: 317 * @arg @ref LL_GPIO_PIN_0 318 * @arg @ref LL_GPIO_PIN_1 319 * @arg @ref LL_GPIO_PIN_2 320 * @arg @ref LL_GPIO_PIN_3 321 * @arg @ref LL_GPIO_PIN_4 322 * @arg @ref LL_GPIO_PIN_5 323 * @arg @ref LL_GPIO_PIN_6 324 * @arg @ref LL_GPIO_PIN_7 325 * @arg @ref LL_GPIO_PIN_8 326 * @arg @ref LL_GPIO_PIN_9 327 * @arg @ref LL_GPIO_PIN_10 328 * @arg @ref LL_GPIO_PIN_11 329 * @arg @ref LL_GPIO_PIN_12 330 * @arg @ref LL_GPIO_PIN_13 331 * @arg @ref LL_GPIO_PIN_14 332 * @arg @ref LL_GPIO_PIN_15 333 * @param Mode This parameter can be one of the following values: 334 * @arg @ref LL_GPIO_MODE_ANALOG 335 * @arg @ref LL_GPIO_MODE_FLOATING 336 * @arg @ref LL_GPIO_MODE_INPUT 337 * @arg @ref LL_GPIO_MODE_OUTPUT 338 * @arg @ref LL_GPIO_MODE_ALTERNATE 339 * @retval None 340 */ 341 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, 342 uint32_t Mode) 343 { 344 register uint32_t *pReg = 345 (uint32_t*) ((uint32_t) ((uint32_t) (&GPIOx->CRL) + (Pin >> 24))); 346 MODIFY_REG(*pReg, 347 ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), 348 (Mode << (POSITION_VAL(Pin) * 4U))); 349 } 350 351 /** 352 * @brief Return gpio mode for a dedicated pin on dedicated port. 353 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, 354 * Alternate function Output. 355 * @note Warning: only one pin can be passed as parameter. 356 * @rmtoll CRL CNFy LL_GPIO_GetPinMode 357 * @rmtoll CRL MODEy LL_GPIO_GetPinMode 358 * @rmtoll CRH CNFy LL_GPIO_GetPinMode 359 * @rmtoll CRH MODEy LL_GPIO_GetPinMode 360 * @param GPIOx GPIO Port 361 * @param Pin This parameter can be one of the following values: 362 * @arg @ref LL_GPIO_PIN_0 363 * @arg @ref LL_GPIO_PIN_1 364 * @arg @ref LL_GPIO_PIN_2 365 * @arg @ref LL_GPIO_PIN_3 366 * @arg @ref LL_GPIO_PIN_4 367 * @arg @ref LL_GPIO_PIN_5 368 * @arg @ref LL_GPIO_PIN_6 369 * @arg @ref LL_GPIO_PIN_7 370 * @arg @ref LL_GPIO_PIN_8 371 * @arg @ref LL_GPIO_PIN_9 372 * @arg @ref LL_GPIO_PIN_10 373 * @arg @ref LL_GPIO_PIN_11 374 * @arg @ref LL_GPIO_PIN_12 375 * @arg @ref LL_GPIO_PIN_13 376 * @arg @ref LL_GPIO_PIN_14 377 * @arg @ref LL_GPIO_PIN_15 378 * @retval Returned value can be one of the following values: 379 * @arg @ref LL_GPIO_MODE_ANALOG 380 * @arg @ref LL_GPIO_MODE_FLOATING 381 * @arg @ref LL_GPIO_MODE_INPUT 382 * @arg @ref LL_GPIO_MODE_OUTPUT 383 * @arg @ref LL_GPIO_MODE_ALTERNATE 384 */ 385 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, 386 uint32_t Pin) 387 { 388 register uint32_t *pReg = 389 (uint32_t*) ((uint32_t) ((uint32_t) (&GPIOx->CRL) + (Pin >> 24))); 390 return (READ_BIT(*pReg, 391 ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) 392 >> (POSITION_VAL(Pin) * 4U)); 393 } 394 395 /** 396 * @brief Configure gpio speed for a dedicated pin on dedicated port. 397 * @note I/O speed can be Low, Medium or Fast speed. 398 * @note Warning: only one pin can be passed as parameter. 399 * @note Refer to datasheet for frequency specifications and the power 400 * supply and load conditions for each speed. 401 * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed 402 * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed 403 * @param GPIOx GPIO Port 404 * @param Pin This parameter can be one of the following values: 405 * @arg @ref LL_GPIO_PIN_0 406 * @arg @ref LL_GPIO_PIN_1 407 * @arg @ref LL_GPIO_PIN_2 408 * @arg @ref LL_GPIO_PIN_3 409 * @arg @ref LL_GPIO_PIN_4 410 * @arg @ref LL_GPIO_PIN_5 411 * @arg @ref LL_GPIO_PIN_6 412 * @arg @ref LL_GPIO_PIN_7 413 * @arg @ref LL_GPIO_PIN_8 414 * @arg @ref LL_GPIO_PIN_9 415 * @arg @ref LL_GPIO_PIN_10 416 * @arg @ref LL_GPIO_PIN_11 417 * @arg @ref LL_GPIO_PIN_12 418 * @arg @ref LL_GPIO_PIN_13 419 * @arg @ref LL_GPIO_PIN_14 420 * @arg @ref LL_GPIO_PIN_15 421 * @param Speed This parameter can be one of the following values: 422 * @arg @ref LL_GPIO_SPEED_FREQ_LOW 423 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM 424 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH 425 * @retval None 426 */ 427 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, 428 uint32_t Speed) 429 { 430 register uint32_t *pReg = 431 (uint32_t*) ((uint32_t) ((uint32_t) (&GPIOx->CRL) + (Pin >> 24))); 432 MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)), 433 (Speed << (POSITION_VAL(Pin) * 4U))); 434 } 435 436 /** 437 * @brief Return gpio speed for a dedicated pin on dedicated port. 438 * @note I/O speed can be Low, Medium, Fast or High speed. 439 * @note Warning: only one pin can be passed as parameter. 440 * @note Refer to datasheet for frequency specifications and the power 441 * supply and load conditions for each speed. 442 * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed 443 * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed 444 * @param GPIOx GPIO Port 445 * @param Pin This parameter can be one of the following values: 446 * @arg @ref LL_GPIO_PIN_0 447 * @arg @ref LL_GPIO_PIN_1 448 * @arg @ref LL_GPIO_PIN_2 449 * @arg @ref LL_GPIO_PIN_3 450 * @arg @ref LL_GPIO_PIN_4 451 * @arg @ref LL_GPIO_PIN_5 452 * @arg @ref LL_GPIO_PIN_6 453 * @arg @ref LL_GPIO_PIN_7 454 * @arg @ref LL_GPIO_PIN_8 455 * @arg @ref LL_GPIO_PIN_9 456 * @arg @ref LL_GPIO_PIN_10 457 * @arg @ref LL_GPIO_PIN_11 458 * @arg @ref LL_GPIO_PIN_12 459 * @arg @ref LL_GPIO_PIN_13 460 * @arg @ref LL_GPIO_PIN_14 461 * @arg @ref LL_GPIO_PIN_15 462 * @retval Returned value can be one of the following values: 463 * @arg @ref LL_GPIO_SPEED_FREQ_LOW 464 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM 465 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH 466 */ 467 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, 468 uint32_t Pin) 469 { 470 register uint32_t *pReg = 471 (uint32_t*) ((uint32_t) ((uint32_t) (&GPIOx->CRL) + (Pin >> 24))); 472 return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) 473 >> (POSITION_VAL(Pin) * 4U)); 474 } 475 476 /** 477 * @brief Configure gpio output type for several pins on dedicated port. 478 * @note Output type as to be set when gpio pin is in output or 479 * alternate modes. Possible type are Push-pull or Open-drain. 480 * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType 481 * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType 482 * @param GPIOx GPIO Port 483 * @param Pin This parameter can be a combination of the following values: 484 * @arg @ref LL_GPIO_PIN_0 485 * @arg @ref LL_GPIO_PIN_1 486 * @arg @ref LL_GPIO_PIN_2 487 * @arg @ref LL_GPIO_PIN_3 488 * @arg @ref LL_GPIO_PIN_4 489 * @arg @ref LL_GPIO_PIN_5 490 * @arg @ref LL_GPIO_PIN_6 491 * @arg @ref LL_GPIO_PIN_7 492 * @arg @ref LL_GPIO_PIN_8 493 * @arg @ref LL_GPIO_PIN_9 494 * @arg @ref LL_GPIO_PIN_10 495 * @arg @ref LL_GPIO_PIN_11 496 * @arg @ref LL_GPIO_PIN_12 497 * @arg @ref LL_GPIO_PIN_13 498 * @arg @ref LL_GPIO_PIN_14 499 * @arg @ref LL_GPIO_PIN_15 500 * @arg @ref LL_GPIO_PIN_ALL 501 * @param OutputType This parameter can be one of the following values: 502 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL 503 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN 504 * @retval None 505 */ 506 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, 507 uint32_t Pin, uint32_t OutputType) 508 { 509 register uint32_t *pReg = 510 (uint32_t*) ((uint32_t) ((uint32_t) (&GPIOx->CRL) + (Pin >> 24))); 511 MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)), 512 (OutputType << (POSITION_VAL(Pin) * 4U))); 513 } 514 515 /** 516 * @brief Return gpio output type for several pins on dedicated port. 517 * @note Output type as to be set when gpio pin is in output or 518 * alternate modes. Possible type are Push-pull or Open-drain. 519 * @note Warning: only one pin can be passed as parameter. 520 * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType 521 * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType 522 * @param GPIOx GPIO Port 523 * @param Pin This parameter can be one of the following values: 524 * @arg @ref LL_GPIO_PIN_0 525 * @arg @ref LL_GPIO_PIN_1 526 * @arg @ref LL_GPIO_PIN_2 527 * @arg @ref LL_GPIO_PIN_3 528 * @arg @ref LL_GPIO_PIN_4 529 * @arg @ref LL_GPIO_PIN_5 530 * @arg @ref LL_GPIO_PIN_6 531 * @arg @ref LL_GPIO_PIN_7 532 * @arg @ref LL_GPIO_PIN_8 533 * @arg @ref LL_GPIO_PIN_9 534 * @arg @ref LL_GPIO_PIN_10 535 * @arg @ref LL_GPIO_PIN_11 536 * @arg @ref LL_GPIO_PIN_12 537 * @arg @ref LL_GPIO_PIN_13 538 * @arg @ref LL_GPIO_PIN_14 539 * @arg @ref LL_GPIO_PIN_15 540 * @arg @ref LL_GPIO_PIN_ALL 541 * @retval Returned value can be one of the following values: 542 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL 543 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN 544 */ 545 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, 546 uint32_t Pin) 547 { 548 register uint32_t *pReg = 549 (uint32_t*) ((uint32_t) ((uint32_t) (&GPIOx->CRL) + (Pin >> 24))); 550 return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) 551 >> (POSITION_VAL(Pin) * 4U)); 552 553 } 554 555 /** 556 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. 557 * @note Warning: only one pin can be passed as parameter. 558 * @rmtoll ODR ODR LL_GPIO_SetPinPull 559 * @param GPIOx GPIO Port 560 * @param Pin This parameter can be one of the following values: 561 * @arg @ref LL_GPIO_PIN_0 562 * @arg @ref LL_GPIO_PIN_1 563 * @arg @ref LL_GPIO_PIN_2 564 * @arg @ref LL_GPIO_PIN_3 565 * @arg @ref LL_GPIO_PIN_4 566 * @arg @ref LL_GPIO_PIN_5 567 * @arg @ref LL_GPIO_PIN_6 568 * @arg @ref LL_GPIO_PIN_7 569 * @arg @ref LL_GPIO_PIN_8 570 * @arg @ref LL_GPIO_PIN_9 571 * @arg @ref LL_GPIO_PIN_10 572 * @arg @ref LL_GPIO_PIN_11 573 * @arg @ref LL_GPIO_PIN_12 574 * @arg @ref LL_GPIO_PIN_13 575 * @arg @ref LL_GPIO_PIN_14 576 * @arg @ref LL_GPIO_PIN_15 577 * @param Pull This parameter can be one of the following values: 578 * @arg @ref LL_GPIO_PULL_DOWN 579 * @arg @ref LL_GPIO_PULL_UP 580 * @retval None 581 */ 582 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, 583 uint32_t Pull) 584 { 585 MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), 586 Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); 587 } 588 589 /** 590 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port 591 * @note Warning: only one pin can be passed as parameter. 592 * @rmtoll ODR ODR LL_GPIO_GetPinPull 593 * @param GPIOx GPIO Port 594 * @param Pin This parameter can be one of the following values: 595 * @arg @ref LL_GPIO_PIN_0 596 * @arg @ref LL_GPIO_PIN_1 597 * @arg @ref LL_GPIO_PIN_2 598 * @arg @ref LL_GPIO_PIN_3 599 * @arg @ref LL_GPIO_PIN_4 600 * @arg @ref LL_GPIO_PIN_5 601 * @arg @ref LL_GPIO_PIN_6 602 * @arg @ref LL_GPIO_PIN_7 603 * @arg @ref LL_GPIO_PIN_8 604 * @arg @ref LL_GPIO_PIN_9 605 * @arg @ref LL_GPIO_PIN_10 606 * @arg @ref LL_GPIO_PIN_11 607 * @arg @ref LL_GPIO_PIN_12 608 * @arg @ref LL_GPIO_PIN_13 609 * @arg @ref LL_GPIO_PIN_14 610 * @arg @ref LL_GPIO_PIN_15 611 * @retval Returned value can be one of the following values: 612 * @arg @ref LL_GPIO_PULL_DOWN 613 * @arg @ref LL_GPIO_PULL_UP 614 */ 615 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, 616 uint32_t Pin) 617 { 618 return (READ_BIT(GPIOx->ODR, 619 (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) 620 >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); 621 } 622 623 /** 624 * @brief Lock configuration of several pins for a dedicated port. 625 * @note When the lock sequence has been applied on a port bit, the 626 * value of this port bit can no longer be modified until the 627 * next reset. 628 * @note Each lock bit freezes a specific configuration register 629 * (control and alternate function registers). 630 * @rmtoll LCKR LCKK LL_GPIO_LockPin 631 * @param GPIOx GPIO Port 632 * @param PinMask This parameter can be a combination of the following values: 633 * @arg @ref LL_GPIO_PIN_0 634 * @arg @ref LL_GPIO_PIN_1 635 * @arg @ref LL_GPIO_PIN_2 636 * @arg @ref LL_GPIO_PIN_3 637 * @arg @ref LL_GPIO_PIN_4 638 * @arg @ref LL_GPIO_PIN_5 639 * @arg @ref LL_GPIO_PIN_6 640 * @arg @ref LL_GPIO_PIN_7 641 * @arg @ref LL_GPIO_PIN_8 642 * @arg @ref LL_GPIO_PIN_9 643 * @arg @ref LL_GPIO_PIN_10 644 * @arg @ref LL_GPIO_PIN_11 645 * @arg @ref LL_GPIO_PIN_12 646 * @arg @ref LL_GPIO_PIN_13 647 * @arg @ref LL_GPIO_PIN_14 648 * @arg @ref LL_GPIO_PIN_15 649 * @arg @ref LL_GPIO_PIN_ALL 650 * @retval None 651 */ 652 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) 653 { 654 __IO uint32_t temp; 655 WRITE_REG(GPIOx->LCKR, 656 GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 657 WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 658 WRITE_REG(GPIOx->LCKR, 659 GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 660 temp = READ_REG(GPIOx->LCKR); 661 (void) temp; 662 } 663 664 /** 665 * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. 666 * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked 667 * @param GPIOx GPIO Port 668 * @param PinMask This parameter can be a combination of the following values: 669 * @arg @ref LL_GPIO_PIN_0 670 * @arg @ref LL_GPIO_PIN_1 671 * @arg @ref LL_GPIO_PIN_2 672 * @arg @ref LL_GPIO_PIN_3 673 * @arg @ref LL_GPIO_PIN_4 674 * @arg @ref LL_GPIO_PIN_5 675 * @arg @ref LL_GPIO_PIN_6 676 * @arg @ref LL_GPIO_PIN_7 677 * @arg @ref LL_GPIO_PIN_8 678 * @arg @ref LL_GPIO_PIN_9 679 * @arg @ref LL_GPIO_PIN_10 680 * @arg @ref LL_GPIO_PIN_11 681 * @arg @ref LL_GPIO_PIN_12 682 * @arg @ref LL_GPIO_PIN_13 683 * @arg @ref LL_GPIO_PIN_14 684 * @arg @ref LL_GPIO_PIN_15 685 * @arg @ref LL_GPIO_PIN_ALL 686 * @retval State of bit (1 or 0). 687 */ 688 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, 689 uint32_t PinMask) 690 { 691 return (READ_BIT(GPIOx->LCKR, 692 ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) 693 == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 694 } 695 696 /** 697 * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. 698 * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked 699 * @param GPIOx GPIO Port 700 * @retval State of bit (1 or 0). 701 */ 702 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) 703 { 704 return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); 705 } 706 707 /** 708 * @} 709 */ 710 711 /** @defgroup GPIO_LL_EF_Data_Access Data Access 712 * @{ 713 */ 714 715 /** 716 * @brief Return full input data register value for a dedicated port. 717 * @rmtoll IDR IDy LL_GPIO_ReadInputPort 718 * @param GPIOx GPIO Port 719 * @retval Input data register value of port 720 */ 721 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) 722 { 723 return (READ_REG(GPIOx->IDR)); 724 } 725 726 /** 727 * @brief Return if input data level for several pins of dedicated port is high or low. 728 * @rmtoll IDR IDy LL_GPIO_IsInputPinSet 729 * @param GPIOx GPIO Port 730 * @param PinMask This parameter can be a combination of the following values: 731 * @arg @ref LL_GPIO_PIN_0 732 * @arg @ref LL_GPIO_PIN_1 733 * @arg @ref LL_GPIO_PIN_2 734 * @arg @ref LL_GPIO_PIN_3 735 * @arg @ref LL_GPIO_PIN_4 736 * @arg @ref LL_GPIO_PIN_5 737 * @arg @ref LL_GPIO_PIN_6 738 * @arg @ref LL_GPIO_PIN_7 739 * @arg @ref LL_GPIO_PIN_8 740 * @arg @ref LL_GPIO_PIN_9 741 * @arg @ref LL_GPIO_PIN_10 742 * @arg @ref LL_GPIO_PIN_11 743 * @arg @ref LL_GPIO_PIN_12 744 * @arg @ref LL_GPIO_PIN_13 745 * @arg @ref LL_GPIO_PIN_14 746 * @arg @ref LL_GPIO_PIN_15 747 * @arg @ref LL_GPIO_PIN_ALL 748 * @retval State of bit (1 or 0). 749 */ 750 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, 751 uint32_t PinMask) 752 { 753 return (READ_BIT(GPIOx->IDR, 754 (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) 755 == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 756 } 757 758 /** 759 * @brief Write output data register for the port. 760 * @rmtoll ODR ODy LL_GPIO_WriteOutputPort 761 * @param GPIOx GPIO Port 762 * @param PortValue Level value for each pin of the port 763 * @retval None 764 */ 765 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, 766 uint32_t PortValue) 767 { 768 WRITE_REG(GPIOx->ODR, PortValue); 769 } 770 771 /** 772 * @brief Return full output data register value for a dedicated port. 773 * @rmtoll ODR ODy LL_GPIO_ReadOutputPort 774 * @param GPIOx GPIO Port 775 * @retval Output data register value of port 776 */ 777 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) 778 { 779 return (uint32_t) (READ_REG(GPIOx->ODR)); 780 } 781 782 /** 783 * @brief Return if input data level for several pins of dedicated port is high or low. 784 * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet 785 * @param GPIOx GPIO Port 786 * @param PinMask This parameter can be a combination of the following values: 787 * @arg @ref LL_GPIO_PIN_0 788 * @arg @ref LL_GPIO_PIN_1 789 * @arg @ref LL_GPIO_PIN_2 790 * @arg @ref LL_GPIO_PIN_3 791 * @arg @ref LL_GPIO_PIN_4 792 * @arg @ref LL_GPIO_PIN_5 793 * @arg @ref LL_GPIO_PIN_6 794 * @arg @ref LL_GPIO_PIN_7 795 * @arg @ref LL_GPIO_PIN_8 796 * @arg @ref LL_GPIO_PIN_9 797 * @arg @ref LL_GPIO_PIN_10 798 * @arg @ref LL_GPIO_PIN_11 799 * @arg @ref LL_GPIO_PIN_12 800 * @arg @ref LL_GPIO_PIN_13 801 * @arg @ref LL_GPIO_PIN_14 802 * @arg @ref LL_GPIO_PIN_15 803 * @arg @ref LL_GPIO_PIN_ALL 804 * @retval State of bit (1 or 0). 805 */ 806 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, 807 uint32_t PinMask) 808 { 809 return (READ_BIT(GPIOx->ODR, 810 (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) 811 == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 812 } 813 814 /** 815 * @brief Set several pins to high level on dedicated gpio port. 816 * @rmtoll BSRR BSy LL_GPIO_SetOutputPin 817 * @param GPIOx GPIO Port 818 * @param PinMask This parameter can be a combination of the following values: 819 * @arg @ref LL_GPIO_PIN_0 820 * @arg @ref LL_GPIO_PIN_1 821 * @arg @ref LL_GPIO_PIN_2 822 * @arg @ref LL_GPIO_PIN_3 823 * @arg @ref LL_GPIO_PIN_4 824 * @arg @ref LL_GPIO_PIN_5 825 * @arg @ref LL_GPIO_PIN_6 826 * @arg @ref LL_GPIO_PIN_7 827 * @arg @ref LL_GPIO_PIN_8 828 * @arg @ref LL_GPIO_PIN_9 829 * @arg @ref LL_GPIO_PIN_10 830 * @arg @ref LL_GPIO_PIN_11 831 * @arg @ref LL_GPIO_PIN_12 832 * @arg @ref LL_GPIO_PIN_13 833 * @arg @ref LL_GPIO_PIN_14 834 * @arg @ref LL_GPIO_PIN_15 835 * @arg @ref LL_GPIO_PIN_ALL 836 * @retval None 837 */ 838 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, 839 uint32_t PinMask) 840 { 841 WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); 842 } 843 844 /** 845 * @brief Set several pins to low level on dedicated gpio port. 846 * @rmtoll BRR BRy LL_GPIO_ResetOutputPin 847 * @param GPIOx GPIO Port 848 * @param PinMask This parameter can be a combination of the following values: 849 * @arg @ref LL_GPIO_PIN_0 850 * @arg @ref LL_GPIO_PIN_1 851 * @arg @ref LL_GPIO_PIN_2 852 * @arg @ref LL_GPIO_PIN_3 853 * @arg @ref LL_GPIO_PIN_4 854 * @arg @ref LL_GPIO_PIN_5 855 * @arg @ref LL_GPIO_PIN_6 856 * @arg @ref LL_GPIO_PIN_7 857 * @arg @ref LL_GPIO_PIN_8 858 * @arg @ref LL_GPIO_PIN_9 859 * @arg @ref LL_GPIO_PIN_10 860 * @arg @ref LL_GPIO_PIN_11 861 * @arg @ref LL_GPIO_PIN_12 862 * @arg @ref LL_GPIO_PIN_13 863 * @arg @ref LL_GPIO_PIN_14 864 * @arg @ref LL_GPIO_PIN_15 865 * @arg @ref LL_GPIO_PIN_ALL 866 * @retval None 867 */ 868 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, 869 uint32_t PinMask) 870 { 871 WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); 872 } 873 874 /** 875 * @brief Toggle data value for several pin of dedicated port. 876 * @rmtoll ODR ODy LL_GPIO_TogglePin 877 * @param GPIOx GPIO Port 878 * @param PinMask This parameter can be a combination of the following values: 879 * @arg @ref LL_GPIO_PIN_0 880 * @arg @ref LL_GPIO_PIN_1 881 * @arg @ref LL_GPIO_PIN_2 882 * @arg @ref LL_GPIO_PIN_3 883 * @arg @ref LL_GPIO_PIN_4 884 * @arg @ref LL_GPIO_PIN_5 885 * @arg @ref LL_GPIO_PIN_6 886 * @arg @ref LL_GPIO_PIN_7 887 * @arg @ref LL_GPIO_PIN_8 888 * @arg @ref LL_GPIO_PIN_9 889 * @arg @ref LL_GPIO_PIN_10 890 * @arg @ref LL_GPIO_PIN_11 891 * @arg @ref LL_GPIO_PIN_12 892 * @arg @ref LL_GPIO_PIN_13 893 * @arg @ref LL_GPIO_PIN_14 894 * @arg @ref LL_GPIO_PIN_15 895 * @arg @ref LL_GPIO_PIN_ALL 896 * @retval None 897 */ 898 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, 899 uint32_t PinMask) 900 { 901 uint32_t odr = READ_REG(GPIOx->ODR); 902 uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); 903 WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask)); 904 } 905 906 /** 907 * @} 908 */ 909 910 /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping 911 * @brief This section propose definition to remap the alternate function to some other port/pins. 912 * @{ 913 */ 914 915 /** 916 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. 917 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1 918 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) 919 * @retval None 920 */ 921 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void) 922 { 923 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG); 924 } 925 926 /** 927 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. 928 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1 929 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 930 * @retval None 931 */ 932 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void) 933 { 934 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), 935 AFIO_MAPR_SWJ_CFG); 936 } 937 938 /** 939 * @brief Check if SPI1 has been remapped or not 940 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1 941 * @retval State of bit (1 or 0). 942 */ 943 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void) 944 { 945 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) 946 == (AFIO_MAPR_SPI1_REMAP)); 947 } 948 949 /** 950 * @brief Enable the remapping of I2C1 alternate function SCL and SDA. 951 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1 952 * @note ENABLE: Remap (SCL/PB8, SDA/PB9) 953 * @retval None 954 */ 955 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void) 956 { 957 SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG); 958 } 959 960 /** 961 * @brief Disable the remapping of I2C1 alternate function SCL and SDA. 962 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1 963 * @note DISABLE: No remap (SCL/PB6, SDA/PB7) 964 * @retval None 965 */ 966 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void) 967 { 968 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), 969 AFIO_MAPR_SWJ_CFG); 970 } 971 972 /** 973 * @brief Check if I2C1 has been remapped or not 974 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1 975 * @retval State of bit (1 or 0). 976 */ 977 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void) 978 { 979 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) 980 == (AFIO_MAPR_I2C1_REMAP)); 981 } 982 983 /** 984 * @brief Enable the remapping of USART1 alternate function TX and RX. 985 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1 986 * @note ENABLE: Remap (TX/PB6, RX/PB7) 987 * @retval None 988 */ 989 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void) 990 { 991 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG); 992 } 993 994 /** 995 * @brief Disable the remapping of USART1 alternate function TX and RX. 996 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1 997 * @note DISABLE: No remap (TX/PA9, RX/PA10) 998 * @retval None 999 */ 1000 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void) 1001 { 1002 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), 1003 AFIO_MAPR_SWJ_CFG); 1004 } 1005 1006 /** 1007 * @brief Check if USART1 has been remapped or not 1008 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1 1009 * @retval State of bit (1 or 0). 1010 */ 1011 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void) 1012 { 1013 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) 1014 == (AFIO_MAPR_USART1_REMAP)); 1015 } 1016 1017 /** 1018 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. 1019 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2 1020 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) 1021 * @retval None 1022 */ 1023 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void) 1024 { 1025 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG); 1026 } 1027 1028 /** 1029 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. 1030 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2 1031 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 1032 * @retval None 1033 */ 1034 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void) 1035 { 1036 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), 1037 AFIO_MAPR_SWJ_CFG); 1038 } 1039 1040 /** 1041 * @brief Check if USART2 has been remapped or not 1042 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2 1043 * @retval State of bit (1 or 0). 1044 */ 1045 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void) 1046 { 1047 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) 1048 == (AFIO_MAPR_USART2_REMAP)); 1049 } 1050 1051 #if defined (AFIO_MAPR_USART3_REMAP) 1052 /** 1053 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 1054 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3 1055 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) 1056 * @retval None 1057 */ 1058 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void) 1059 { 1060 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), 1061 (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); 1062 } 1063 1064 /** 1065 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 1066 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3 1067 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 1068 * @retval None 1069 */ 1070 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void) 1071 { 1072 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), 1073 (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); 1074 } 1075 1076 /** 1077 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 1078 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3 1079 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 1080 * @retval None 1081 */ 1082 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void) 1083 { 1084 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), 1085 (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); 1086 } 1087 #endif 1088 1089 /** 1090 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 1091 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1 1092 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) 1093 * @retval None 1094 */ 1095 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void) 1096 { 1097 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), 1098 (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); 1099 } 1100 1101 /** 1102 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 1103 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1 1104 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 1105 * @retval None 1106 */ 1107 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void) 1108 { 1109 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), 1110 (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); 1111 } 1112 1113 /** 1114 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 1115 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1 1116 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 1117 * @retval None 1118 */ 1119 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void) 1120 { 1121 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), 1122 (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); 1123 } 1124 1125 /** 1126 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 1127 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2 1128 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) 1129 * @retval None 1130 */ 1131 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void) 1132 { 1133 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), 1134 (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); 1135 } 1136 1137 /** 1138 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 1139 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2 1140 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 1141 * @retval None 1142 */ 1143 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void) 1144 { 1145 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), 1146 (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG)); 1147 } 1148 1149 /** 1150 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 1151 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2 1152 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 1153 * @retval None 1154 */ 1155 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void) 1156 { 1157 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), 1158 (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG)); 1159 } 1160 1161 /** 1162 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 1163 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2 1164 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 1165 * @retval None 1166 */ 1167 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void) 1168 { 1169 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), 1170 (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); 1171 } 1172 1173 /** 1174 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 1175 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3 1176 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) 1177 * @note TIM3_ETR on PE0 is not re-mapped. 1178 * @retval None 1179 */ 1180 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void) 1181 { 1182 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), 1183 (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); 1184 } 1185 1186 /** 1187 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 1188 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3 1189 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 1190 * @note TIM3_ETR on PE0 is not re-mapped. 1191 * @retval None 1192 */ 1193 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void) 1194 { 1195 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), 1196 (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); 1197 } 1198 1199 /** 1200 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 1201 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3 1202 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 1203 * @note TIM3_ETR on PE0 is not re-mapped. 1204 * @retval None 1205 */ 1206 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void) 1207 { 1208 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), 1209 (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); 1210 } 1211 1212 #if defined(AFIO_MAPR_TIM4_REMAP) 1213 /** 1214 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. 1215 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4 1216 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) 1217 * @note TIM4_ETR on PE0 is not re-mapped. 1218 * @retval None 1219 */ 1220 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void) 1221 { 1222 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG); 1223 } 1224 /** 1225 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. 1226 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4 1227 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 1228 * @note TIM4_ETR on PE0 is not re-mapped. 1229 * @retval None 1230 */ 1231 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void) 1232 { 1233 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), 1234 AFIO_MAPR_SWJ_CFG); 1235 } 1236 1237 /** 1238 * @brief Check if TIM4 has been remapped or not 1239 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4 1240 * @retval State of bit (1 or 0). 1241 */ 1242 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void) 1243 { 1244 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) 1245 == (AFIO_MAPR_TIM4_REMAP)); 1246 } 1247 #endif 1248 1249 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) 1250 1251 /** 1252 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 1253 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1 1254 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 1255 * @retval None 1256 */ 1257 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void) 1258 { 1259 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), 1260 (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG)); 1261 } 1262 1263 /** 1264 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 1265 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1 1266 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) 1267 * @retval None 1268 */ 1269 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void) 1270 { 1271 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), 1272 (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG)); 1273 } 1274 1275 /** 1276 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 1277 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1 1278 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 1279 * @retval None 1280 */ 1281 __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void) 1282 { 1283 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), 1284 (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG)); 1285 } 1286 #endif 1287 1288 /** 1289 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used 1290 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 1291 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 1292 * on 100-pin and 144-pin packages, no need for remapping). 1293 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01 1294 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. 1295 * @retval None 1296 */ 1297 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void) 1298 { 1299 SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG); 1300 } 1301 1302 /** 1303 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used 1304 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 1305 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 1306 * on 100-pin and 144-pin packages, no need for remapping). 1307 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01 1308 * @note DISABLE: No remapping of PD0 and PD1 1309 * @retval None 1310 */ 1311 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void) 1312 { 1313 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), 1314 AFIO_MAPR_SWJ_CFG); 1315 } 1316 1317 /** 1318 * @brief Check if PD01 has been remapped or not 1319 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01 1320 * @retval State of bit (1 or 0). 1321 */ 1322 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void) 1323 { 1324 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) 1325 == (AFIO_MAPR_PD01_REMAP)); 1326 } 1327 1328 #if defined(AFIO_MAPR_TIM5CH4_IREMAP) 1329 /** 1330 * @brief Enable the remapping of TIM5CH4. 1331 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4 1332 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. 1333 * @note This function is available only in high density value line devices. 1334 * @retval None 1335 */ 1336 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void) 1337 { 1338 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG); 1339 } 1340 1341 /** 1342 * @brief Disable the remapping of TIM5CH4. 1343 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4 1344 * @note DISABLE: TIM5_CH4 is connected to PA3 1345 * @note This function is available only in high density value line devices. 1346 * @retval None 1347 */ 1348 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void) 1349 { 1350 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1351 } 1352 1353 /** 1354 * @brief Check if TIM5CH4 has been remapped or not 1355 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4 1356 * @retval State of bit (1 or 0). 1357 */ 1358 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void) 1359 { 1360 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP)); 1361 } 1362 #endif 1363 1364 #if defined(AFIO_MAPR_ETH_REMAP) 1365 /** 1366 * @brief Enable the remapping of Ethernet MAC connections with the PHY. 1367 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH 1368 * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) 1369 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1370 * @retval None 1371 */ 1372 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void) 1373 { 1374 SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG); 1375 } 1376 1377 /** 1378 * @brief Disable the remapping of Ethernet MAC connections with the PHY. 1379 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH 1380 * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) 1381 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1382 * @retval None 1383 */ 1384 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void) 1385 { 1386 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1387 } 1388 1389 /** 1390 * @brief Check if ETH has been remapped or not 1391 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH 1392 * @retval State of bit (1 or 0). 1393 */ 1394 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void) 1395 { 1396 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP)); 1397 } 1398 #endif 1399 1400 #if defined(AFIO_MAPR_CAN2_REMAP) 1401 1402 /** 1403 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. 1404 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2 1405 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) 1406 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1407 * @retval None 1408 */ 1409 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void) 1410 { 1411 SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG); 1412 } 1413 /** 1414 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. 1415 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2 1416 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) 1417 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1418 * @retval None 1419 */ 1420 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void) 1421 { 1422 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1423 } 1424 1425 /** 1426 * @brief Check if CAN2 has been remapped or not 1427 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2 1428 * @retval State of bit (1 or 0). 1429 */ 1430 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void) 1431 { 1432 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP)); 1433 } 1434 #endif 1435 1436 #if defined(AFIO_MAPR_MII_RMII_SEL) 1437 /** 1438 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. 1439 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII 1440 * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY 1441 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1442 * @retval None 1443 */ 1444 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void) 1445 { 1446 SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG); 1447 } 1448 1449 /** 1450 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. 1451 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII 1452 * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY 1453 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1454 * @retval None 1455 */ 1456 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void) 1457 { 1458 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1459 } 1460 #endif 1461 1462 #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP) 1463 /** 1464 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). 1465 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ 1466 * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. 1467 * @retval None 1468 */ 1469 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void) 1470 { 1471 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); 1472 } 1473 1474 /** 1475 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). 1476 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ 1477 * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 1478 * @retval None 1479 */ 1480 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void) 1481 { 1482 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1483 } 1484 1485 /** 1486 * @brief Check if ADC1_ETRGINJ has been remapped or not 1487 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ 1488 * @retval State of bit (1 or 0). 1489 */ 1490 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void) 1491 { 1492 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP)); 1493 } 1494 #endif 1495 1496 #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP) 1497 /** 1498 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). 1499 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG 1500 * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. 1501 * @retval None 1502 */ 1503 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void) 1504 { 1505 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); 1506 } 1507 1508 /** 1509 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). 1510 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG 1511 * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 1512 * @retval None 1513 */ 1514 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void) 1515 { 1516 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1517 } 1518 1519 /** 1520 * @brief Check if ADC1_ETRGREG has been remapped or not 1521 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG 1522 * @retval State of bit (1 or 0). 1523 */ 1524 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void) 1525 { 1526 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP)); 1527 } 1528 #endif 1529 1530 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) 1531 1532 /** 1533 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). 1534 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ 1535 * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. 1536 * @retval None 1537 */ 1538 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void) 1539 { 1540 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); 1541 } 1542 1543 /** 1544 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). 1545 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ 1546 * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 1547 * @retval None 1548 */ 1549 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void) 1550 { 1551 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1552 } 1553 1554 /** 1555 * @brief Check if ADC2_ETRGINJ has been remapped or not 1556 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ 1557 * @retval State of bit (1 or 0). 1558 */ 1559 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void) 1560 { 1561 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP)); 1562 } 1563 #endif 1564 1565 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) 1566 1567 /** 1568 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 1569 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG 1570 * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. 1571 * @retval None 1572 */ 1573 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void) 1574 { 1575 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); 1576 } 1577 1578 /** 1579 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 1580 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG 1581 * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 1582 * @retval None 1583 */ 1584 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void) 1585 { 1586 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1587 } 1588 1589 /** 1590 * @brief Check if ADC2_ETRGREG has been remapped or not 1591 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG 1592 * @retval State of bit (1 or 0). 1593 */ 1594 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void) 1595 { 1596 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP)); 1597 } 1598 #endif 1599 1600 /** 1601 * @brief Enable the Serial wire JTAG configuration 1602 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ 1603 * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State 1604 * @retval None 1605 */ 1606 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void) 1607 { 1608 MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET); 1609 } 1610 1611 /** 1612 * @brief Enable the Serial wire JTAG configuration 1613 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST 1614 * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST 1615 * @retval None 1616 */ 1617 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void) 1618 { 1619 MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST); 1620 } 1621 1622 /** 1623 * @brief Enable the Serial wire JTAG configuration 1624 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG 1625 * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled 1626 * @retval None 1627 */ 1628 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void) 1629 { 1630 MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, 1631 AFIO_MAPR_SWJ_CFG_JTAGDISABLE); 1632 } 1633 1634 /** 1635 * @brief Disable the Serial wire JTAG configuration 1636 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ 1637 * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled 1638 * @retval None 1639 */ 1640 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void) 1641 { 1642 MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE); 1643 } 1644 1645 #if defined(AFIO_MAPR_SPI3_REMAP) 1646 1647 /** 1648 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. 1649 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3 1650 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) 1651 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1652 * @retval None 1653 */ 1654 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void) 1655 { 1656 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG); 1657 } 1658 1659 /** 1660 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. 1661 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3 1662 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). 1663 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1664 * @retval None 1665 */ 1666 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void) 1667 { 1668 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1669 } 1670 1671 /** 1672 * @brief Check if SPI3 has been remapped or not 1673 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP 1674 * @retval State of bit (1 or 0). 1675 */ 1676 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void) 1677 { 1678 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP)); 1679 } 1680 #endif 1681 1682 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) 1683 1684 /** 1685 * @brief Control of TIM2_ITR1 internal mapping. 1686 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB 1687 * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. 1688 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1689 * @retval None 1690 */ 1691 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void) 1692 { 1693 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG); 1694 } 1695 1696 /** 1697 * @brief Control of TIM2_ITR1 internal mapping. 1698 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH 1699 * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. 1700 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1701 * @retval None 1702 */ 1703 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void) 1704 { 1705 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1706 } 1707 #endif 1708 1709 #if defined(AFIO_MAPR_PTP_PPS_REMAP) 1710 1711 /** 1712 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 1713 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS 1714 * @note ENABLE: PTP_PPS is output on PB5 pin. 1715 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1716 * @retval None 1717 */ 1718 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void) 1719 { 1720 SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG); 1721 } 1722 1723 /** 1724 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 1725 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS 1726 * @note DISABLE: PTP_PPS not output on PB5 pin. 1727 * @note This bit is available only in connectivity line devices and is reserved otherwise. 1728 * @retval None 1729 */ 1730 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void) 1731 { 1732 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 1733 } 1734 #endif 1735 1736 #if defined(AFIO_MAPR2_TIM9_REMAP) 1737 1738 /** 1739 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. 1740 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9 1741 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). 1742 * @retval None 1743 */ 1744 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void) 1745 { 1746 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); 1747 } 1748 1749 /** 1750 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. 1751 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9 1752 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). 1753 * @retval None 1754 */ 1755 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void) 1756 { 1757 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); 1758 } 1759 1760 /** 1761 * @brief Check if TIM9_CH1 and TIM9_CH2 have been remapped or not 1762 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9 1763 * @retval State of bit (1 or 0). 1764 */ 1765 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void) 1766 { 1767 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP)); 1768 } 1769 #endif 1770 1771 #if defined(AFIO_MAPR2_TIM10_REMAP) 1772 1773 /** 1774 * @brief Enable the remapping of TIM10_CH1. 1775 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10 1776 * @note ENABLE: Remap (TIM10_CH1 on PF6). 1777 * @retval None 1778 */ 1779 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void) 1780 { 1781 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); 1782 } 1783 1784 /** 1785 * @brief Disable the remapping of TIM10_CH1. 1786 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10 1787 * @note DISABLE: No remap (TIM10_CH1 on PB8). 1788 * @retval None 1789 */ 1790 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void) 1791 { 1792 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); 1793 } 1794 1795 /** 1796 * @brief Check if TIM10_CH1 has been remapped or not 1797 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10 1798 * @retval State of bit (1 or 0). 1799 */ 1800 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void) 1801 { 1802 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP)); 1803 } 1804 #endif 1805 1806 #if defined(AFIO_MAPR2_TIM11_REMAP) 1807 /** 1808 * @brief Enable the remapping of TIM11_CH1. 1809 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11 1810 * @note ENABLE: Remap (TIM11_CH1 on PF7). 1811 * @retval None 1812 */ 1813 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void) 1814 { 1815 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); 1816 } 1817 1818 /** 1819 * @brief Disable the remapping of TIM11_CH1. 1820 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11 1821 * @note DISABLE: No remap (TIM11_CH1 on PB9). 1822 * @retval None 1823 */ 1824 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void) 1825 { 1826 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); 1827 } 1828 1829 /** 1830 * @brief Check if TIM11_CH1 has been remapped or not 1831 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11 1832 * @retval State of bit (1 or 0). 1833 */ 1834 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void) 1835 { 1836 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP)); 1837 } 1838 #endif 1839 1840 #if defined(AFIO_MAPR2_TIM13_REMAP) 1841 1842 /** 1843 * @brief Enable the remapping of TIM13_CH1. 1844 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13 1845 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). 1846 * @retval None 1847 */ 1848 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void) 1849 { 1850 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); 1851 } 1852 1853 /** 1854 * @brief Disable the remapping of TIM13_CH1. 1855 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13 1856 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). 1857 * @retval None 1858 */ 1859 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void) 1860 { 1861 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); 1862 } 1863 1864 /** 1865 * @brief Check if TIM13_CH1 has been remapped or not 1866 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13 1867 * @retval State of bit (1 or 0). 1868 */ 1869 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void) 1870 { 1871 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP)); 1872 } 1873 #endif 1874 1875 #if defined(AFIO_MAPR2_TIM14_REMAP) 1876 1877 /** 1878 * @brief Enable the remapping of TIM14_CH1. 1879 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14 1880 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). 1881 * @retval None 1882 */ 1883 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void) 1884 { 1885 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); 1886 } 1887 1888 /** 1889 * @brief Disable the remapping of TIM14_CH1. 1890 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14 1891 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). 1892 * @retval None 1893 */ 1894 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void) 1895 { 1896 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); 1897 } 1898 1899 /** 1900 * @brief Check if TIM14_CH1 has been remapped or not 1901 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14 1902 * @retval State of bit (1 or 0). 1903 */ 1904 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void) 1905 { 1906 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP)); 1907 } 1908 #endif 1909 1910 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) 1911 1912 /** 1913 * @brief Controls the use of the optional FSMC_NADV signal. 1914 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV 1915 * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. 1916 * @retval None 1917 */ 1918 __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void) 1919 { 1920 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); 1921 } 1922 1923 /** 1924 * @brief Controls the use of the optional FSMC_NADV signal. 1925 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV 1926 * @note CONNECTED: The NADV signal is connected to the output (default). 1927 * @retval None 1928 */ 1929 __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void) 1930 { 1931 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); 1932 } 1933 #endif 1934 1935 #if defined(AFIO_MAPR2_TIM15_REMAP) 1936 1937 /** 1938 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. 1939 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15 1940 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). 1941 * @retval None 1942 */ 1943 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void) 1944 { 1945 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); 1946 } 1947 /** 1948 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. 1949 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15 1950 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). 1951 * @retval None 1952 */ 1953 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void) 1954 { 1955 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); 1956 } 1957 1958 /** 1959 * @brief Check if TIM15_CH1 has been remapped or not 1960 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15 1961 * @retval State of bit (1 or 0). 1962 */ 1963 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void) 1964 { 1965 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP)); 1966 } 1967 #endif 1968 1969 #if defined(AFIO_MAPR2_TIM16_REMAP) 1970 1971 /** 1972 * @brief Enable the remapping of TIM16_CH1. 1973 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16 1974 * @note ENABLE: Remap (TIM16_CH1 on PA6). 1975 * @retval None 1976 */ 1977 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void) 1978 { 1979 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); 1980 } 1981 1982 /** 1983 * @brief Disable the remapping of TIM16_CH1. 1984 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16 1985 * @note DISABLE: No remap (TIM16_CH1 on PB8). 1986 * @retval None 1987 */ 1988 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void) 1989 { 1990 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); 1991 } 1992 1993 /** 1994 * @brief Check if TIM16_CH1 has been remapped or not 1995 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16 1996 * @retval State of bit (1 or 0). 1997 */ 1998 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void) 1999 { 2000 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP)); 2001 } 2002 #endif 2003 2004 #if defined(AFIO_MAPR2_TIM17_REMAP) 2005 2006 /** 2007 * @brief Enable the remapping of TIM17_CH1. 2008 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17 2009 * @note ENABLE: Remap (TIM17_CH1 on PA7). 2010 * @retval None 2011 */ 2012 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void) 2013 { 2014 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); 2015 } 2016 2017 /** 2018 * @brief Disable the remapping of TIM17_CH1. 2019 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17 2020 * @note DISABLE: No remap (TIM17_CH1 on PB9). 2021 * @retval None 2022 */ 2023 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void) 2024 { 2025 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); 2026 } 2027 2028 /** 2029 * @brief Check if TIM17_CH1 has been remapped or not 2030 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17 2031 * @retval State of bit (1 or 0). 2032 */ 2033 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void) 2034 { 2035 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP)); 2036 } 2037 #endif 2038 2039 #if defined(AFIO_MAPR2_CEC_REMAP) 2040 2041 /** 2042 * @brief Enable the remapping of CEC. 2043 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC 2044 * @note ENABLE: Remap (CEC on PB10). 2045 * @retval None 2046 */ 2047 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void) 2048 { 2049 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); 2050 } 2051 2052 /** 2053 * @brief Disable the remapping of CEC. 2054 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC 2055 * @note DISABLE: No remap (CEC on PB8). 2056 * @retval None 2057 */ 2058 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void) 2059 { 2060 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); 2061 } 2062 2063 /** 2064 * @brief Check if CEC has been remapped or not 2065 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC 2066 * @retval State of bit (1 or 0). 2067 */ 2068 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void) 2069 { 2070 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP)); 2071 } 2072 #endif 2073 2074 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) 2075 2076 /** 2077 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. 2078 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA 2079 * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) 2080 * @retval None 2081 */ 2082 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void) 2083 { 2084 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); 2085 } 2086 2087 /** 2088 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. 2089 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA 2090 * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). 2091 * @retval None 2092 */ 2093 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void) 2094 { 2095 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); 2096 } 2097 2098 /** 2099 * @brief Check if TIM1DMA has been remapped or not 2100 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA 2101 * @retval State of bit (1 or 0). 2102 */ 2103 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void) 2104 { 2105 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP)); 2106 } 2107 #endif 2108 2109 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) 2110 2111 /** 2112 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. 2113 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA 2114 * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) 2115 * @retval None 2116 */ 2117 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void) 2118 { 2119 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); 2120 } 2121 2122 /** 2123 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. 2124 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA 2125 * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) 2126 * @retval None 2127 */ 2128 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void) 2129 { 2130 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); 2131 } 2132 2133 /** 2134 * @brief Check if TIM67DACDMA has been remapped or not 2135 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA 2136 * @retval State of bit (1 or 0). 2137 */ 2138 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void) 2139 { 2140 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP)); 2141 } 2142 #endif 2143 2144 #if defined(AFIO_MAPR2_TIM12_REMAP) 2145 2146 /** 2147 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. 2148 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12 2149 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). 2150 * @note This bit is available only in high density value line devices. 2151 * @retval None 2152 */ 2153 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void) 2154 { 2155 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); 2156 } 2157 2158 /** 2159 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. 2160 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12 2161 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). 2162 * @note This bit is available only in high density value line devices. 2163 * @retval None 2164 */ 2165 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void) 2166 { 2167 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); 2168 } 2169 2170 /** 2171 * @brief Check if TIM12_CH1 has been remapped or not 2172 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12 2173 * @retval State of bit (1 or 0). 2174 */ 2175 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void) 2176 { 2177 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP)); 2178 } 2179 #endif 2180 2181 #if defined(AFIO_MAPR2_MISC_REMAP) 2182 2183 /** 2184 * @brief Miscellaneous features remapping. 2185 * This bit is set and cleared by software. It controls miscellaneous features. 2186 * The DMA2 channel 5 interrupt position in the vector table. 2187 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). 2188 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC 2189 * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is 2190 * selected as DAC Trigger 3, TIM15 triggers TIM1/3. 2191 * @note This bit is available only in high density value line devices. 2192 * @retval None 2193 */ 2194 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void) 2195 { 2196 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); 2197 } 2198 2199 /** 2200 * @brief Miscellaneous features remapping. 2201 * This bit is set and cleared by software. It controls miscellaneous features. 2202 * The DMA2 channel 5 interrupt position in the vector table. 2203 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). 2204 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC 2205 * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO 2206 * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. 2207 * @note This bit is available only in high density value line devices. 2208 * @retval None 2209 */ 2210 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void) 2211 { 2212 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); 2213 } 2214 2215 /** 2216 * @brief Check if MISC has been remapped or not 2217 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC 2218 * @retval State of bit (1 or 0). 2219 */ 2220 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void) 2221 { 2222 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP)); 2223 } 2224 #endif 2225 2226 /** 2227 * @} 2228 */ 2229 2230 /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration 2231 * @brief This section propose definition to Configure EVENTOUT Cortex feature . 2232 * @{ 2233 */ 2234 2235 /** 2236 * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. 2237 * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n 2238 * EVCR PIN LL_GPIO_AF_ConfigEventout 2239 * @param LL_GPIO_PortSource This parameter can be one of the following values: 2240 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A 2241 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B 2242 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C 2243 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D 2244 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E 2245 * @param LL_GPIO_PinSource This parameter can be one of the following values: 2246 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0 2247 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1 2248 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2 2249 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3 2250 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4 2251 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5 2252 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6 2253 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7 2254 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8 2255 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9 2256 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10 2257 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11 2258 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12 2259 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13 2260 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14 2261 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15 2262 * @retval None 2263 */ 2264 __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, 2265 uint32_t LL_GPIO_PinSource) 2266 { 2267 MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), 2268 (LL_GPIO_PortSource) | (LL_GPIO_PinSource)); 2269 } 2270 2271 /** 2272 * @brief Enables the Event Output. 2273 * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout 2274 * @retval None 2275 */ 2276 __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void) 2277 { 2278 SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 2279 } 2280 2281 /** 2282 * @brief Disables the Event Output. 2283 * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout 2284 * @retval None 2285 */ 2286 __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void) 2287 { 2288 CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 2289 } 2290 2291 /** 2292 * @} 2293 */ 2294 /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt 2295 * @brief This section Configure source input for the EXTI external interrupt . 2296 * @{ 2297 */ 2298 2299 /** 2300 * @brief Configure source input for the EXTI external interrupt. 2301 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n 2302 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n 2303 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n 2304 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource 2305 * @param Port This parameter can be one of the following values: 2306 * @arg @ref LL_GPIO_AF_EXTI_PORTA 2307 * @arg @ref LL_GPIO_AF_EXTI_PORTB 2308 * @arg @ref LL_GPIO_AF_EXTI_PORTC 2309 * @arg @ref LL_GPIO_AF_EXTI_PORTD 2310 * @arg @ref LL_GPIO_AF_EXTI_PORTE 2311 * @arg @ref LL_GPIO_AF_EXTI_PORTF 2312 * @arg @ref LL_GPIO_AF_EXTI_PORTG 2313 * @param Line This parameter can be one of the following values: 2314 * @arg @ref LL_GPIO_AF_EXTI_LINE0 2315 * @arg @ref LL_GPIO_AF_EXTI_LINE1 2316 * @arg @ref LL_GPIO_AF_EXTI_LINE2 2317 * @arg @ref LL_GPIO_AF_EXTI_LINE3 2318 * @arg @ref LL_GPIO_AF_EXTI_LINE4 2319 * @arg @ref LL_GPIO_AF_EXTI_LINE5 2320 * @arg @ref LL_GPIO_AF_EXTI_LINE6 2321 * @arg @ref LL_GPIO_AF_EXTI_LINE7 2322 * @arg @ref LL_GPIO_AF_EXTI_LINE8 2323 * @arg @ref LL_GPIO_AF_EXTI_LINE9 2324 * @arg @ref LL_GPIO_AF_EXTI_LINE10 2325 * @arg @ref LL_GPIO_AF_EXTI_LINE11 2326 * @arg @ref LL_GPIO_AF_EXTI_LINE12 2327 * @arg @ref LL_GPIO_AF_EXTI_LINE13 2328 * @arg @ref LL_GPIO_AF_EXTI_LINE14 2329 * @arg @ref LL_GPIO_AF_EXTI_LINE15 2330 * @retval None 2331 */ 2332 __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line) 2333 { 2334 MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), 2335 Port << POSITION_VAL((Line >> 16))); 2336 } 2337 2338 /** 2339 * @brief Get the configured defined for specific EXTI Line 2340 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n 2341 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n 2342 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n 2343 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource 2344 * @param Line This parameter can be one of the following values: 2345 * @arg @ref LL_GPIO_AF_EXTI_LINE0 2346 * @arg @ref LL_GPIO_AF_EXTI_LINE1 2347 * @arg @ref LL_GPIO_AF_EXTI_LINE2 2348 * @arg @ref LL_GPIO_AF_EXTI_LINE3 2349 * @arg @ref LL_GPIO_AF_EXTI_LINE4 2350 * @arg @ref LL_GPIO_AF_EXTI_LINE5 2351 * @arg @ref LL_GPIO_AF_EXTI_LINE6 2352 * @arg @ref LL_GPIO_AF_EXTI_LINE7 2353 * @arg @ref LL_GPIO_AF_EXTI_LINE8 2354 * @arg @ref LL_GPIO_AF_EXTI_LINE9 2355 * @arg @ref LL_GPIO_AF_EXTI_LINE10 2356 * @arg @ref LL_GPIO_AF_EXTI_LINE11 2357 * @arg @ref LL_GPIO_AF_EXTI_LINE12 2358 * @arg @ref LL_GPIO_AF_EXTI_LINE13 2359 * @arg @ref LL_GPIO_AF_EXTI_LINE14 2360 * @arg @ref LL_GPIO_AF_EXTI_LINE15 2361 * @retval Returned value can be one of the following values: 2362 * @arg @ref LL_GPIO_AF_EXTI_PORTA 2363 * @arg @ref LL_GPIO_AF_EXTI_PORTB 2364 * @arg @ref LL_GPIO_AF_EXTI_PORTC 2365 * @arg @ref LL_GPIO_AF_EXTI_PORTD 2366 * @arg @ref LL_GPIO_AF_EXTI_PORTE 2367 * @arg @ref LL_GPIO_AF_EXTI_PORTF 2368 * @arg @ref LL_GPIO_AF_EXTI_PORTG 2369 */ 2370 __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line) 2371 { 2372 return (uint32_t) (READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) 2373 >> POSITION_VAL(Line >> 16)); 2374 } 2375 2376 /** 2377 * @} 2378 */ 2379 2380 #if defined(USE_FULL_LL_DRIVER) 2381 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions 2382 * @{ 2383 */ 2384 2385 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); 2386 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); 2387 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); 2388 2389 /** 2390 * @} 2391 */ 2392 #endif /* USE_FULL_LL_DRIVER */ 2393 2394 /** 2395 * @} 2396 */ 2397 2398 /** 2399 * @} 2400 */ 2401 2402 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */ 2403 /** 2404 * @} 2405 */ 2406 2407 #ifdef __cplusplus 2408 } 2409 #endif 2410 2411 #endif /* STM32F1xx_LL_GPIO_H */ 2412