Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h (65755B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef __STM32F1xx_HAL_RCC_H 20 #define __STM32F1xx_HAL_RCC_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32f1xx_hal_def.h" 28 29 /** @addtogroup STM32F1xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 39 /** @defgroup RCC_Exported_Types RCC Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief RCC PLL configuration structure definition 45 */ 46 typedef struct { 47 uint32_t PLLState; /*!< PLLState: The new state of the PLL. 48 This parameter can be a value of @ref RCC_PLL_Config */ 49 50 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. 51 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 52 53 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock 54 This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ 55 } RCC_PLLInitTypeDef; 56 57 /** 58 * @brief RCC System, AHB and APB busses clock configuration structure definition 59 */ 60 typedef struct { 61 uint32_t ClockType; /*!< The clock to be configured. 62 This parameter can be a value of @ref RCC_System_Clock_Type */ 63 64 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. 65 This parameter can be a value of @ref RCC_System_Clock_Source */ 66 67 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 68 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 69 70 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 71 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 72 73 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 74 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 75 } RCC_ClkInitTypeDef; 76 77 /** 78 * @} 79 */ 80 81 /* Exported constants --------------------------------------------------------*/ 82 /** @defgroup RCC_Exported_Constants RCC Exported Constants 83 * @{ 84 */ 85 86 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 87 * @{ 88 */ 89 90 #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ 91 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ 92 93 /** 94 * @} 95 */ 96 97 /** @defgroup RCC_Oscillator_Type Oscillator Type 98 * @{ 99 */ 100 #define RCC_OSCILLATORTYPE_NONE 0x00000000U 101 #define RCC_OSCILLATORTYPE_HSE 0x00000001U 102 #define RCC_OSCILLATORTYPE_HSI 0x00000002U 103 #define RCC_OSCILLATORTYPE_LSE 0x00000004U 104 #define RCC_OSCILLATORTYPE_LSI 0x00000008U 105 /** 106 * @} 107 */ 108 109 /** @defgroup RCC_HSE_Config HSE Config 110 * @{ 111 */ 112 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 113 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 114 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 115 /** 116 * @} 117 */ 118 119 /** @defgroup RCC_LSE_Config LSE Config 120 * @{ 121 */ 122 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 123 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 124 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 125 126 /** 127 * @} 128 */ 129 130 /** @defgroup RCC_HSI_Config HSI Config 131 * @{ 132 */ 133 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 134 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 135 136 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ 137 138 /** 139 * @} 140 */ 141 142 /** @defgroup RCC_LSI_Config LSI Config 143 * @{ 144 */ 145 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 146 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 147 148 /** 149 * @} 150 */ 151 152 /** @defgroup RCC_PLL_Config PLL Config 153 * @{ 154 */ 155 #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ 156 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ 157 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ 158 159 /** 160 * @} 161 */ 162 163 /** @defgroup RCC_System_Clock_Type System Clock Type 164 * @{ 165 */ 166 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 167 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 168 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 169 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ 170 171 /** 172 * @} 173 */ 174 175 /** @defgroup RCC_System_Clock_Source System Clock Source 176 * @{ 177 */ 178 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ 179 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ 180 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ 181 182 /** 183 * @} 184 */ 185 186 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 187 * @{ 188 */ 189 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 190 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 191 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 192 193 /** 194 * @} 195 */ 196 197 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 198 * @{ 199 */ 200 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 201 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 202 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 203 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 204 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 205 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 206 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 207 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 208 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 209 210 /** 211 * @} 212 */ 213 214 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 215 * @{ 216 */ 217 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 218 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 219 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 220 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 221 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 222 223 /** 224 * @} 225 */ 226 227 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 228 * @{ 229 */ 230 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ 231 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ 232 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ 233 #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ 234 /** 235 * @} 236 */ 237 238 /** @defgroup RCC_MCO_Index MCO Index 239 * @{ 240 */ 241 #define RCC_MCO1 0x00000000U 242 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 243 244 /** 245 * @} 246 */ 247 248 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler 249 * @{ 250 */ 251 #define RCC_MCODIV_1 0x00000000U 252 253 /** 254 * @} 255 */ 256 257 /** @defgroup RCC_Interrupt Interrupts 258 * @{ 259 */ 260 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ 261 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ 262 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ 263 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ 264 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ 265 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ 266 /** 267 * @} 268 */ 269 270 /** @defgroup RCC_Flag Flags 271 * Elements values convention: XXXYYYYYb 272 * - YYYYY : Flag position in the register 273 * - XXX : Register index 274 * - 001: CR register 275 * - 010: BDCR register 276 * - 011: CSR register 277 * @{ 278 */ 279 /* Flags in the CR register */ 280 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ 281 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ 282 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ 283 284 /* Flags in the CSR register */ 285 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ 286 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ 287 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ 288 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ 289 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ 290 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ 291 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ 292 293 /* Flags in the BDCR register */ 294 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ 295 296 /** 297 * @} 298 */ 299 300 /** 301 * @} 302 */ 303 304 /* Exported macro ------------------------------------------------------------*/ 305 306 /** @defgroup RCC_Exported_Macros RCC Exported Macros 307 * @{ 308 */ 309 310 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable 311 * @brief Enable or disable the AHB1 peripheral clock. 312 * @note After reset, the peripheral clock (used for registers read/write access) 313 * is disabled and the application software has to enable this clock before 314 * using it. 315 * @{ 316 */ 317 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 318 __IO uint32_t tmpreg; \ 319 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 320 /* Delay after an RCC peripheral clock enabling */\ 321 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ 322 UNUSED(tmpreg); \ 323 } while(0U) 324 325 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ 326 __IO uint32_t tmpreg; \ 327 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 328 /* Delay after an RCC peripheral clock enabling */\ 329 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ 330 UNUSED(tmpreg); \ 331 } while(0U) 332 333 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ 334 __IO uint32_t tmpreg; \ 335 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 336 /* Delay after an RCC peripheral clock enabling */\ 337 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ 338 UNUSED(tmpreg); \ 339 } while(0U) 340 341 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 342 __IO uint32_t tmpreg; \ 343 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 344 /* Delay after an RCC peripheral clock enabling */\ 345 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ 346 UNUSED(tmpreg); \ 347 } while(0U) 348 349 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) 350 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) 351 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) 352 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) 353 354 /** 355 * @} 356 */ 357 358 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status 359 * @brief Get the enable or disable status of the AHB peripheral clock. 360 * @note After reset, the peripheral clock (used for registers read/write access) 361 * is disabled and the application software has to enable this clock before 362 * using it. 363 * @{ 364 */ 365 366 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) 367 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) 368 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) 369 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) 370 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) 371 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) 372 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) 373 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) 374 375 /** 376 * @} 377 */ 378 379 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable 380 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. 381 * @note After reset, the peripheral clock (used for registers read/write access) 382 * is disabled and the application software has to enable this clock before 383 * using it. 384 * @{ 385 */ 386 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 387 __IO uint32_t tmpreg; \ 388 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 389 /* Delay after an RCC peripheral clock enabling */\ 390 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ 391 UNUSED(tmpreg); \ 392 } while(0U) 393 394 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 395 __IO uint32_t tmpreg; \ 396 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 397 /* Delay after an RCC peripheral clock enabling */\ 398 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ 399 UNUSED(tmpreg); \ 400 } while(0U) 401 402 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 403 __IO uint32_t tmpreg; \ 404 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 405 /* Delay after an RCC peripheral clock enabling */\ 406 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ 407 UNUSED(tmpreg); \ 408 } while(0U) 409 410 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 411 __IO uint32_t tmpreg; \ 412 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 413 /* Delay after an RCC peripheral clock enabling */\ 414 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ 415 UNUSED(tmpreg); \ 416 } while(0U) 417 418 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 419 __IO uint32_t tmpreg; \ 420 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 421 /* Delay after an RCC peripheral clock enabling */\ 422 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ 423 UNUSED(tmpreg); \ 424 } while(0U) 425 426 #define __HAL_RCC_BKP_CLK_ENABLE() do { \ 427 __IO uint32_t tmpreg; \ 428 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ 429 /* Delay after an RCC peripheral clock enabling */\ 430 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ 431 UNUSED(tmpreg); \ 432 } while(0U) 433 434 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 435 __IO uint32_t tmpreg; \ 436 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 437 /* Delay after an RCC peripheral clock enabling */\ 438 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ 439 UNUSED(tmpreg); \ 440 } while(0U) 441 442 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) 443 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) 444 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) 445 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) 446 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) 447 448 #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) 449 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) 450 451 /** 452 * @} 453 */ 454 455 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status 456 * @brief Get the enable or disable status of the APB1 peripheral clock. 457 * @note After reset, the peripheral clock (used for registers read/write access) 458 * is disabled and the application software has to enable this clock before 459 * using it. 460 * @{ 461 */ 462 463 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 464 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 465 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 466 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 467 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) 468 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) 469 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) 470 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) 471 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) 472 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) 473 #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) 474 #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) 475 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) 476 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) 477 478 /** 479 * @} 480 */ 481 482 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable 483 * @brief Enable or disable the High Speed APB (APB2) peripheral clock. 484 * @note After reset, the peripheral clock (used for registers read/write access) 485 * is disabled and the application software has to enable this clock before 486 * using it. 487 * @{ 488 */ 489 #define __HAL_RCC_AFIO_CLK_ENABLE() do { \ 490 __IO uint32_t tmpreg; \ 491 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ 492 /* Delay after an RCC peripheral clock enabling */\ 493 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ 494 UNUSED(tmpreg); \ 495 } while(0U) 496 497 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 498 __IO uint32_t tmpreg; \ 499 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ 500 /* Delay after an RCC peripheral clock enabling */\ 501 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ 502 UNUSED(tmpreg); \ 503 } while(0U) 504 505 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 506 __IO uint32_t tmpreg; \ 507 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ 508 /* Delay after an RCC peripheral clock enabling */\ 509 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ 510 UNUSED(tmpreg); \ 511 } while(0U) 512 513 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 514 __IO uint32_t tmpreg; \ 515 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ 516 /* Delay after an RCC peripheral clock enabling */\ 517 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ 518 UNUSED(tmpreg); \ 519 } while(0U) 520 521 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 522 __IO uint32_t tmpreg; \ 523 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ 524 /* Delay after an RCC peripheral clock enabling */\ 525 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ 526 UNUSED(tmpreg); \ 527 } while(0U) 528 529 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ 530 __IO uint32_t tmpreg; \ 531 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 532 /* Delay after an RCC peripheral clock enabling */\ 533 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ 534 UNUSED(tmpreg); \ 535 } while(0U) 536 537 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 538 __IO uint32_t tmpreg; \ 539 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 540 /* Delay after an RCC peripheral clock enabling */\ 541 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ 542 UNUSED(tmpreg); \ 543 } while(0U) 544 545 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 546 __IO uint32_t tmpreg; \ 547 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 548 /* Delay after an RCC peripheral clock enabling */\ 549 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ 550 UNUSED(tmpreg); \ 551 } while(0U) 552 553 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 554 __IO uint32_t tmpreg; \ 555 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 556 /* Delay after an RCC peripheral clock enabling */\ 557 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ 558 UNUSED(tmpreg); \ 559 } while(0U) 560 561 #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) 562 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) 563 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) 564 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) 565 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) 566 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) 567 568 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) 569 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) 570 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) 571 572 /** 573 * @} 574 */ 575 576 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status 577 * @brief Get the enable or disable status of the APB2 peripheral clock. 578 * @note After reset, the peripheral clock (used for registers read/write access) 579 * is disabled and the application software has to enable this clock before 580 * using it. 581 * @{ 582 */ 583 584 #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) 585 #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) 586 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) 587 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) 588 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) 589 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) 590 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) 591 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) 592 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) 593 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) 594 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) 595 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) 596 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) 597 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) 598 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) 599 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) 600 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) 601 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) 602 603 /** 604 * @} 605 */ 606 607 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset 608 * @brief Force or release APB1 peripheral reset. 609 * @{ 610 */ 611 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) 612 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) 613 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 614 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) 615 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) 616 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) 617 618 #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) 619 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) 620 621 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) 622 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) 623 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) 624 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) 625 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) 626 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) 627 628 #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) 629 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) 630 631 /** 632 * @} 633 */ 634 635 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset 636 * @brief Force or release APB2 peripheral reset. 637 * @{ 638 */ 639 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) 640 #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) 641 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) 642 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) 643 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) 644 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) 645 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) 646 647 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) 648 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) 649 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) 650 651 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) 652 #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) 653 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) 654 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) 655 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) 656 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) 657 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) 658 659 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) 660 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) 661 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) 662 663 /** 664 * @} 665 */ 666 667 /** @defgroup RCC_HSI_Configuration HSI Configuration 668 * @{ 669 */ 670 671 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). 672 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 673 * @note HSI can not be stopped if it is used as system clock source. In this case, 674 * you have to select another source of the system clock then stop the HSI. 675 * @note After enabling the HSI, the application software should wait on HSIRDY 676 * flag to be set indicating that HSI clock is stable and can be used as 677 * system clock source. 678 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 679 * clock cycles. 680 */ 681 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) 682 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) 683 684 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 685 * @note The calibration is used to compensate for the variations in voltage 686 * and temperature that influence the frequency of the internal HSI RC. 687 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. 688 * (default is RCC_HSICALIBRATION_DEFAULT). 689 * This parameter must be a number between 0 and 0x1F. 690 */ 691 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ 692 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) 693 694 /** 695 * @} 696 */ 697 698 /** @defgroup RCC_LSI_Configuration LSI Configuration 699 * @{ 700 */ 701 702 /** @brief Macro to enable the Internal Low Speed oscillator (LSI). 703 * @note After enabling the LSI, the application software should wait on 704 * LSIRDY flag to be set indicating that LSI clock is stable and can 705 * be used to clock the IWDG and/or the RTC. 706 */ 707 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) 708 709 /** @brief Macro to disable the Internal Low Speed oscillator (LSI). 710 * @note LSI can not be disabled if the IWDG is running. 711 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 712 * clock cycles. 713 */ 714 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) 715 716 /** 717 * @} 718 */ 719 720 /** @defgroup RCC_HSE_Configuration HSE Configuration 721 * @{ 722 */ 723 724 /** 725 * @brief Macro to configure the External High Speed oscillator (HSE). 726 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 727 * supported by this macro. User should request a transition to HSE Off 728 * first and then HSE On or HSE Bypass. 729 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 730 * software should wait on HSERDY flag to be set indicating that HSE clock 731 * is stable and can be used to clock the PLL and/or system clock. 732 * @note HSE state can not be changed if it is used directly or through the 733 * PLL as system clock. In this case, you have to select another source 734 * of the system clock then change the HSE state (ex. disable it). 735 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 736 * @note This function reset the CSSON bit, so if the clock security system(CSS) 737 * was previously enabled you have to enable it again after calling this 738 * function. 739 * @param __STATE__ specifies the new state of the HSE. 740 * This parameter can be one of the following values: 741 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after 742 * 6 HSE oscillator clock cycles. 743 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator 744 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock 745 */ 746 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 747 do{ \ 748 if ((__STATE__) == RCC_HSE_ON) \ 749 { \ 750 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 751 } \ 752 else if ((__STATE__) == RCC_HSE_OFF) \ 753 { \ 754 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 755 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 756 } \ 757 else if ((__STATE__) == RCC_HSE_BYPASS) \ 758 { \ 759 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 760 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 761 } \ 762 else \ 763 { \ 764 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 765 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 766 } \ 767 }while(0U) 768 769 /** 770 * @} 771 */ 772 773 /** @defgroup RCC_LSE_Configuration LSE Configuration 774 * @{ 775 */ 776 777 /** 778 * @brief Macro to configure the External Low Speed oscillator (LSE). 779 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. 780 * @note As the LSE is in the Backup domain and write access is denied to 781 * this domain after reset, you have to enable write access using 782 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE 783 * (to be done once after reset). 784 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 785 * software should wait on LSERDY flag to be set indicating that LSE clock 786 * is stable and can be used to clock the RTC. 787 * @param __STATE__ specifies the new state of the LSE. 788 * This parameter can be one of the following values: 789 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after 790 * 6 LSE oscillator clock cycles. 791 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. 792 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 793 */ 794 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 795 do{ \ 796 if ((__STATE__) == RCC_LSE_ON) \ 797 { \ 798 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 799 } \ 800 else if ((__STATE__) == RCC_LSE_OFF) \ 801 { \ 802 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 803 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 804 } \ 805 else if ((__STATE__) == RCC_LSE_BYPASS) \ 806 { \ 807 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 808 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 809 } \ 810 else \ 811 { \ 812 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 813 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 814 } \ 815 }while(0U) 816 817 /** 818 * @} 819 */ 820 821 /** @defgroup RCC_PLL_Configuration PLL Configuration 822 * @{ 823 */ 824 825 /** @brief Macro to enable the main PLL. 826 * @note After enabling the main PLL, the application software should wait on 827 * PLLRDY flag to be set indicating that PLL clock is stable and can 828 * be used as system clock source. 829 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 830 */ 831 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) 832 833 /** @brief Macro to disable the main PLL. 834 * @note The main PLL can not be disabled if it is used as system clock source 835 */ 836 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) 837 838 /** @brief Macro to configure the main PLL clock source and multiplication factors. 839 * @note This function must be used only when the main PLL is disabled. 840 * 841 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. 842 * This parameter can be one of the following values: 843 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry 844 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 845 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock 846 * This parameter can be one of the following values: 847 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 848 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 849 @if STM32F105xC 850 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 851 @elseif STM32F107xC 852 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 853 @else 854 * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 855 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 856 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 857 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 858 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 859 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 860 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 861 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 862 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 863 @endif 864 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 865 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 866 * 867 */ 868 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ 869 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) 870 871 /** @brief Get oscillator clock selected as PLL input clock 872 * @retval The clock source used for PLL entry. The returned value can be one 873 * of the following: 874 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock 875 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock 876 */ 877 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) 878 879 /** 880 * @} 881 */ 882 883 /** @defgroup RCC_Get_Clock_source Get Clock source 884 * @{ 885 */ 886 887 /** 888 * @brief Macro to configure the system clock source. 889 * @param __SYSCLKSOURCE__ specifies the system clock source. 890 * This parameter can be one of the following values: 891 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 892 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 893 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. 894 */ 895 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 896 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 897 898 /** @brief Macro to get the clock source used as system clock. 899 * @retval The clock source used as system clock. The returned value can be one 900 * of the following: 901 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock 902 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock 903 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock 904 */ 905 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) 906 907 /** 908 * @} 909 */ 910 911 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config 912 * @{ 913 */ 914 915 #if defined(RCC_CFGR_MCO_3) 916 /** @brief Macro to configure the MCO clock. 917 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 918 * This parameter can be one of the following values: 919 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 920 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock 921 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 922 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 923 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock 924 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock 925 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock 926 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock 927 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock 928 * @param __MCODIV__ specifies the MCO clock prescaler. 929 * This parameter can be one of the following values: 930 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 931 */ 932 #else 933 /** @brief Macro to configure the MCO clock. 934 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 935 * This parameter can be one of the following values: 936 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock 937 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock 938 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock 939 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock 940 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock 941 * @param __MCODIV__ specifies the MCO clock prescaler. 942 * This parameter can be one of the following values: 943 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source 944 */ 945 #endif 946 947 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 948 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) 949 950 /** 951 * @} 952 */ 953 954 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 955 * @{ 956 */ 957 958 /** @brief Macro to configure the RTC clock (RTCCLK). 959 * @note As the RTC clock configuration bits are in the Backup domain and write 960 * access is denied to this domain after reset, you have to enable write 961 * access using the Power Backup Access macro before to configure 962 * the RTC clock source (to be done once after reset). 963 * @note Once the RTC clock is configured it can't be changed unless the 964 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by 965 * a Power On Reset (POR). 966 * 967 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 968 * This parameter can be one of the following values: 969 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 970 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 971 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 972 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock 973 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 974 * work in STOP and STANDBY modes, and can be used as wakeup source. 975 * However, when the HSE clock is used as RTC clock source, the RTC 976 * cannot be used in STOP and STANDBY modes. 977 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 978 * RTC clock source). 979 */ 980 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 981 982 /** @brief Macro to get the RTC clock source. 983 * @retval The clock source can be one of the following values: 984 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock 985 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock 986 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock 987 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock 988 */ 989 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) 990 991 /** @brief Macro to enable the the RTC clock. 992 * @note These macros must be used only after the RTC clock source was selected. 993 */ 994 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) 995 996 /** @brief Macro to disable the the RTC clock. 997 * @note These macros must be used only after the RTC clock source was selected. 998 */ 999 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) 1000 1001 /** @brief Macro to force the Backup domain reset. 1002 * @note This function resets the RTC peripheral (including the backup registers) 1003 * and the RTC clock source selection in RCC_BDCR register. 1004 */ 1005 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) 1006 1007 /** @brief Macros to release the Backup domain reset. 1008 */ 1009 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) 1010 1011 /** 1012 * @} 1013 */ 1014 1015 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1016 * @brief macros to manage the specified RCC Flags and interrupts. 1017 * @{ 1018 */ 1019 1020 /** @brief Enable RCC interrupt. 1021 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1022 * This parameter can be any combination of the following values: 1023 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1024 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1025 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1026 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1027 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1028 @if STM32F105xx 1029 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1030 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1031 @elsif STM32F107xx 1032 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1033 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1034 @endif 1035 */ 1036 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) 1037 1038 /** @brief Disable RCC interrupt. 1039 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1040 * This parameter can be any combination of the following values: 1041 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1042 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1043 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1044 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1045 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt 1046 @if STM32F105xx 1047 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1048 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1049 @elsif STM32F107xx 1050 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1051 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1052 @endif 1053 */ 1054 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) 1055 1056 /** @brief Clear the RCC's interrupt pending bits. 1057 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1058 * This parameter can be any combination of the following values: 1059 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1060 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1061 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1062 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1063 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1064 @if STM32F105xx 1065 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1066 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1067 @elsif STM32F107xx 1068 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1069 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1070 @endif 1071 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1072 */ 1073 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) 1074 1075 /** @brief Check the RCC's interrupt has occurred or not. 1076 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1077 * This parameter can be one of the following values: 1078 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. 1079 * @arg @ref RCC_IT_LSERDY LSE ready interrupt. 1080 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. 1081 * @arg @ref RCC_IT_HSERDY HSE ready interrupt. 1082 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. 1083 @if STM32F105xx 1084 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1085 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1086 @elsif STM32F107xx 1087 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. 1088 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. 1089 @endif 1090 * @arg @ref RCC_IT_CSS Clock Security System interrupt 1091 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1092 */ 1093 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) 1094 1095 /** @brief Set RMVF bit to clear the reset flags. 1096 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, 1097 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST 1098 */ 1099 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) 1100 1101 /** @brief Check RCC flag is set or not. 1102 * @param __FLAG__ specifies the flag to check. 1103 * This parameter can be one of the following values: 1104 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. 1105 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. 1106 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. 1107 @if STM32F105xx 1108 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. 1109 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. 1110 @elsif STM32F107xx 1111 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. 1112 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. 1113 @endif 1114 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. 1115 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. 1116 * @arg @ref RCC_FLAG_PINRST Pin reset. 1117 * @arg @ref RCC_FLAG_PORRST POR/PDR reset. 1118 * @arg @ref RCC_FLAG_SFTRST Software reset. 1119 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. 1120 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. 1121 * @arg @ref RCC_FLAG_LPWRRST Low Power reset. 1122 * @retval The new state of __FLAG__ (TRUE or FALSE). 1123 */ 1124 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ 1125 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ 1126 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) 1127 1128 /** 1129 * @} 1130 */ 1131 1132 /** 1133 * @} 1134 */ 1135 1136 /* Include RCC HAL Extension module */ 1137 #include "stm32f1xx_hal_rcc_ex.h" 1138 1139 /* Exported functions --------------------------------------------------------*/ 1140 /** @addtogroup RCC_Exported_Functions 1141 * @{ 1142 */ 1143 1144 /** @addtogroup RCC_Exported_Functions_Group1 1145 * @{ 1146 */ 1147 1148 /* Initialization and de-initialization functions ******************************/ 1149 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1150 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1151 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, 1152 uint32_t FLatency); 1153 1154 /** 1155 * @} 1156 */ 1157 1158 /** @addtogroup RCC_Exported_Functions_Group2 1159 * @{ 1160 */ 1161 1162 /* Peripheral Control functions ************************************************/ 1163 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, 1164 uint32_t RCC_MCODiv); 1165 void HAL_RCC_EnableCSS(void); 1166 void HAL_RCC_DisableCSS(void); 1167 uint32_t HAL_RCC_GetSysClockFreq(void); 1168 uint32_t HAL_RCC_GetHCLKFreq(void); 1169 uint32_t HAL_RCC_GetPCLK1Freq(void); 1170 uint32_t HAL_RCC_GetPCLK2Freq(void); 1171 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1172 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, 1173 uint32_t *pFLatency); 1174 1175 /* CSS NMI IRQ handler */ 1176 void HAL_RCC_NMI_IRQHandler(void); 1177 1178 /* User Callbacks in non blocking mode (IT mode) */ 1179 void HAL_RCC_CSSCallback(void); 1180 1181 /** 1182 * @} 1183 */ 1184 1185 /** 1186 * @} 1187 */ 1188 1189 /** @addtogroup RCC_Private_Constants 1190 * @{ 1191 */ 1192 1193 /** @defgroup RCC_Timeout RCC Timeout 1194 * @{ 1195 */ 1196 1197 /* Disable Backup domain write protection state change timeout */ 1198 #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ 1199 /* LSE state change timeout */ 1200 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 1201 #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ 1202 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT 1203 #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 1204 #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 1205 #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ 1206 1207 /** 1208 * @} 1209 */ 1210 1211 /** @defgroup RCC_Register_Offset Register offsets 1212 * @{ 1213 */ 1214 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 1215 #define RCC_CR_OFFSET 0x00U 1216 #define RCC_CFGR_OFFSET 0x04U 1217 #define RCC_CIR_OFFSET 0x08U 1218 #define RCC_BDCR_OFFSET 0x20U 1219 #define RCC_CSR_OFFSET 0x24U 1220 1221 /** 1222 * @} 1223 */ 1224 1225 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion 1226 * @brief RCC registers bit address in the alias region 1227 * @{ 1228 */ 1229 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) 1230 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) 1231 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) 1232 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) 1233 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) 1234 1235 /* --- CR Register ---*/ 1236 /* Alias word address of HSION bit */ 1237 #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos 1238 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) 1239 /* Alias word address of HSEON bit */ 1240 #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos 1241 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) 1242 /* Alias word address of CSSON bit */ 1243 #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos 1244 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) 1245 /* Alias word address of PLLON bit */ 1246 #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos 1247 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) 1248 1249 /* --- CSR Register ---*/ 1250 /* Alias word address of LSION bit */ 1251 #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos 1252 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) 1253 1254 /* Alias word address of RMVF bit */ 1255 #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos 1256 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) 1257 1258 /* --- BDCR Registers ---*/ 1259 /* Alias word address of LSEON bit */ 1260 #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos 1261 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) 1262 1263 /* Alias word address of LSEON bit */ 1264 #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos 1265 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) 1266 1267 /* Alias word address of RTCEN bit */ 1268 #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos 1269 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) 1270 1271 /* Alias word address of BDRST bit */ 1272 #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos 1273 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) 1274 1275 /** 1276 * @} 1277 */ 1278 1279 /* CR register byte 2 (Bits[23:16]) base address */ 1280 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) 1281 1282 /* CIR register byte 1 (Bits[15:8]) base address */ 1283 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) 1284 1285 /* CIR register byte 2 (Bits[23:16]) base address */ 1286 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) 1287 1288 /* Defines used for Flags */ 1289 #define CR_REG_INDEX ((uint8_t)1) 1290 #define BDCR_REG_INDEX ((uint8_t)2) 1291 #define CSR_REG_INDEX ((uint8_t)3) 1292 1293 #define RCC_FLAG_MASK ((uint8_t)0x1F) 1294 1295 /** 1296 * @} 1297 */ 1298 1299 /** @addtogroup RCC_Private_Macros 1300 * @{ 1301 */ 1302 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy 1303 * @{ 1304 */ 1305 #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 1306 #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 1307 #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 1308 #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 1309 /** 1310 * @} 1311 */ 1312 1313 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ 1314 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 1315 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 1316 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 1317 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 1318 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 1319 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 1320 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 1321 ((__HSE__) == RCC_HSE_BYPASS)) 1322 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 1323 ((__LSE__) == RCC_LSE_BYPASS)) 1324 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 1325 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) 1326 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 1327 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ 1328 ((__PLL__) == RCC_PLL_ON)) 1329 1330 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ 1331 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ 1332 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ 1333 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) 1334 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 1335 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 1336 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 1337 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ 1338 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ 1339 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) 1340 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 1341 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 1342 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 1343 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 1344 ((__HCLK__) == RCC_SYSCLK_DIV512)) 1345 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 1346 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 1347 ((__PCLK__) == RCC_HCLK_DIV16)) 1348 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) 1349 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) 1350 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 1351 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 1352 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 1353 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) 1354 1355 /** 1356 * @} 1357 */ 1358 1359 /** 1360 * @} 1361 */ 1362 1363 /** 1364 * @} 1365 */ 1366 1367 #ifdef __cplusplus 1368 } 1369 #endif 1370 1371 #endif /* __STM32F1xx_HAL_RCC_H */ 1372