Drivers/CMSIS/Include/core_sc000.h (45502B)
1 /**************************************************************************//** 2 * @file core_sc000.h 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File 4 * @version V5.0.5 5 * @date 28. May 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_SC000_H_GENERIC 32 #define __CORE_SC000_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup SC000 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS SC000 definitions */ 65 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ 68 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_SC (000U) /*!< Cortex secure core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 This core does not support an FPU at all 74 */ 75 #define __FPU_USED 0U 76 77 #if defined ( __CC_ARM ) 78 #if defined __TARGET_FPU_VFP 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 80 #endif 81 82 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 83 #if defined __ARM_PCS_VFP 84 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 85 #endif 86 87 #elif defined ( __GNUC__ ) 88 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 90 #endif 91 92 #elif defined ( __ICCARM__ ) 93 #if defined __ARMVFP__ 94 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 95 #endif 96 97 #elif defined ( __TI_ARM__ ) 98 #if defined __TI_VFP_SUPPORT__ 99 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 100 #endif 101 102 #elif defined ( __TASKING__ ) 103 #if defined __FPU_VFP__ 104 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 105 #endif 106 107 #elif defined ( __CSMC__ ) 108 #if ( __CSMC__ & 0x400U) 109 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 110 #endif 111 112 #endif 113 114 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 115 116 #ifdef __cplusplus 117 } 118 #endif 119 120 #endif /* __CORE_SC000_H_GENERIC */ 121 122 #ifndef __CMSIS_GENERIC 123 124 #ifndef __CORE_SC000_H_DEPENDANT 125 #define __CORE_SC000_H_DEPENDANT 126 127 #ifdef __cplusplus 128 extern "C" { 129 #endif 130 131 /* check device defines and use defaults */ 132 #if defined __CHECK_DEVICE_DEFINES 133 #ifndef __SC000_REV 134 #define __SC000_REV 0x0000U 135 #warning "__SC000_REV not defined in device header file; using default!" 136 #endif 137 138 #ifndef __MPU_PRESENT 139 #define __MPU_PRESENT 0U 140 #warning "__MPU_PRESENT not defined in device header file; using default!" 141 #endif 142 143 #ifndef __NVIC_PRIO_BITS 144 #define __NVIC_PRIO_BITS 2U 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 146 #endif 147 148 #ifndef __Vendor_SysTickConfig 149 #define __Vendor_SysTickConfig 0U 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 151 #endif 152 #endif 153 154 /* IO definitions (access restrictions to peripheral registers) */ 155 /** 156 \defgroup CMSIS_glob_defs CMSIS Global Defines 157 158 <strong>IO Type Qualifiers</strong> are used 159 \li to specify the access to peripheral variables. 160 \li for automatic generation of peripheral register debug information. 161 */ 162 #ifdef __cplusplus 163 #define __I volatile /*!< Defines 'read only' permissions */ 164 #else 165 #define __I volatile const /*!< Defines 'read only' permissions */ 166 #endif 167 #define __O volatile /*!< Defines 'write only' permissions */ 168 #define __IO volatile /*!< Defines 'read / write' permissions */ 169 170 /* following defines should be used for structure members */ 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 172 #define __OM volatile /*! Defines 'write only' structure member permissions */ 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 174 175 /*@} end of group SC000 */ 176 177 /******************************************************************************* 178 * Register Abstraction 179 Core Register contain: 180 - Core Register 181 - Core NVIC Register 182 - Core SCB Register 183 - Core SysTick Register 184 - Core MPU Register 185 ******************************************************************************/ 186 /** 187 \defgroup CMSIS_core_register Defines and Type Definitions 188 \brief Type definitions and defines for Cortex-M processor based devices. 189 */ 190 191 /** 192 \ingroup CMSIS_core_register 193 \defgroup CMSIS_CORE Status and Control Registers 194 \brief Core Register type definitions. 195 @{ 196 */ 197 198 /** 199 \brief Union type to access the Application Program Status Register (APSR). 200 */ 201 typedef union { 202 struct { 203 uint32_t _reserved0 :28; /*!< bit: 0..27 Reserved */ 204 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 205 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 206 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 207 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 208 } b; /*!< Structure used for bit access */ 209 uint32_t w; /*!< Type used for word access */ 210 } APSR_Type; 211 212 /* APSR Register Definitions */ 213 #define APSR_N_Pos 31U /*!< APSR: N Position */ 214 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 215 216 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 217 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 218 219 #define APSR_C_Pos 29U /*!< APSR: C Position */ 220 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 221 222 #define APSR_V_Pos 28U /*!< APSR: V Position */ 223 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 224 225 /** 226 \brief Union type to access the Interrupt Program Status Register (IPSR). 227 */ 228 typedef union { 229 struct { 230 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 231 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 232 } b; /*!< Structure used for bit access */ 233 uint32_t w; /*!< Type used for word access */ 234 } IPSR_Type; 235 236 /* IPSR Register Definitions */ 237 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 238 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 239 240 /** 241 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 242 */ 243 typedef union { 244 struct { 245 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 246 uint32_t _reserved0 :15; /*!< bit: 9..23 Reserved */ 247 uint32_t T :1; /*!< bit: 24 Thumb bit (read 0) */ 248 uint32_t _reserved1 :3; /*!< bit: 25..27 Reserved */ 249 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 250 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 251 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 252 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 253 } b; /*!< Structure used for bit access */ 254 uint32_t w; /*!< Type used for word access */ 255 } xPSR_Type; 256 257 /* xPSR Register Definitions */ 258 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 259 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 260 261 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 262 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 263 264 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 265 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 266 267 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 268 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 269 270 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 271 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 272 273 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 274 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 275 276 /** 277 \brief Union type to access the Control Registers (CONTROL). 278 */ 279 typedef union { 280 struct { 281 uint32_t _reserved0 :1; /*!< bit: 0 Reserved */ 282 uint32_t SPSEL :1; /*!< bit: 1 Stack to be used */ 283 uint32_t _reserved1 :30; /*!< bit: 2..31 Reserved */ 284 } b; /*!< Structure used for bit access */ 285 uint32_t w; /*!< Type used for word access */ 286 } CONTROL_Type; 287 288 /* CONTROL Register Definitions */ 289 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 290 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 291 292 /*@} end of group CMSIS_CORE */ 293 294 /** 295 \ingroup CMSIS_core_register 296 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 297 \brief Type definitions for the NVIC Registers 298 @{ 299 */ 300 301 /** 302 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 303 */ 304 typedef struct { 305 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 306 uint32_t RESERVED0[31U]; 307 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 308 uint32_t RSERVED1[31U]; 309 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 310 uint32_t RESERVED2[31U]; 311 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 312 uint32_t RESERVED3[31U]; 313 uint32_t RESERVED4[64U]; 314 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 315 } NVIC_Type; 316 317 /*@} end of group CMSIS_NVIC */ 318 319 /** 320 \ingroup CMSIS_core_register 321 \defgroup CMSIS_SCB System Control Block (SCB) 322 \brief Type definitions for the System Control Block Registers 323 @{ 324 */ 325 326 /** 327 \brief Structure type to access the System Control Block (SCB). 328 */ 329 typedef struct { 330 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 331 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 332 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 333 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 334 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 335 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 336 uint32_t RESERVED0[1U]; 337 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 338 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 339 uint32_t RESERVED1[154U]; 340 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ 341 } SCB_Type; 342 343 /* SCB CPUID Register Definitions */ 344 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 345 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 346 347 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 348 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 349 350 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 351 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 352 353 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 354 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 355 356 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 357 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 358 359 /* SCB Interrupt Control State Register Definitions */ 360 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 361 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 362 363 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 364 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 365 366 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 367 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 368 369 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 370 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 371 372 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 373 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 374 375 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 376 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 377 378 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 379 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 380 381 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 382 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 383 384 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 385 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 386 387 /* SCB Interrupt Control State Register Definitions */ 388 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 389 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 390 391 /* SCB Application Interrupt and Reset Control Register Definitions */ 392 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 393 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 394 395 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 396 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 397 398 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 399 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 400 401 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 402 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 403 404 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 405 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 406 407 /* SCB System Control Register Definitions */ 408 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 409 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 410 411 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 412 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 413 414 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 415 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 416 417 /* SCB Configuration Control Register Definitions */ 418 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 419 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 420 421 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 422 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 423 424 /* SCB System Handler Control and State Register Definitions */ 425 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 426 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 427 428 /*@} end of group CMSIS_SCB */ 429 430 /** 431 \ingroup CMSIS_core_register 432 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 433 \brief Type definitions for the System Control and ID Register not in the SCB 434 @{ 435 */ 436 437 /** 438 \brief Structure type to access the System Control and ID Register not in the SCB. 439 */ 440 typedef struct { 441 uint32_t RESERVED0[2U]; 442 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 443 } SCnSCB_Type; 444 445 /* Auxiliary Control Register Definitions */ 446 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 447 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 448 449 /*@} end of group CMSIS_SCnotSCB */ 450 451 /** 452 \ingroup CMSIS_core_register 453 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 454 \brief Type definitions for the System Timer Registers. 455 @{ 456 */ 457 458 /** 459 \brief Structure type to access the System Timer (SysTick). 460 */ 461 typedef struct { 462 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 463 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 464 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 465 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 466 } SysTick_Type; 467 468 /* SysTick Control / Status Register Definitions */ 469 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 470 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 471 472 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 473 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 474 475 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 476 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 477 478 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 479 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 480 481 /* SysTick Reload Register Definitions */ 482 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 483 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 484 485 /* SysTick Current Register Definitions */ 486 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 487 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 488 489 /* SysTick Calibration Register Definitions */ 490 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 491 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 492 493 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 494 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 495 496 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 497 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 498 499 /*@} end of group CMSIS_SysTick */ 500 501 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 502 /** 503 \ingroup CMSIS_core_register 504 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 505 \brief Type definitions for the Memory Protection Unit (MPU) 506 @{ 507 */ 508 509 /** 510 \brief Structure type to access the Memory Protection Unit (MPU). 511 */ 512 typedef struct 513 { 514 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 515 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 516 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 517 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 518 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 519 }MPU_Type; 520 521 /* MPU Type Register Definitions */ 522 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 523 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 524 525 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 526 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 527 528 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 529 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 530 531 /* MPU Control Register Definitions */ 532 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 533 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 534 535 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 536 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 537 538 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 539 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 540 541 /* MPU Region Number Register Definitions */ 542 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 543 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 544 545 /* MPU Region Base Address Register Definitions */ 546 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ 547 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 548 549 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 550 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 551 552 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 553 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 554 555 /* MPU Region Attribute and Size Register Definitions */ 556 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 557 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 558 559 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 560 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 561 562 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 563 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 564 565 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 566 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 567 568 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 569 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 570 571 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 572 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 573 574 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 575 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 576 577 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 578 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 579 580 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 581 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 582 583 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 584 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 585 586 /*@} end of group CMSIS_MPU */ 587 #endif 588 589 /** 590 \ingroup CMSIS_core_register 591 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 592 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 593 Therefore they are not covered by the SC000 header file. 594 @{ 595 */ 596 /*@} end of group CMSIS_CoreDebug */ 597 598 /** 599 \ingroup CMSIS_core_register 600 \defgroup CMSIS_core_bitfield Core register bit field macros 601 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 602 @{ 603 */ 604 605 /** 606 \brief Mask and shift a bit field value for use in a register bit range. 607 \param[in] field Name of the register bit field. 608 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 609 \return Masked and shifted value. 610 */ 611 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 612 613 /** 614 \brief Mask and shift a register value to extract a bit filed value. 615 \param[in] field Name of the register bit field. 616 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 617 \return Masked and shifted bit field value. 618 */ 619 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 620 621 /*@} end of group CMSIS_core_bitfield */ 622 623 /** 624 \ingroup CMSIS_core_register 625 \defgroup CMSIS_core_base Core Definitions 626 \brief Definitions for base addresses, unions, and structures. 627 @{ 628 */ 629 630 /* Memory mapping of Core Hardware */ 631 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 632 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 633 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 634 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 635 636 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 637 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 638 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 639 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 640 641 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 642 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 643 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 644 #endif 645 646 /*@} */ 647 648 /******************************************************************************* 649 * Hardware Abstraction Layer 650 Core Function Interface contains: 651 - Core NVIC Functions 652 - Core SysTick Functions 653 - Core Register Access Functions 654 ******************************************************************************/ 655 /** 656 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 657 */ 658 659 /* ########################## NVIC functions #################################### */ 660 /** 661 \ingroup CMSIS_Core_FunctionInterface 662 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 663 \brief Functions that manage interrupts and exceptions via the NVIC. 664 @{ 665 */ 666 667 #ifdef CMSIS_NVIC_VIRTUAL 668 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 669 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 670 #endif 671 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 672 #else 673 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ 674 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ 675 #define NVIC_EnableIRQ __NVIC_EnableIRQ 676 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 677 #define NVIC_DisableIRQ __NVIC_DisableIRQ 678 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 679 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 680 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 681 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ 682 #define NVIC_SetPriority __NVIC_SetPriority 683 #define NVIC_GetPriority __NVIC_GetPriority 684 #define NVIC_SystemReset __NVIC_SystemReset 685 #endif /* CMSIS_NVIC_VIRTUAL */ 686 687 #ifdef CMSIS_VECTAB_VIRTUAL 688 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 689 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 690 #endif 691 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 692 #else 693 #define NVIC_SetVector __NVIC_SetVector 694 #define NVIC_GetVector __NVIC_GetVector 695 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 696 697 #define NVIC_USER_IRQ_OFFSET 16 698 699 /* The following EXC_RETURN values are saved the LR on exception entry */ 700 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 701 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 702 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 703 704 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 705 /* The following MACROS handle generation of the register offset and byte masks */ 706 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 707 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 708 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 709 710 /** 711 \brief Enable Interrupt 712 \details Enables a device specific interrupt in the NVIC interrupt controller. 713 \param [in] IRQn Device specific interrupt number. 714 \note IRQn must not be negative. 715 */ 716 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 717 { 718 if ((int32_t) (IRQn) >= 0) { 719 NVIC->ISER[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 720 } 721 } 722 723 /** 724 \brief Get Interrupt Enable status 725 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 726 \param [in] IRQn Device specific interrupt number. 727 \return 0 Interrupt is not enabled. 728 \return 1 Interrupt is enabled. 729 \note IRQn must not be negative. 730 */ 731 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 732 { 733 if ((int32_t) (IRQn) >= 0) { 734 return ((uint32_t) ( 735 ((NVIC->ISER[0U] & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 736 1UL : 0UL)); 737 } else { 738 return (0U); 739 } 740 } 741 742 /** 743 \brief Disable Interrupt 744 \details Disables a device specific interrupt in the NVIC interrupt controller. 745 \param [in] IRQn Device specific interrupt number. 746 \note IRQn must not be negative. 747 */ 748 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 749 { 750 if ((int32_t) (IRQn) >= 0) { 751 NVIC->ICER[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 752 __DSB(); 753 __ISB(); 754 } 755 } 756 757 /** 758 \brief Get Pending Interrupt 759 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 760 \param [in] IRQn Device specific interrupt number. 761 \return 0 Interrupt status is not pending. 762 \return 1 Interrupt status is pending. 763 \note IRQn must not be negative. 764 */ 765 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 766 { 767 if ((int32_t) (IRQn) >= 0) { 768 return ((uint32_t) ( 769 ((NVIC->ISPR[0U] & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 770 1UL : 0UL)); 771 } else { 772 return (0U); 773 } 774 } 775 776 /** 777 \brief Set Pending Interrupt 778 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 779 \param [in] IRQn Device specific interrupt number. 780 \note IRQn must not be negative. 781 */ 782 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 783 { 784 if ((int32_t) (IRQn) >= 0) { 785 NVIC->ISPR[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 786 } 787 } 788 789 /** 790 \brief Clear Pending Interrupt 791 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 792 \param [in] IRQn Device specific interrupt number. 793 \note IRQn must not be negative. 794 */ 795 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 796 { 797 if ((int32_t) (IRQn) >= 0) { 798 NVIC->ICPR[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 799 } 800 } 801 802 /** 803 \brief Set Interrupt Priority 804 \details Sets the priority of a device specific interrupt or a processor exception. 805 The interrupt number can be positive to specify a device specific interrupt, 806 or negative to specify a processor exception. 807 \param [in] IRQn Interrupt number. 808 \param [in] priority Priority to set. 809 \note The priority cannot be set for every processor exception. 810 */ 811 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 812 { 813 if ((int32_t) (IRQn) >= 0) { 814 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t) (NVIC->IP[_IP_IDX(IRQn)] 815 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 816 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 817 << _BIT_SHIFT(IRQn))); 818 } else { 819 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t) (SCB->SHP[_SHP_IDX(IRQn)] 820 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 821 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 822 << _BIT_SHIFT(IRQn))); 823 } 824 } 825 826 /** 827 \brief Get Interrupt Priority 828 \details Reads the priority of a device specific interrupt or a processor exception. 829 The interrupt number can be positive to specify a device specific interrupt, 830 or negative to specify a processor exception. 831 \param [in] IRQn Interrupt number. 832 \return Interrupt Priority. 833 Value is aligned automatically to the implemented priority bits of the microcontroller. 834 */ 835 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 836 { 837 838 if ((int32_t) (IRQn) >= 0) { 839 return ((uint32_t) (((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 840 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 841 } else { 842 return ((uint32_t) (((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 843 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 844 } 845 } 846 847 /** 848 \brief Set Interrupt Vector 849 \details Sets an interrupt vector in SRAM based interrupt vector table. 850 The interrupt number can be positive to specify a device specific interrupt, 851 or negative to specify a processor exception. 852 VTOR must been relocated to SRAM before. 853 \param [in] IRQn Interrupt number 854 \param [in] vector Address of interrupt handler function 855 */ 856 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 857 { 858 uint32_t *vectors = (uint32_t*) SCB->VTOR; 859 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 860 } 861 862 /** 863 \brief Get Interrupt Vector 864 \details Reads an interrupt vector from interrupt vector table. 865 The interrupt number can be positive to specify a device specific interrupt, 866 or negative to specify a processor exception. 867 \param [in] IRQn Interrupt number. 868 \return Address of interrupt handler function 869 */ 870 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 871 { 872 uint32_t *vectors = (uint32_t*) SCB->VTOR; 873 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 874 } 875 876 /** 877 \brief System Reset 878 \details Initiates a system reset request to reset the MCU. 879 */ 880 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 881 { 882 __DSB(); /* Ensure all outstanding memory accesses included 883 buffered write are completed before reset */ 884 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 885 SCB_AIRCR_SYSRESETREQ_Msk); 886 __DSB(); /* Ensure completion of memory access */ 887 888 for (;;) /* wait until reset */ 889 { 890 __NOP(); 891 } 892 } 893 894 /*@} end of CMSIS_Core_NVICFunctions */ 895 896 /* ########################## FPU functions #################################### */ 897 /** 898 \ingroup CMSIS_Core_FunctionInterface 899 \defgroup CMSIS_Core_FpuFunctions FPU Functions 900 \brief Function that provides FPU type. 901 @{ 902 */ 903 904 /** 905 \brief get FPU type 906 \details returns the FPU type 907 \returns 908 - \b 0: No FPU 909 - \b 1: Single precision FPU 910 - \b 2: Double + Single precision FPU 911 */ 912 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 913 { 914 return 0U; /* No FPU */ 915 } 916 917 /*@} end of CMSIS_Core_FpuFunctions */ 918 919 /* ################################## SysTick function ############################################ */ 920 /** 921 \ingroup CMSIS_Core_FunctionInterface 922 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 923 \brief Functions that configure the System. 924 @{ 925 */ 926 927 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 928 929 /** 930 \brief System Tick Configuration 931 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 932 Counter is in free running mode to generate periodic interrupts. 933 \param [in] ticks Number of ticks between two interrupts. 934 \return 0 Function succeeded. 935 \return 1 Function failed. 936 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 937 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 938 must contain a vendor-specific implementation of this function. 939 */ 940 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 941 { 942 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 943 { 944 return (1UL); /* Reload value impossible */ 945 } 946 947 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 948 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 949 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 950 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 951 SysTick_CTRL_TICKINT_Msk | 952 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 953 return (0UL); /* Function successful */ 954 } 955 956 #endif 957 958 /*@} end of CMSIS_Core_SysTickFunctions */ 959 960 #ifdef __cplusplus 961 } 962 #endif 963 964 #endif /* __CORE_SC000_H_DEPENDANT */ 965 966 #endif /* __CMSIS_GENERIC */