Drivers/CMSIS/Include/core_cm7.h (144983B)
1 /**************************************************************************//** 2 * @file core_cm7.h 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File 4 * @version V5.0.8 5 * @date 04. June 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_CM7_H_GENERIC 32 #define __CORE_CM7_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup Cortex_M7 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS CM7 definitions */ 65 #define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ 68 __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_M (7U) /*!< Cortex-M Core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 74 */ 75 #if defined ( __CC_ARM ) 76 #if defined __TARGET_FPU_VFP 77 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 78 #define __FPU_USED 1U 79 #else 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 81 #define __FPU_USED 0U 82 #endif 83 #else 84 #define __FPU_USED 0U 85 #endif 86 87 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 88 #if defined __ARM_PCS_VFP 89 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 90 #define __FPU_USED 1U 91 #else 92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 93 #define __FPU_USED 0U 94 #endif 95 #else 96 #define __FPU_USED 0U 97 #endif 98 99 #elif defined ( __GNUC__ ) 100 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 102 #define __FPU_USED 1U 103 #else 104 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 105 #define __FPU_USED 0U 106 #endif 107 #else 108 #define __FPU_USED 0U 109 #endif 110 111 #elif defined ( __ICCARM__ ) 112 #if defined __ARMVFP__ 113 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 114 #define __FPU_USED 1U 115 #else 116 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 117 #define __FPU_USED 0U 118 #endif 119 #else 120 #define __FPU_USED 0U 121 #endif 122 123 #elif defined ( __TI_ARM__ ) 124 #if defined __TI_VFP_SUPPORT__ 125 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 126 #define __FPU_USED 1U 127 #else 128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 129 #define __FPU_USED 0U 130 #endif 131 #else 132 #define __FPU_USED 0U 133 #endif 134 135 #elif defined ( __TASKING__ ) 136 #if defined __FPU_VFP__ 137 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 138 #define __FPU_USED 1U 139 #else 140 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 141 #define __FPU_USED 0U 142 #endif 143 #else 144 #define __FPU_USED 0U 145 #endif 146 147 #elif defined ( __CSMC__ ) 148 #if ( __CSMC__ & 0x400U) 149 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 150 #define __FPU_USED 1U 151 #else 152 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 153 #define __FPU_USED 0U 154 #endif 155 #else 156 #define __FPU_USED 0U 157 #endif 158 159 #endif 160 161 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 162 163 #ifdef __cplusplus 164 } 165 #endif 166 167 #endif /* __CORE_CM7_H_GENERIC */ 168 169 #ifndef __CMSIS_GENERIC 170 171 #ifndef __CORE_CM7_H_DEPENDANT 172 #define __CORE_CM7_H_DEPENDANT 173 174 #ifdef __cplusplus 175 extern "C" { 176 #endif 177 178 /* check device defines and use defaults */ 179 #if defined __CHECK_DEVICE_DEFINES 180 #ifndef __CM7_REV 181 #define __CM7_REV 0x0000U 182 #warning "__CM7_REV not defined in device header file; using default!" 183 #endif 184 185 #ifndef __FPU_PRESENT 186 #define __FPU_PRESENT 0U 187 #warning "__FPU_PRESENT not defined in device header file; using default!" 188 #endif 189 190 #ifndef __MPU_PRESENT 191 #define __MPU_PRESENT 0U 192 #warning "__MPU_PRESENT not defined in device header file; using default!" 193 #endif 194 195 #ifndef __ICACHE_PRESENT 196 #define __ICACHE_PRESENT 0U 197 #warning "__ICACHE_PRESENT not defined in device header file; using default!" 198 #endif 199 200 #ifndef __DCACHE_PRESENT 201 #define __DCACHE_PRESENT 0U 202 #warning "__DCACHE_PRESENT not defined in device header file; using default!" 203 #endif 204 205 #ifndef __DTCM_PRESENT 206 #define __DTCM_PRESENT 0U 207 #warning "__DTCM_PRESENT not defined in device header file; using default!" 208 #endif 209 210 #ifndef __NVIC_PRIO_BITS 211 #define __NVIC_PRIO_BITS 3U 212 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 213 #endif 214 215 #ifndef __Vendor_SysTickConfig 216 #define __Vendor_SysTickConfig 0U 217 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 218 #endif 219 #endif 220 221 /* IO definitions (access restrictions to peripheral registers) */ 222 /** 223 \defgroup CMSIS_glob_defs CMSIS Global Defines 224 225 <strong>IO Type Qualifiers</strong> are used 226 \li to specify the access to peripheral variables. 227 \li for automatic generation of peripheral register debug information. 228 */ 229 #ifdef __cplusplus 230 #define __I volatile /*!< Defines 'read only' permissions */ 231 #else 232 #define __I volatile const /*!< Defines 'read only' permissions */ 233 #endif 234 #define __O volatile /*!< Defines 'write only' permissions */ 235 #define __IO volatile /*!< Defines 'read / write' permissions */ 236 237 /* following defines should be used for structure members */ 238 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 239 #define __OM volatile /*! Defines 'write only' structure member permissions */ 240 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 241 242 /*@} end of group Cortex_M7 */ 243 244 /******************************************************************************* 245 * Register Abstraction 246 Core Register contain: 247 - Core Register 248 - Core NVIC Register 249 - Core SCB Register 250 - Core SysTick Register 251 - Core Debug Register 252 - Core MPU Register 253 - Core FPU Register 254 ******************************************************************************/ 255 /** 256 \defgroup CMSIS_core_register Defines and Type Definitions 257 \brief Type definitions and defines for Cortex-M processor based devices. 258 */ 259 260 /** 261 \ingroup CMSIS_core_register 262 \defgroup CMSIS_CORE Status and Control Registers 263 \brief Core Register type definitions. 264 @{ 265 */ 266 267 /** 268 \brief Union type to access the Application Program Status Register (APSR). 269 */ 270 typedef union { 271 struct { 272 uint32_t _reserved0 :16; /*!< bit: 0..15 Reserved */ 273 uint32_t GE :4; /*!< bit: 16..19 Greater than or Equal flags */ 274 uint32_t _reserved1 :7; /*!< bit: 20..26 Reserved */ 275 uint32_t Q :1; /*!< bit: 27 Saturation condition flag */ 276 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 277 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 278 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 279 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 280 } b; /*!< Structure used for bit access */ 281 uint32_t w; /*!< Type used for word access */ 282 } APSR_Type; 283 284 /* APSR Register Definitions */ 285 #define APSR_N_Pos 31U /*!< APSR: N Position */ 286 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 287 288 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 289 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 290 291 #define APSR_C_Pos 29U /*!< APSR: C Position */ 292 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 293 294 #define APSR_V_Pos 28U /*!< APSR: V Position */ 295 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 296 297 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 298 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 299 300 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 301 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 302 303 /** 304 \brief Union type to access the Interrupt Program Status Register (IPSR). 305 */ 306 typedef union { 307 struct { 308 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 309 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 310 } b; /*!< Structure used for bit access */ 311 uint32_t w; /*!< Type used for word access */ 312 } IPSR_Type; 313 314 /* IPSR Register Definitions */ 315 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 316 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 317 318 /** 319 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 320 */ 321 typedef union { 322 struct { 323 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 324 uint32_t _reserved0 :1; /*!< bit: 9 Reserved */ 325 uint32_t ICI_IT_1 :6; /*!< bit: 10..15 ICI/IT part 1 */ 326 uint32_t GE :4; /*!< bit: 16..19 Greater than or Equal flags */ 327 uint32_t _reserved1 :4; /*!< bit: 20..23 Reserved */ 328 uint32_t T :1; /*!< bit: 24 Thumb bit */ 329 uint32_t ICI_IT_2 :2; /*!< bit: 25..26 ICI/IT part 2 */ 330 uint32_t Q :1; /*!< bit: 27 Saturation condition flag */ 331 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 332 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 333 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 334 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 335 } b; /*!< Structure used for bit access */ 336 uint32_t w; /*!< Type used for word access */ 337 } xPSR_Type; 338 339 /* xPSR Register Definitions */ 340 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 341 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 342 343 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 344 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 345 346 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 347 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 348 349 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 350 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 351 352 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 353 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 354 355 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 356 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 357 358 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 359 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 360 361 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 362 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 363 364 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 365 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 366 367 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 368 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 369 370 /** 371 \brief Union type to access the Control Registers (CONTROL). 372 */ 373 typedef union { 374 struct { 375 uint32_t nPRIV :1; /*!< bit: 0 Execution privilege in Thread mode */ 376 uint32_t SPSEL :1; /*!< bit: 1 Stack to be used */ 377 uint32_t FPCA :1; /*!< bit: 2 FP extension active flag */ 378 uint32_t _reserved0 :29; /*!< bit: 3..31 Reserved */ 379 } b; /*!< Structure used for bit access */ 380 uint32_t w; /*!< Type used for word access */ 381 } CONTROL_Type; 382 383 /* CONTROL Register Definitions */ 384 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 385 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 386 387 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 388 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 389 390 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 391 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 392 393 /*@} end of group CMSIS_CORE */ 394 395 /** 396 \ingroup CMSIS_core_register 397 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 398 \brief Type definitions for the NVIC Registers 399 @{ 400 */ 401 402 /** 403 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 404 */ 405 typedef struct { 406 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 407 uint32_t RESERVED0[24U]; 408 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 409 uint32_t RSERVED1[24U]; 410 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 411 uint32_t RESERVED2[24U]; 412 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 413 uint32_t RESERVED3[24U]; 414 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 415 uint32_t RESERVED4[56U]; 416 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 417 uint32_t RESERVED5[644U]; 418 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 419 } NVIC_Type; 420 421 /* Software Triggered Interrupt Register Definitions */ 422 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 423 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 424 425 /*@} end of group CMSIS_NVIC */ 426 427 /** 428 \ingroup CMSIS_core_register 429 \defgroup CMSIS_SCB System Control Block (SCB) 430 \brief Type definitions for the System Control Block Registers 431 @{ 432 */ 433 434 /** 435 \brief Structure type to access the System Control Block (SCB). 436 */ 437 typedef struct { 438 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 439 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 440 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 441 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 442 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 443 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 444 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 445 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 446 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 447 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 448 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 449 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 450 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 451 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 452 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 453 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 454 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 455 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 456 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 457 uint32_t RESERVED0[1U]; 458 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 459 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 460 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ 461 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ 462 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 463 uint32_t RESERVED3[93U]; 464 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 465 uint32_t RESERVED4[15U]; 466 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ 467 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ 468 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ 469 uint32_t RESERVED5[1U]; 470 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 471 uint32_t RESERVED6[1U]; 472 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 473 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 474 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 475 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 476 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 477 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ 478 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ 479 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ 480 uint32_t RESERVED7[6U]; 481 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ 482 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ 483 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ 484 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ 485 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ 486 uint32_t RESERVED8[1U]; 487 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ 488 } SCB_Type; 489 490 /* SCB CPUID Register Definitions */ 491 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 492 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 493 494 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 495 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 496 497 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 498 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 499 500 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 501 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 502 503 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 504 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 505 506 /* SCB Interrupt Control State Register Definitions */ 507 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 508 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 509 510 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 511 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 512 513 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 514 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 515 516 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 517 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 518 519 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 520 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 521 522 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 523 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 524 525 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 526 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 527 528 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 529 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 530 531 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 532 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 533 534 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 535 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 536 537 /* SCB Vector Table Offset Register Definitions */ 538 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 539 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 540 541 /* SCB Application Interrupt and Reset Control Register Definitions */ 542 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 543 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 544 545 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 546 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 547 548 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 549 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 550 551 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 552 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 553 554 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 555 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 556 557 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 558 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 559 560 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 561 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 562 563 /* SCB System Control Register Definitions */ 564 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 565 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 566 567 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 568 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 569 570 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 571 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 572 573 /* SCB Configuration Control Register Definitions */ 574 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ 575 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ 576 577 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ 578 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ 579 580 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ 581 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ 582 583 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 584 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 585 586 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 587 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 588 589 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 590 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 591 592 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 593 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 594 595 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 596 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 597 598 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 599 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 600 601 /* SCB System Handler Control and State Register Definitions */ 602 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 603 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 604 605 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 606 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 607 608 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 609 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 610 611 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 612 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 613 614 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 615 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 616 617 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 618 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 619 620 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 621 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 622 623 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 624 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 625 626 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 627 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 628 629 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 630 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 631 632 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 633 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 634 635 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 636 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 637 638 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 639 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 640 641 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 642 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 643 644 /* SCB Configurable Fault Status Register Definitions */ 645 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 646 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 647 648 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 649 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 650 651 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 652 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 653 654 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 655 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 656 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 657 658 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 659 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 660 661 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 662 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 663 664 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 665 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 666 667 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 668 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 669 670 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 671 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 672 673 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 674 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 675 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 676 677 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 678 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 679 680 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 681 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 682 683 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 684 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 685 686 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 687 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 688 689 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 690 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 691 692 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 693 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 694 695 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 696 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 697 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 698 699 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 700 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 701 702 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 703 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 704 705 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 706 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 707 708 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 709 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 710 711 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 712 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 713 714 /* SCB Hard Fault Status Register Definitions */ 715 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 716 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 717 718 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 719 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 720 721 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 722 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 723 724 /* SCB Debug Fault Status Register Definitions */ 725 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 726 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 727 728 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 729 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 730 731 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 732 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 733 734 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 735 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 736 737 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 738 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 739 740 /* SCB Cache Level ID Register Definitions */ 741 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ 742 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ 743 744 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ 745 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ 746 747 /* SCB Cache Type Register Definitions */ 748 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ 749 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ 750 751 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ 752 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ 753 754 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ 755 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ 756 757 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ 758 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ 759 760 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ 761 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ 762 763 /* SCB Cache Size ID Register Definitions */ 764 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ 765 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ 766 767 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ 768 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ 769 770 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ 771 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ 772 773 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ 774 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ 775 776 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ 777 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ 778 779 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ 780 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ 781 782 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ 783 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ 784 785 /* SCB Cache Size Selection Register Definitions */ 786 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ 787 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ 788 789 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ 790 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ 791 792 /* SCB Software Triggered Interrupt Register Definitions */ 793 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ 794 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ 795 796 /* SCB D-Cache Invalidate by Set-way Register Definitions */ 797 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ 798 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ 799 800 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ 801 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ 802 803 /* SCB D-Cache Clean by Set-way Register Definitions */ 804 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ 805 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ 806 807 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ 808 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ 809 810 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ 811 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ 812 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ 813 814 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ 815 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ 816 817 /* Instruction Tightly-Coupled Memory Control Register Definitions */ 818 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ 819 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ 820 821 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ 822 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ 823 824 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ 825 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ 826 827 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ 828 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ 829 830 /* Data Tightly-Coupled Memory Control Register Definitions */ 831 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ 832 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ 833 834 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ 835 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ 836 837 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ 838 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ 839 840 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ 841 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ 842 843 /* AHBP Control Register Definitions */ 844 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ 845 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ 846 847 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ 848 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ 849 850 /* L1 Cache Control Register Definitions */ 851 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ 852 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ 853 854 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ 855 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ 856 857 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ 858 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ 859 860 /* AHBS Control Register Definitions */ 861 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ 862 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ 863 864 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ 865 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ 866 867 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ 868 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ 869 870 /* Auxiliary Bus Fault Status Register Definitions */ 871 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ 872 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ 873 874 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ 875 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ 876 877 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ 878 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ 879 880 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ 881 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ 882 883 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ 884 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ 885 886 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ 887 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ 888 889 /*@} end of group CMSIS_SCB */ 890 891 /** 892 \ingroup CMSIS_core_register 893 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 894 \brief Type definitions for the System Control and ID Register not in the SCB 895 @{ 896 */ 897 898 /** 899 \brief Structure type to access the System Control and ID Register not in the SCB. 900 */ 901 typedef struct { 902 uint32_t RESERVED0[1U]; 903 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 904 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 905 } SCnSCB_Type; 906 907 /* Interrupt Controller Type Register Definitions */ 908 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 909 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 910 911 /* Auxiliary Control Register Definitions */ 912 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ 913 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ 914 915 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ 916 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ 917 918 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ 919 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ 920 921 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 922 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 923 924 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 925 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 926 927 /*@} end of group CMSIS_SCnotSCB */ 928 929 /** 930 \ingroup CMSIS_core_register 931 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 932 \brief Type definitions for the System Timer Registers. 933 @{ 934 */ 935 936 /** 937 \brief Structure type to access the System Timer (SysTick). 938 */ 939 typedef struct { 940 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 941 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 942 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 943 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 944 } SysTick_Type; 945 946 /* SysTick Control / Status Register Definitions */ 947 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 948 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 949 950 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 951 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 952 953 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 954 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 955 956 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 957 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 958 959 /* SysTick Reload Register Definitions */ 960 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 961 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 962 963 /* SysTick Current Register Definitions */ 964 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 965 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 966 967 /* SysTick Calibration Register Definitions */ 968 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 969 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 970 971 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 972 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 973 974 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 975 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 976 977 /*@} end of group CMSIS_SysTick */ 978 979 /** 980 \ingroup CMSIS_core_register 981 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 982 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 983 @{ 984 */ 985 986 /** 987 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 988 */ 989 typedef struct { 990 __OM union 991 { 992 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 993 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 994 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 995 } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 996 uint32_t RESERVED0[864U]; 997 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 998 uint32_t RESERVED1[15U]; 999 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 1000 uint32_t RESERVED2[15U]; 1001 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 1002 uint32_t RESERVED3[29U]; 1003 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 1004 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 1005 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 1006 uint32_t RESERVED4[43U]; 1007 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 1008 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 1009 uint32_t RESERVED5[6U]; 1010 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 1011 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 1012 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 1013 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 1014 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 1015 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 1016 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 1017 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 1018 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 1019 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 1020 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 1021 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 1022 } ITM_Type; 1023 1024 /* ITM Trace Privilege Register Definitions */ 1025 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1026 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 1027 1028 /* ITM Trace Control Register Definitions */ 1029 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 1030 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 1031 1032 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 1033 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 1034 1035 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 1036 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 1037 1038 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 1039 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 1040 1041 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 1042 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 1043 1044 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 1045 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 1046 1047 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 1048 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 1049 1050 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 1051 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 1052 1053 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 1054 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 1055 1056 /* ITM Integration Write Register Definitions */ 1057 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 1058 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 1059 1060 /* ITM Integration Read Register Definitions */ 1061 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 1062 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 1063 1064 /* ITM Integration Mode Control Register Definitions */ 1065 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 1066 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 1067 1068 /* ITM Lock Status Register Definitions */ 1069 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 1070 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 1071 1072 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 1073 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 1074 1075 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 1076 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 1077 1078 /*@}*//* end of group CMSIS_ITM */ 1079 1080 /** 1081 \ingroup CMSIS_core_register 1082 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 1083 \brief Type definitions for the Data Watchpoint and Trace (DWT) 1084 @{ 1085 */ 1086 1087 /** 1088 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 1089 */ 1090 typedef struct { 1091 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 1092 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 1093 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 1094 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 1095 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 1096 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 1097 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 1098 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 1099 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 1100 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 1101 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 1102 uint32_t RESERVED0[1U]; 1103 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 1104 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 1105 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 1106 uint32_t RESERVED1[1U]; 1107 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 1108 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 1109 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 1110 uint32_t RESERVED2[1U]; 1111 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 1112 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 1113 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 1114 uint32_t RESERVED3[981U]; 1115 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ 1116 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ 1117 } DWT_Type; 1118 1119 /* DWT Control Register Definitions */ 1120 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 1121 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 1122 1123 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 1124 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 1125 1126 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 1127 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 1128 1129 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 1130 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 1131 1132 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 1133 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 1134 1135 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 1136 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 1137 1138 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 1139 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 1140 1141 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 1142 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 1143 1144 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 1145 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 1146 1147 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 1148 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 1149 1150 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 1151 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 1152 1153 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 1154 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 1155 1156 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 1157 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 1158 1159 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 1160 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 1161 1162 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 1163 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 1164 1165 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 1166 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 1167 1168 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 1169 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 1170 1171 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 1172 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 1173 1174 /* DWT CPI Count Register Definitions */ 1175 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 1176 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 1177 1178 /* DWT Exception Overhead Count Register Definitions */ 1179 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 1180 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 1181 1182 /* DWT Sleep Count Register Definitions */ 1183 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 1184 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 1185 1186 /* DWT LSU Count Register Definitions */ 1187 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 1188 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 1189 1190 /* DWT Folded-instruction Count Register Definitions */ 1191 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 1192 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 1193 1194 /* DWT Comparator Mask Register Definitions */ 1195 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 1196 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 1197 1198 /* DWT Comparator Function Register Definitions */ 1199 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 1200 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 1201 1202 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 1203 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 1204 1205 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 1206 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 1207 1208 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 1209 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 1210 1211 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 1212 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 1213 1214 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 1215 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 1216 1217 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 1218 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 1219 1220 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 1221 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 1222 1223 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 1224 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 1225 1226 /*@}*//* end of group CMSIS_DWT */ 1227 1228 /** 1229 \ingroup CMSIS_core_register 1230 \defgroup CMSIS_TPI Trace Port Interface (TPI) 1231 \brief Type definitions for the Trace Port Interface (TPI) 1232 @{ 1233 */ 1234 1235 /** 1236 \brief Structure type to access the Trace Port Interface Register (TPI). 1237 */ 1238 typedef struct { 1239 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 1240 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 1241 uint32_t RESERVED0[2U]; 1242 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 1243 uint32_t RESERVED1[55U]; 1244 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 1245 uint32_t RESERVED2[131U]; 1246 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 1247 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 1248 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 1249 uint32_t RESERVED3[759U]; 1250 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 1251 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 1252 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 1253 uint32_t RESERVED4[1U]; 1254 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 1255 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 1256 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 1257 uint32_t RESERVED5[39U]; 1258 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 1259 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 1260 uint32_t RESERVED7[8U]; 1261 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 1262 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 1263 } TPI_Type; 1264 1265 /* TPI Asynchronous Clock Prescaler Register Definitions */ 1266 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 1267 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 1268 1269 /* TPI Selected Pin Protocol Register Definitions */ 1270 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 1271 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 1272 1273 /* TPI Formatter and Flush Status Register Definitions */ 1274 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 1275 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 1276 1277 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 1278 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 1279 1280 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 1281 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 1282 1283 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 1284 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 1285 1286 /* TPI Formatter and Flush Control Register Definitions */ 1287 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 1288 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 1289 1290 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 1291 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 1292 1293 /* TPI TRIGGER Register Definitions */ 1294 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 1295 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 1296 1297 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1298 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 1299 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 1300 1301 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 1302 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 1303 1304 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 1305 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 1306 1307 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 1308 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 1309 1310 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 1311 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 1312 1313 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 1314 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 1315 1316 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 1317 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 1318 1319 /* TPI ITATBCTR2 Register Definitions */ 1320 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ 1321 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ 1322 1323 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ 1324 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ 1325 1326 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1327 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 1328 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 1329 1330 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 1331 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 1332 1333 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 1334 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 1335 1336 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 1337 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 1338 1339 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 1340 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 1341 1342 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 1343 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 1344 1345 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 1346 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 1347 1348 /* TPI ITATBCTR0 Register Definitions */ 1349 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ 1350 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ 1351 1352 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ 1353 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ 1354 1355 /* TPI Integration Mode Control Register Definitions */ 1356 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 1357 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 1358 1359 /* TPI DEVID Register Definitions */ 1360 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 1361 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1362 1363 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 1364 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1365 1366 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 1367 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1368 1369 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 1370 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 1371 1372 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 1373 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 1374 1375 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 1376 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 1377 1378 /* TPI DEVTYPE Register Definitions */ 1379 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 1380 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 1381 1382 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 1383 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1384 1385 /*@}*//* end of group CMSIS_TPI */ 1386 1387 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1388 /** 1389 \ingroup CMSIS_core_register 1390 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1391 \brief Type definitions for the Memory Protection Unit (MPU) 1392 @{ 1393 */ 1394 1395 /** 1396 \brief Structure type to access the Memory Protection Unit (MPU). 1397 */ 1398 typedef struct 1399 { 1400 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1401 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1402 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1403 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 1404 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 1405 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 1406 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 1407 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 1408 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 1409 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 1410 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 1411 } MPU_Type; 1412 1413 #define MPU_TYPE_RALIASES 4U 1414 1415 /* MPU Type Register Definitions */ 1416 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 1417 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 1418 1419 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 1420 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 1421 1422 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 1423 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 1424 1425 /* MPU Control Register Definitions */ 1426 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 1427 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 1428 1429 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 1430 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 1431 1432 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 1433 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 1434 1435 /* MPU Region Number Register Definitions */ 1436 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 1437 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 1438 1439 /* MPU Region Base Address Register Definitions */ 1440 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1441 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1442 1443 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1444 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1445 1446 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1447 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 1448 1449 /* MPU Region Attribute and Size Register Definitions */ 1450 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1451 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1452 1453 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1454 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1455 1456 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1457 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1458 1459 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1460 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1461 1462 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 1463 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 1464 1465 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 1466 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 1467 1468 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 1469 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 1470 1471 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 1472 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 1473 1474 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 1475 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 1476 1477 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 1478 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 1479 1480 /*@} end of group CMSIS_MPU */ 1481 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 1482 1483 /** 1484 \ingroup CMSIS_core_register 1485 \defgroup CMSIS_FPU Floating Point Unit (FPU) 1486 \brief Type definitions for the Floating Point Unit (FPU) 1487 @{ 1488 */ 1489 1490 /** 1491 \brief Structure type to access the Floating Point Unit (FPU). 1492 */ 1493 typedef struct { 1494 uint32_t RESERVED0[1U]; 1495 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 1496 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 1497 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 1498 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 1499 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 1500 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ 1501 } FPU_Type; 1502 1503 /* Floating-Point Context Control Register Definitions */ 1504 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 1505 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 1506 1507 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 1508 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 1509 1510 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 1511 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 1512 1513 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 1514 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 1515 1516 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 1517 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 1518 1519 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 1520 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 1521 1522 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 1523 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 1524 1525 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 1526 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 1527 1528 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 1529 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 1530 1531 /* Floating-Point Context Address Register Definitions */ 1532 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 1533 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 1534 1535 /* Floating-Point Default Status Control Register Definitions */ 1536 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 1537 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 1538 1539 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 1540 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 1541 1542 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 1543 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 1544 1545 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 1546 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 1547 1548 /* Media and FP Feature Register 0 Definitions */ 1549 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 1550 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 1551 1552 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 1553 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 1554 1555 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 1556 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 1557 1558 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 1559 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 1560 1561 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 1562 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 1563 1564 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 1565 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 1566 1567 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 1568 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 1569 1570 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 1571 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 1572 1573 /* Media and FP Feature Register 1 Definitions */ 1574 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 1575 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 1576 1577 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1578 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1579 1580 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1581 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1582 1583 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1584 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 1585 1586 /* Media and FP Feature Register 2 Definitions */ 1587 1588 /*@} end of group CMSIS_FPU */ 1589 1590 /** 1591 \ingroup CMSIS_core_register 1592 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1593 \brief Type definitions for the Core Debug Registers 1594 @{ 1595 */ 1596 1597 /** 1598 \brief Structure type to access the Core Debug Register (CoreDebug). 1599 */ 1600 typedef struct { 1601 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1602 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1603 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1604 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1605 } CoreDebug_Type; 1606 1607 /* Debug Halting Control and Status Register Definitions */ 1608 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 1609 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1610 1611 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1612 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1613 1614 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1615 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1616 1617 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1618 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1619 1620 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 1621 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1622 1623 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 1624 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1625 1626 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 1627 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1628 1629 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 1630 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 1631 1632 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1633 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1634 1635 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 1636 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1637 1638 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 1639 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1640 1641 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1642 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1643 1644 /* Debug Core Register Selector Register Definitions */ 1645 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 1646 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1647 1648 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 1649 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 1650 1651 /* Debug Exception and Monitor Control Register Definitions */ 1652 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 1653 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 1654 1655 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 1656 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 1657 1658 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 1659 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 1660 1661 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 1662 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 1663 1664 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 1665 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 1666 1667 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1668 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1669 1670 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 1671 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 1672 1673 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 1674 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 1675 1676 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 1677 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 1678 1679 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 1680 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 1681 1682 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 1683 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 1684 1685 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 1686 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 1687 1688 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1689 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1690 1691 /*@} end of group CMSIS_CoreDebug */ 1692 1693 /** 1694 \ingroup CMSIS_core_register 1695 \defgroup CMSIS_core_bitfield Core register bit field macros 1696 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1697 @{ 1698 */ 1699 1700 /** 1701 \brief Mask and shift a bit field value for use in a register bit range. 1702 \param[in] field Name of the register bit field. 1703 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1704 \return Masked and shifted value. 1705 */ 1706 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1707 1708 /** 1709 \brief Mask and shift a register value to extract a bit filed value. 1710 \param[in] field Name of the register bit field. 1711 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1712 \return Masked and shifted bit field value. 1713 */ 1714 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1715 1716 /*@} end of group CMSIS_core_bitfield */ 1717 1718 /** 1719 \ingroup CMSIS_core_register 1720 \defgroup CMSIS_core_base Core Definitions 1721 \brief Definitions for base addresses, unions, and structures. 1722 @{ 1723 */ 1724 1725 /* Memory mapping of Core Hardware */ 1726 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1727 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1728 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1729 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1730 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1731 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1732 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1733 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1734 1735 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 1736 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1737 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1738 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1739 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 1740 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1741 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1742 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 1743 1744 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1745 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1746 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1747 #endif 1748 1749 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 1750 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 1751 1752 /*@} */ 1753 1754 /******************************************************************************* 1755 * Hardware Abstraction Layer 1756 Core Function Interface contains: 1757 - Core NVIC Functions 1758 - Core SysTick Functions 1759 - Core Debug Functions 1760 - Core Register Access Functions 1761 ******************************************************************************/ 1762 /** 1763 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1764 */ 1765 1766 /* ########################## NVIC functions #################################### */ 1767 /** 1768 \ingroup CMSIS_Core_FunctionInterface 1769 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1770 \brief Functions that manage interrupts and exceptions via the NVIC. 1771 @{ 1772 */ 1773 1774 #ifdef CMSIS_NVIC_VIRTUAL 1775 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1776 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1777 #endif 1778 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1779 #else 1780 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1781 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1782 #define NVIC_EnableIRQ __NVIC_EnableIRQ 1783 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1784 #define NVIC_DisableIRQ __NVIC_DisableIRQ 1785 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1786 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1787 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1788 #define NVIC_GetActive __NVIC_GetActive 1789 #define NVIC_SetPriority __NVIC_SetPriority 1790 #define NVIC_GetPriority __NVIC_GetPriority 1791 #define NVIC_SystemReset __NVIC_SystemReset 1792 #endif /* CMSIS_NVIC_VIRTUAL */ 1793 1794 #ifdef CMSIS_VECTAB_VIRTUAL 1795 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1796 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1797 #endif 1798 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1799 #else 1800 #define NVIC_SetVector __NVIC_SetVector 1801 #define NVIC_GetVector __NVIC_GetVector 1802 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1803 1804 #define NVIC_USER_IRQ_OFFSET 16 1805 1806 /* The following EXC_RETURN values are saved the LR on exception entry */ 1807 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 1808 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 1809 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 1810 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ 1811 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ 1812 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ 1813 1814 /** 1815 \brief Set Priority Grouping 1816 \details Sets the priority grouping field using the required unlock sequence. 1817 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1818 Only values from 0..7 are used. 1819 In case of a conflict between priority grouping and available 1820 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1821 \param [in] PriorityGroup Priority grouping field. 1822 */ 1823 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1824 { 1825 uint32_t reg_value; 1826 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1827 1828 reg_value = SCB->AIRCR; /* read old register configuration */ 1829 reg_value &= ~((uint32_t) (SCB_AIRCR_VECTKEY_Msk 1830 | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 1831 reg_value = (reg_value | ((uint32_t) 0x5FAUL << SCB_AIRCR_VECTKEY_Pos) 1832 | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */ 1833 SCB->AIRCR = reg_value; 1834 } 1835 1836 /** 1837 \brief Get Priority Grouping 1838 \details Reads the priority grouping field from the NVIC Interrupt Controller. 1839 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1840 */ 1841 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1842 { 1843 return ((uint32_t) ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) 1844 >> SCB_AIRCR_PRIGROUP_Pos)); 1845 } 1846 1847 /** 1848 \brief Enable Interrupt 1849 \details Enables a device specific interrupt in the NVIC interrupt controller. 1850 \param [in] IRQn Device specific interrupt number. 1851 \note IRQn must not be negative. 1852 */ 1853 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1854 { 1855 if ((int32_t) (IRQn) >= 0) { 1856 NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1857 << (((uint32_t) IRQn) & 0x1FUL)); 1858 } 1859 } 1860 1861 /** 1862 \brief Get Interrupt Enable status 1863 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1864 \param [in] IRQn Device specific interrupt number. 1865 \return 0 Interrupt is not enabled. 1866 \return 1 Interrupt is enabled. 1867 \note IRQn must not be negative. 1868 */ 1869 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1870 { 1871 if ((int32_t) (IRQn) >= 0) { 1872 return ((uint32_t) ( 1873 ((NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] 1874 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1875 1UL : 0UL)); 1876 } else { 1877 return (0U); 1878 } 1879 } 1880 1881 /** 1882 \brief Disable Interrupt 1883 \details Disables a device specific interrupt in the NVIC interrupt controller. 1884 \param [in] IRQn Device specific interrupt number. 1885 \note IRQn must not be negative. 1886 */ 1887 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1888 { 1889 if ((int32_t) (IRQn) >= 0) { 1890 NVIC->ICER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1891 << (((uint32_t) IRQn) & 0x1FUL)); 1892 __DSB(); 1893 __ISB(); 1894 } 1895 } 1896 1897 /** 1898 \brief Get Pending Interrupt 1899 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 1900 \param [in] IRQn Device specific interrupt number. 1901 \return 0 Interrupt status is not pending. 1902 \return 1 Interrupt status is pending. 1903 \note IRQn must not be negative. 1904 */ 1905 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1906 { 1907 if ((int32_t) (IRQn) >= 0) { 1908 return ((uint32_t) ( 1909 ((NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] 1910 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1911 1UL : 0UL)); 1912 } else { 1913 return (0U); 1914 } 1915 } 1916 1917 /** 1918 \brief Set Pending Interrupt 1919 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1920 \param [in] IRQn Device specific interrupt number. 1921 \note IRQn must not be negative. 1922 */ 1923 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1924 { 1925 if ((int32_t) (IRQn) >= 0) { 1926 NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1927 << (((uint32_t) IRQn) & 0x1FUL)); 1928 } 1929 } 1930 1931 /** 1932 \brief Clear Pending Interrupt 1933 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1934 \param [in] IRQn Device specific interrupt number. 1935 \note IRQn must not be negative. 1936 */ 1937 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1938 { 1939 if ((int32_t) (IRQn) >= 0) { 1940 NVIC->ICPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1941 << (((uint32_t) IRQn) & 0x1FUL)); 1942 } 1943 } 1944 1945 /** 1946 \brief Get Active Interrupt 1947 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 1948 \param [in] IRQn Device specific interrupt number. 1949 \return 0 Interrupt status is not active. 1950 \return 1 Interrupt status is active. 1951 \note IRQn must not be negative. 1952 */ 1953 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1954 { 1955 if ((int32_t) (IRQn) >= 0) { 1956 return ((uint32_t) ( 1957 ((NVIC->IABR[(((uint32_t) IRQn) >> 5UL)] 1958 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1959 1UL : 0UL)); 1960 } else { 1961 return (0U); 1962 } 1963 } 1964 1965 /** 1966 \brief Set Interrupt Priority 1967 \details Sets the priority of a device specific interrupt or a processor exception. 1968 The interrupt number can be positive to specify a device specific interrupt, 1969 or negative to specify a processor exception. 1970 \param [in] IRQn Interrupt number. 1971 \param [in] priority Priority to set. 1972 \note The priority cannot be set for every processor exception. 1973 */ 1974 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1975 { 1976 if ((int32_t) (IRQn) >= 0) { 1977 NVIC->IP[((uint32_t) IRQn)] = (uint8_t) ((priority 1978 << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL); 1979 } else { 1980 SCB->SHPR[(((uint32_t) IRQn) & 0xFUL) - 4UL] = (uint8_t) ((priority 1981 << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL); 1982 } 1983 } 1984 1985 /** 1986 \brief Get Interrupt Priority 1987 \details Reads the priority of a device specific interrupt or a processor exception. 1988 The interrupt number can be positive to specify a device specific interrupt, 1989 or negative to specify a processor exception. 1990 \param [in] IRQn Interrupt number. 1991 \return Interrupt Priority. 1992 Value is aligned automatically to the implemented priority bits of the microcontroller. 1993 */ 1994 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1995 { 1996 1997 if ((int32_t) (IRQn) >= 0) { 1998 return (((uint32_t) NVIC->IP[((uint32_t) IRQn)] 1999 >> (8U - __NVIC_PRIO_BITS))); 2000 } else { 2001 return (((uint32_t) SCB->SHPR[(((uint32_t) IRQn) & 0xFUL) - 4UL] 2002 >> (8U - __NVIC_PRIO_BITS))); 2003 } 2004 } 2005 2006 /** 2007 \brief Encode Priority 2008 \details Encodes the priority for an interrupt with the given priority group, 2009 preemptive priority value, and subpriority value. 2010 In case of a conflict between priority grouping and available 2011 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 2012 \param [in] PriorityGroup Used priority group. 2013 \param [in] PreemptPriority Preemptive priority value (starting from 0). 2014 \param [in] SubPriority Subpriority value (starting from 0). 2015 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 2016 */ 2017 __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, 2018 uint32_t PreemptPriority, uint32_t SubPriority) 2019 { 2020 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 2021 uint32_t PreemptPriorityBits; 2022 uint32_t SubPriorityBits; 2023 2024 PreemptPriorityBits = 2025 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 2026 (uint32_t) (__NVIC_PRIO_BITS) : 2027 (uint32_t) (7UL - PriorityGroupTmp); 2028 SubPriorityBits = 2029 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) 2030 < (uint32_t) 7UL) ? 2031 (uint32_t) 0UL : 2032 (uint32_t) ((PriorityGroupTmp - 7UL) 2033 + (uint32_t) (__NVIC_PRIO_BITS)); 2034 2035 return (((PreemptPriority 2036 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL)) 2037 << SubPriorityBits) 2038 | ((SubPriority & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL)))); 2039 } 2040 2041 /** 2042 \brief Decode Priority 2043 \details Decodes an interrupt priority value with a given priority group to 2044 preemptive priority value and subpriority value. 2045 In case of a conflict between priority grouping and available 2046 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 2047 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 2048 \param [in] PriorityGroup Used priority group. 2049 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 2050 \param [out] pSubPriority Subpriority value (starting from 0). 2051 */ 2052 __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, 2053 uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 2054 uint32_t *const pSubPriority) 2055 { 2056 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 2057 uint32_t PreemptPriorityBits; 2058 uint32_t SubPriorityBits; 2059 2060 PreemptPriorityBits = 2061 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 2062 (uint32_t) (__NVIC_PRIO_BITS) : 2063 (uint32_t) (7UL - PriorityGroupTmp); 2064 SubPriorityBits = 2065 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) 2066 < (uint32_t) 7UL) ? 2067 (uint32_t) 0UL : 2068 (uint32_t) ((PriorityGroupTmp - 7UL) 2069 + (uint32_t) (__NVIC_PRIO_BITS)); 2070 2071 *pPreemptPriority = (Priority >> SubPriorityBits) 2072 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL); 2073 *pSubPriority = (Priority) 2074 & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL); 2075 } 2076 2077 /** 2078 \brief Set Interrupt Vector 2079 \details Sets an interrupt vector in SRAM based interrupt vector table. 2080 The interrupt number can be positive to specify a device specific interrupt, 2081 or negative to specify a processor exception. 2082 VTOR must been relocated to SRAM before. 2083 \param [in] IRQn Interrupt number 2084 \param [in] vector Address of interrupt handler function 2085 */ 2086 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 2087 { 2088 uint32_t *vectors = (uint32_t*) SCB->VTOR; 2089 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 2090 } 2091 2092 /** 2093 \brief Get Interrupt Vector 2094 \details Reads an interrupt vector from interrupt vector table. 2095 The interrupt number can be positive to specify a device specific interrupt, 2096 or negative to specify a processor exception. 2097 \param [in] IRQn Interrupt number. 2098 \return Address of interrupt handler function 2099 */ 2100 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 2101 { 2102 uint32_t *vectors = (uint32_t*) SCB->VTOR; 2103 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 2104 } 2105 2106 /** 2107 \brief System Reset 2108 \details Initiates a system reset request to reset the MCU. 2109 */ 2110 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 2111 { 2112 __DSB(); /* Ensure all outstanding memory accesses included 2113 buffered write are completed before reset */ 2114 SCB->AIRCR = (uint32_t) ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) 2115 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 2116 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 2117 __DSB(); /* Ensure completion of memory access */ 2118 2119 for (;;) /* wait until reset */ 2120 { 2121 __NOP(); 2122 } 2123 } 2124 2125 /*@} end of CMSIS_Core_NVICFunctions */ 2126 2127 /* ########################## MPU functions #################################### */ 2128 2129 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 2130 2131 #include "mpu_armv7.h" 2132 2133 #endif 2134 2135 /* ########################## FPU functions #################################### */ 2136 /** 2137 \ingroup CMSIS_Core_FunctionInterface 2138 \defgroup CMSIS_Core_FpuFunctions FPU Functions 2139 \brief Function that provides FPU type. 2140 @{ 2141 */ 2142 2143 /** 2144 \brief get FPU type 2145 \details returns the FPU type 2146 \returns 2147 - \b 0: No FPU 2148 - \b 1: Single precision FPU 2149 - \b 2: Double + Single precision FPU 2150 */ 2151 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 2152 { 2153 uint32_t mvfr0; 2154 2155 mvfr0 = SCB->MVFR0; 2156 if ((mvfr0 2157 & (FPU_MVFR0_Single_precision_Msk 2158 | FPU_MVFR0_Double_precision_Msk)) == 0x220U) { 2159 return 2U; /* Double + Single precision FPU */ 2160 } else if ((mvfr0 2161 & (FPU_MVFR0_Single_precision_Msk 2162 | FPU_MVFR0_Double_precision_Msk)) == 0x020U) { 2163 return 1U; /* Single precision FPU */ 2164 } else { 2165 return 0U; /* No FPU */ 2166 } 2167 } 2168 2169 /*@} end of CMSIS_Core_FpuFunctions */ 2170 2171 /* ########################## Cache functions #################################### */ 2172 /** 2173 \ingroup CMSIS_Core_FunctionInterface 2174 \defgroup CMSIS_Core_CacheFunctions Cache Functions 2175 \brief Functions that configure Instruction and Data cache. 2176 @{ 2177 */ 2178 2179 /* Cache Size ID Register Macros */ 2180 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) 2181 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) 2182 2183 /** 2184 \brief Enable I-Cache 2185 \details Turns on I-Cache 2186 */ 2187 __STATIC_INLINE void SCB_EnableICache(void) 2188 { 2189 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 2190 __DSB(); 2191 __ISB(); 2192 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 2193 __DSB(); 2194 __ISB(); 2195 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ 2196 __DSB(); 2197 __ISB(); 2198 #endif 2199 } 2200 2201 /** 2202 \brief Disable I-Cache 2203 \details Turns off I-Cache 2204 */ 2205 __STATIC_INLINE void SCB_DisableICache(void) 2206 { 2207 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 2208 __DSB(); 2209 __ISB(); 2210 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ 2211 SCB->ICIALLU = 0UL; /* invalidate I-Cache */ 2212 __DSB(); 2213 __ISB(); 2214 #endif 2215 } 2216 2217 /** 2218 \brief Invalidate I-Cache 2219 \details Invalidates I-Cache 2220 */ 2221 __STATIC_INLINE void SCB_InvalidateICache(void) 2222 { 2223 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) 2224 __DSB(); 2225 __ISB(); 2226 SCB->ICIALLU = 0UL; 2227 __DSB(); 2228 __ISB(); 2229 #endif 2230 } 2231 2232 /** 2233 \brief Enable D-Cache 2234 \details Turns on D-Cache 2235 */ 2236 __STATIC_INLINE void SCB_EnableDCache(void) 2237 { 2238 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 2239 uint32_t ccsidr; 2240 uint32_t sets; 2241 uint32_t ways; 2242 2243 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 2244 __DSB(); 2245 2246 ccsidr = SCB->CCSIDR; 2247 2248 /* invalidate D-Cache */ 2249 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 2250 do { 2251 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 2252 do { 2253 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 2254 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 2255 #if defined ( __CC_ARM ) 2256 __schedule_barrier(); 2257 #endif 2258 } while (ways-- != 0U); 2259 } while(sets-- != 0U); 2260 __DSB(); 2261 2262 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ 2263 2264 __DSB(); 2265 __ISB(); 2266 #endif 2267 } 2268 2269 /** 2270 \brief Disable D-Cache 2271 \details Turns off D-Cache 2272 */ 2273 __STATIC_INLINE void SCB_DisableDCache(void) 2274 { 2275 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 2276 uint32_t ccsidr; 2277 uint32_t sets; 2278 uint32_t ways; 2279 2280 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 2281 __DSB(); 2282 2283 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ 2284 __DSB(); 2285 2286 ccsidr = SCB->CCSIDR; 2287 2288 /* clean & invalidate D-Cache */ 2289 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 2290 do { 2291 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 2292 do { 2293 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | 2294 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); 2295 #if defined ( __CC_ARM ) 2296 __schedule_barrier(); 2297 #endif 2298 } while (ways-- != 0U); 2299 } while(sets-- != 0U); 2300 2301 __DSB(); 2302 __ISB(); 2303 #endif 2304 } 2305 2306 /** 2307 \brief Invalidate D-Cache 2308 \details Invalidates D-Cache 2309 */ 2310 __STATIC_INLINE void SCB_InvalidateDCache(void) 2311 { 2312 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 2313 uint32_t ccsidr; 2314 uint32_t sets; 2315 uint32_t ways; 2316 2317 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 2318 __DSB(); 2319 2320 ccsidr = SCB->CCSIDR; 2321 2322 /* invalidate D-Cache */ 2323 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 2324 do { 2325 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 2326 do { 2327 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | 2328 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); 2329 #if defined ( __CC_ARM ) 2330 __schedule_barrier(); 2331 #endif 2332 } while (ways-- != 0U); 2333 } while(sets-- != 0U); 2334 2335 __DSB(); 2336 __ISB(); 2337 #endif 2338 } 2339 2340 /** 2341 \brief Clean D-Cache 2342 \details Cleans D-Cache 2343 */ 2344 __STATIC_INLINE void SCB_CleanDCache(void) 2345 { 2346 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 2347 uint32_t ccsidr; 2348 uint32_t sets; 2349 uint32_t ways; 2350 2351 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 2352 __DSB(); 2353 2354 ccsidr = SCB->CCSIDR; 2355 2356 /* clean D-Cache */ 2357 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 2358 do { 2359 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 2360 do { 2361 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | 2362 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); 2363 #if defined ( __CC_ARM ) 2364 __schedule_barrier(); 2365 #endif 2366 } while (ways-- != 0U); 2367 } while(sets-- != 0U); 2368 2369 __DSB(); 2370 __ISB(); 2371 #endif 2372 } 2373 2374 /** 2375 \brief Clean & Invalidate D-Cache 2376 \details Cleans and Invalidates D-Cache 2377 */ 2378 __STATIC_INLINE void SCB_CleanInvalidateDCache(void) 2379 { 2380 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 2381 uint32_t ccsidr; 2382 uint32_t sets; 2383 uint32_t ways; 2384 2385 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ 2386 __DSB(); 2387 2388 ccsidr = SCB->CCSIDR; 2389 2390 /* clean & invalidate D-Cache */ 2391 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); 2392 do { 2393 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); 2394 do { 2395 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | 2396 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); 2397 #if defined ( __CC_ARM ) 2398 __schedule_barrier(); 2399 #endif 2400 } while (ways-- != 0U); 2401 } while(sets-- != 0U); 2402 2403 __DSB(); 2404 __ISB(); 2405 #endif 2406 } 2407 2408 /** 2409 \brief D-Cache Invalidate by address 2410 \details Invalidates D-Cache for the given address 2411 \param[in] addr address (aligned to 32-byte boundary) 2412 \param[in] dsize size of memory block (in number of bytes) 2413 */ 2414 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, 2415 int32_t dsize) 2416 { 2417 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 2418 int32_t op_size = dsize; 2419 uint32_t op_addr = (uint32_t)addr; 2420 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ 2421 2422 __DSB(); 2423 2424 while (op_size > 0) { 2425 SCB->DCIMVAC = op_addr; 2426 op_addr += (uint32_t)linesize; 2427 op_size -= linesize; 2428 } 2429 2430 __DSB(); 2431 __ISB(); 2432 #endif 2433 } 2434 2435 /** 2436 \brief D-Cache Clean by address 2437 \details Cleans D-Cache for the given address 2438 \param[in] addr address (aligned to 32-byte boundary) 2439 \param[in] dsize size of memory block (in number of bytes) 2440 */ 2441 __STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize) 2442 { 2443 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 2444 int32_t op_size = dsize; 2445 uint32_t op_addr = (uint32_t) addr; 2446 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ 2447 2448 __DSB(); 2449 2450 while (op_size > 0) { 2451 SCB->DCCMVAC = op_addr; 2452 op_addr += (uint32_t)linesize; 2453 op_size -= linesize; 2454 } 2455 2456 __DSB(); 2457 __ISB(); 2458 #endif 2459 } 2460 2461 /** 2462 \brief D-Cache Clean and Invalidate by address 2463 \details Cleans and invalidates D_Cache for the given address 2464 \param[in] addr address (aligned to 32-byte boundary) 2465 \param[in] dsize size of memory block (in number of bytes) 2466 */ 2467 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, 2468 int32_t dsize) 2469 { 2470 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) 2471 int32_t op_size = dsize; 2472 uint32_t op_addr = (uint32_t) addr; 2473 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ 2474 2475 __DSB(); 2476 2477 while (op_size > 0) { 2478 SCB->DCCIMVAC = op_addr; 2479 op_addr += (uint32_t)linesize; 2480 op_size -= linesize; 2481 } 2482 2483 __DSB(); 2484 __ISB(); 2485 #endif 2486 } 2487 2488 /*@} end of CMSIS_Core_CacheFunctions */ 2489 2490 /* ################################## SysTick function ############################################ */ 2491 /** 2492 \ingroup CMSIS_Core_FunctionInterface 2493 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 2494 \brief Functions that configure the System. 2495 @{ 2496 */ 2497 2498 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 2499 2500 /** 2501 \brief System Tick Configuration 2502 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 2503 Counter is in free running mode to generate periodic interrupts. 2504 \param [in] ticks Number of ticks between two interrupts. 2505 \return 0 Function succeeded. 2506 \return 1 Function failed. 2507 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 2508 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 2509 must contain a vendor-specific implementation of this function. 2510 */ 2511 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 2512 { 2513 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 2514 { 2515 return (1UL); /* Reload value impossible */ 2516 } 2517 2518 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 2519 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 2520 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 2521 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 2522 SysTick_CTRL_TICKINT_Msk | 2523 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 2524 return (0UL); /* Function successful */ 2525 } 2526 2527 #endif 2528 2529 /*@} end of CMSIS_Core_SysTickFunctions */ 2530 2531 /* ##################################### Debug In/Output function ########################################### */ 2532 /** 2533 \ingroup CMSIS_Core_FunctionInterface 2534 \defgroup CMSIS_core_DebugFunctions ITM Functions 2535 \brief Functions that access the ITM debug interface. 2536 @{ 2537 */ 2538 2539 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 2540 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 2541 2542 /** 2543 \brief ITM Send Character 2544 \details Transmits a character via the ITM channel 0, and 2545 \li Just returns when no debugger is connected that has booked the output. 2546 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 2547 \param [in] ch Character to transmit. 2548 \returns Character to transmit. 2549 */ 2550 __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) 2551 { 2552 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 2553 ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ 2554 { 2555 while (ITM->PORT[0U].u32 == 0UL) { 2556 __NOP(); 2557 } 2558 ITM->PORT[0U].u8 = (uint8_t) ch; 2559 } 2560 return (ch); 2561 } 2562 2563 /** 2564 \brief ITM Receive Character 2565 \details Inputs a character via the external variable \ref ITM_RxBuffer. 2566 \return Received character. 2567 \return -1 No character pending. 2568 */ 2569 __STATIC_INLINE int32_t ITM_ReceiveChar(void) 2570 { 2571 int32_t ch = -1; /* no character available */ 2572 2573 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 2574 ch = ITM_RxBuffer; 2575 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 2576 } 2577 2578 return (ch); 2579 } 2580 2581 /** 2582 \brief ITM Check Character 2583 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 2584 \return 0 No character available. 2585 \return 1 Character available. 2586 */ 2587 __STATIC_INLINE int32_t ITM_CheckChar(void) 2588 { 2589 2590 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 2591 return (0); /* no character available */ 2592 } else { 2593 return (1); /* character available */ 2594 } 2595 } 2596 2597 /*@} end of CMSIS_core_DebugFunctions */ 2598 2599 #ifdef __cplusplus 2600 } 2601 #endif 2602 2603 #endif /* __CORE_CM7_H_DEPENDANT */ 2604 2605 #endif /* __CMSIS_GENERIC */