Drivers/CMSIS/Include/core_cm3.h (108906B)
1 /**************************************************************************//** 2 * @file core_cm3.h 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File 4 * @version V5.0.8 5 * @date 04. June 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_CM3_H_GENERIC 32 #define __CORE_CM3_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup Cortex_M3 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS CM3 definitions */ 65 #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ 68 __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_M (3U) /*!< Cortex-M Core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 This core does not support an FPU at all 74 */ 75 #define __FPU_USED 0U 76 77 #if defined ( __CC_ARM ) 78 #if defined __TARGET_FPU_VFP 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 80 #endif 81 82 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 83 #if defined __ARM_PCS_VFP 84 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 85 #endif 86 87 #elif defined ( __GNUC__ ) 88 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 90 #endif 91 92 #elif defined ( __ICCARM__ ) 93 #if defined __ARMVFP__ 94 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 95 #endif 96 97 #elif defined ( __TI_ARM__ ) 98 #if defined __TI_VFP_SUPPORT__ 99 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 100 #endif 101 102 #elif defined ( __TASKING__ ) 103 #if defined __FPU_VFP__ 104 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 105 #endif 106 107 #elif defined ( __CSMC__ ) 108 #if ( __CSMC__ & 0x400U) 109 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 110 #endif 111 112 #endif 113 114 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 115 116 #ifdef __cplusplus 117 } 118 #endif 119 120 #endif /* __CORE_CM3_H_GENERIC */ 121 122 #ifndef __CMSIS_GENERIC 123 124 #ifndef __CORE_CM3_H_DEPENDANT 125 #define __CORE_CM3_H_DEPENDANT 126 127 #ifdef __cplusplus 128 extern "C" { 129 #endif 130 131 /* check device defines and use defaults */ 132 #if defined __CHECK_DEVICE_DEFINES 133 #ifndef __CM3_REV 134 #define __CM3_REV 0x0200U 135 #warning "__CM3_REV not defined in device header file; using default!" 136 #endif 137 138 #ifndef __MPU_PRESENT 139 #define __MPU_PRESENT 0U 140 #warning "__MPU_PRESENT not defined in device header file; using default!" 141 #endif 142 143 #ifndef __NVIC_PRIO_BITS 144 #define __NVIC_PRIO_BITS 3U 145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 146 #endif 147 148 #ifndef __Vendor_SysTickConfig 149 #define __Vendor_SysTickConfig 0U 150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 151 #endif 152 #endif 153 154 /* IO definitions (access restrictions to peripheral registers) */ 155 /** 156 \defgroup CMSIS_glob_defs CMSIS Global Defines 157 158 <strong>IO Type Qualifiers</strong> are used 159 \li to specify the access to peripheral variables. 160 \li for automatic generation of peripheral register debug information. 161 */ 162 #ifdef __cplusplus 163 #define __I volatile /*!< Defines 'read only' permissions */ 164 #else 165 #define __I volatile const /*!< Defines 'read only' permissions */ 166 #endif 167 #define __O volatile /*!< Defines 'write only' permissions */ 168 #define __IO volatile /*!< Defines 'read / write' permissions */ 169 170 /* following defines should be used for structure members */ 171 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 172 #define __OM volatile /*! Defines 'write only' structure member permissions */ 173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 174 175 /*@} end of group Cortex_M3 */ 176 177 /******************************************************************************* 178 * Register Abstraction 179 Core Register contain: 180 - Core Register 181 - Core NVIC Register 182 - Core SCB Register 183 - Core SysTick Register 184 - Core Debug Register 185 - Core MPU Register 186 ******************************************************************************/ 187 /** 188 \defgroup CMSIS_core_register Defines and Type Definitions 189 \brief Type definitions and defines for Cortex-M processor based devices. 190 */ 191 192 /** 193 \ingroup CMSIS_core_register 194 \defgroup CMSIS_CORE Status and Control Registers 195 \brief Core Register type definitions. 196 @{ 197 */ 198 199 /** 200 \brief Union type to access the Application Program Status Register (APSR). 201 */ 202 typedef union { 203 struct { 204 uint32_t _reserved0 :27; /*!< bit: 0..26 Reserved */ 205 uint32_t Q :1; /*!< bit: 27 Saturation condition flag */ 206 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 207 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 208 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 209 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 210 } b; /*!< Structure used for bit access */ 211 uint32_t w; /*!< Type used for word access */ 212 } APSR_Type; 213 214 /* APSR Register Definitions */ 215 #define APSR_N_Pos 31U /*!< APSR: N Position */ 216 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 217 218 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 219 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 220 221 #define APSR_C_Pos 29U /*!< APSR: C Position */ 222 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 223 224 #define APSR_V_Pos 28U /*!< APSR: V Position */ 225 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 226 227 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 228 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 229 230 /** 231 \brief Union type to access the Interrupt Program Status Register (IPSR). 232 */ 233 typedef union { 234 struct { 235 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 236 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 237 } b; /*!< Structure used for bit access */ 238 uint32_t w; /*!< Type used for word access */ 239 } IPSR_Type; 240 241 /* IPSR Register Definitions */ 242 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 243 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 244 245 /** 246 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 247 */ 248 typedef union { 249 struct { 250 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 251 uint32_t _reserved0 :1; /*!< bit: 9 Reserved */ 252 uint32_t ICI_IT_1 :6; /*!< bit: 10..15 ICI/IT part 1 */ 253 uint32_t _reserved1 :8; /*!< bit: 16..23 Reserved */ 254 uint32_t T :1; /*!< bit: 24 Thumb bit */ 255 uint32_t ICI_IT_2 :2; /*!< bit: 25..26 ICI/IT part 2 */ 256 uint32_t Q :1; /*!< bit: 27 Saturation condition flag */ 257 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 258 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 259 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 260 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 261 } b; /*!< Structure used for bit access */ 262 uint32_t w; /*!< Type used for word access */ 263 } xPSR_Type; 264 265 /* xPSR Register Definitions */ 266 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 267 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 268 269 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 270 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 271 272 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 273 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 274 275 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 276 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 277 278 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 279 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 280 281 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 282 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 283 284 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 285 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 286 287 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 288 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 289 290 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 291 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 292 293 /** 294 \brief Union type to access the Control Registers (CONTROL). 295 */ 296 typedef union { 297 struct { 298 uint32_t nPRIV :1; /*!< bit: 0 Execution privilege in Thread mode */ 299 uint32_t SPSEL :1; /*!< bit: 1 Stack to be used */ 300 uint32_t _reserved1 :30; /*!< bit: 2..31 Reserved */ 301 } b; /*!< Structure used for bit access */ 302 uint32_t w; /*!< Type used for word access */ 303 } CONTROL_Type; 304 305 /* CONTROL Register Definitions */ 306 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 307 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 308 309 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 310 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 311 312 /*@} end of group CMSIS_CORE */ 313 314 /** 315 \ingroup CMSIS_core_register 316 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 317 \brief Type definitions for the NVIC Registers 318 @{ 319 */ 320 321 /** 322 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 323 */ 324 typedef struct { 325 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 326 uint32_t RESERVED0[24U]; 327 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 328 uint32_t RSERVED1[24U]; 329 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 330 uint32_t RESERVED2[24U]; 331 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 332 uint32_t RESERVED3[24U]; 333 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 334 uint32_t RESERVED4[56U]; 335 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 336 uint32_t RESERVED5[644U]; 337 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 338 } NVIC_Type; 339 340 /* Software Triggered Interrupt Register Definitions */ 341 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 342 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 343 344 /*@} end of group CMSIS_NVIC */ 345 346 /** 347 \ingroup CMSIS_core_register 348 \defgroup CMSIS_SCB System Control Block (SCB) 349 \brief Type definitions for the System Control Block Registers 350 @{ 351 */ 352 353 /** 354 \brief Structure type to access the System Control Block (SCB). 355 */ 356 typedef struct { 357 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 358 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 359 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 360 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 361 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 362 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 363 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 364 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 365 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 366 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 367 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 368 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 369 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 370 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 371 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 372 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 373 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 374 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 375 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 376 uint32_t RESERVED0[5U]; 377 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 378 } SCB_Type; 379 380 /* SCB CPUID Register Definitions */ 381 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 382 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 383 384 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 385 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 386 387 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 388 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 389 390 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 391 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 392 393 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 394 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 395 396 /* SCB Interrupt Control State Register Definitions */ 397 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 398 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 399 400 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 401 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 402 403 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 404 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 405 406 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 407 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 408 409 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 410 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 411 412 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 413 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 414 415 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 416 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 417 418 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 419 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 420 421 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 422 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 423 424 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 425 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 426 427 /* SCB Vector Table Offset Register Definitions */ 428 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ 429 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ 430 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ 431 432 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 433 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 434 #else 435 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 436 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 437 #endif 438 439 /* SCB Application Interrupt and Reset Control Register Definitions */ 440 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 441 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 442 443 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 444 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 445 446 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 447 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 448 449 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 450 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 451 452 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 453 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 454 455 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 456 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 457 458 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 459 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 460 461 /* SCB System Control Register Definitions */ 462 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 463 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 464 465 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 466 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 467 468 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 469 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 470 471 /* SCB Configuration Control Register Definitions */ 472 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 473 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 474 475 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 476 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 477 478 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 479 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 480 481 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 482 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 483 484 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 485 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 486 487 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 488 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 489 490 /* SCB System Handler Control and State Register Definitions */ 491 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 492 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 493 494 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 495 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 496 497 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 498 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 499 500 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 501 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 502 503 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 504 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 505 506 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 507 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 508 509 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 510 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 511 512 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 513 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 514 515 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 516 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 517 518 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 519 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 520 521 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 522 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 523 524 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 525 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 526 527 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 528 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 529 530 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 531 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 532 533 /* SCB Configurable Fault Status Register Definitions */ 534 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 535 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 536 537 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 538 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 539 540 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 541 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 542 543 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 544 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 545 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 546 547 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 548 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 549 550 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 551 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 552 553 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 554 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 555 556 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 557 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 558 559 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 560 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 561 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 562 563 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 564 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 565 566 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 567 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 568 569 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 570 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 571 572 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 573 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 574 575 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 576 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 577 578 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 579 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 580 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 581 582 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 583 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 584 585 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 586 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 587 588 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 589 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 590 591 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 592 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 593 594 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 595 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 596 597 /* SCB Hard Fault Status Register Definitions */ 598 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 599 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 600 601 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 602 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 603 604 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 605 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 606 607 /* SCB Debug Fault Status Register Definitions */ 608 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 609 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 610 611 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 612 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 613 614 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 615 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 616 617 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 618 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 619 620 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 621 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 622 623 /*@} end of group CMSIS_SCB */ 624 625 /** 626 \ingroup CMSIS_core_register 627 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 628 \brief Type definitions for the System Control and ID Register not in the SCB 629 @{ 630 */ 631 632 /** 633 \brief Structure type to access the System Control and ID Register not in the SCB. 634 */ 635 typedef struct { 636 uint32_t RESERVED0[1U]; 637 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 638 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) 639 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 640 #else 641 uint32_t RESERVED1[1U]; 642 #endif 643 } SCnSCB_Type; 644 645 /* Interrupt Controller Type Register Definitions */ 646 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 647 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 648 649 /* Auxiliary Control Register Definitions */ 650 651 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 652 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 653 654 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ 655 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 656 657 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 658 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 659 660 /*@} end of group CMSIS_SCnotSCB */ 661 662 /** 663 \ingroup CMSIS_core_register 664 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 665 \brief Type definitions for the System Timer Registers. 666 @{ 667 */ 668 669 /** 670 \brief Structure type to access the System Timer (SysTick). 671 */ 672 typedef struct { 673 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 674 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 675 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 676 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 677 } SysTick_Type; 678 679 /* SysTick Control / Status Register Definitions */ 680 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 681 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 682 683 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 684 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 685 686 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 687 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 688 689 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 690 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 691 692 /* SysTick Reload Register Definitions */ 693 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 694 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 695 696 /* SysTick Current Register Definitions */ 697 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 698 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 699 700 /* SysTick Calibration Register Definitions */ 701 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 702 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 703 704 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 705 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 706 707 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 708 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 709 710 /*@} end of group CMSIS_SysTick */ 711 712 /** 713 \ingroup CMSIS_core_register 714 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 715 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 716 @{ 717 */ 718 719 /** 720 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 721 */ 722 typedef struct { 723 __OM union 724 { 725 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 726 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 727 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 728 } PORT[32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 729 uint32_t RESERVED0[864U]; 730 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 731 uint32_t RESERVED1[15U]; 732 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 733 uint32_t RESERVED2[15U]; 734 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 735 uint32_t RESERVED3[29U]; 736 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 737 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 738 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 739 uint32_t RESERVED4[43U]; 740 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 741 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 742 uint32_t RESERVED5[6U]; 743 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 744 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 745 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 746 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 747 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 748 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 749 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 750 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 751 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 752 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 753 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 754 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 755 } ITM_Type; 756 757 /* ITM Trace Privilege Register Definitions */ 758 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 759 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 760 761 /* ITM Trace Control Register Definitions */ 762 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 763 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 764 765 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 766 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 767 768 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 769 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 770 771 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 772 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 773 774 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 775 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 776 777 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 778 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 779 780 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 781 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 782 783 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 784 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 785 786 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 787 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 788 789 /* ITM Integration Write Register Definitions */ 790 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 791 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 792 793 /* ITM Integration Read Register Definitions */ 794 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 795 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 796 797 /* ITM Integration Mode Control Register Definitions */ 798 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 799 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 800 801 /* ITM Lock Status Register Definitions */ 802 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 803 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 804 805 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 806 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 807 808 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 809 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 810 811 /*@}*//* end of group CMSIS_ITM */ 812 813 /** 814 \ingroup CMSIS_core_register 815 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 816 \brief Type definitions for the Data Watchpoint and Trace (DWT) 817 @{ 818 */ 819 820 /** 821 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 822 */ 823 typedef struct { 824 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 825 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 826 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 827 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 828 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 829 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 830 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 831 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 832 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 833 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 834 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 835 uint32_t RESERVED0[1U]; 836 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 837 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 838 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 839 uint32_t RESERVED1[1U]; 840 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 841 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 842 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 843 uint32_t RESERVED2[1U]; 844 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 845 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 846 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 847 } DWT_Type; 848 849 /* DWT Control Register Definitions */ 850 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 851 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 852 853 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 854 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 855 856 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 857 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 858 859 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 860 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 861 862 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 863 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 864 865 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 866 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 867 868 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 869 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 870 871 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 872 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 873 874 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 875 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 876 877 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 878 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 879 880 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 881 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 882 883 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 884 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 885 886 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 887 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 888 889 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 890 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 891 892 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 893 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 894 895 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 896 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 897 898 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 899 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 900 901 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 902 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 903 904 /* DWT CPI Count Register Definitions */ 905 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 906 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 907 908 /* DWT Exception Overhead Count Register Definitions */ 909 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 910 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 911 912 /* DWT Sleep Count Register Definitions */ 913 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 914 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 915 916 /* DWT LSU Count Register Definitions */ 917 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 918 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 919 920 /* DWT Folded-instruction Count Register Definitions */ 921 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 922 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 923 924 /* DWT Comparator Mask Register Definitions */ 925 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 926 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 927 928 /* DWT Comparator Function Register Definitions */ 929 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 930 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 931 932 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 933 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 934 935 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 936 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 937 938 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 939 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 940 941 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 942 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 943 944 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 945 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 946 947 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 948 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 949 950 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 951 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 952 953 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 954 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 955 956 /*@}*//* end of group CMSIS_DWT */ 957 958 /** 959 \ingroup CMSIS_core_register 960 \defgroup CMSIS_TPI Trace Port Interface (TPI) 961 \brief Type definitions for the Trace Port Interface (TPI) 962 @{ 963 */ 964 965 /** 966 \brief Structure type to access the Trace Port Interface Register (TPI). 967 */ 968 typedef struct { 969 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 970 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 971 uint32_t RESERVED0[2U]; 972 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 973 uint32_t RESERVED1[55U]; 974 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 975 uint32_t RESERVED2[131U]; 976 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 977 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 978 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 979 uint32_t RESERVED3[759U]; 980 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 981 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 982 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 983 uint32_t RESERVED4[1U]; 984 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 985 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 986 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 987 uint32_t RESERVED5[39U]; 988 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 989 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 990 uint32_t RESERVED7[8U]; 991 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 992 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 993 } TPI_Type; 994 995 /* TPI Asynchronous Clock Prescaler Register Definitions */ 996 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 997 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 998 999 /* TPI Selected Pin Protocol Register Definitions */ 1000 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 1001 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 1002 1003 /* TPI Formatter and Flush Status Register Definitions */ 1004 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 1005 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 1006 1007 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 1008 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 1009 1010 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 1011 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 1012 1013 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 1014 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 1015 1016 /* TPI Formatter and Flush Control Register Definitions */ 1017 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 1018 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 1019 1020 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 1021 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 1022 1023 /* TPI TRIGGER Register Definitions */ 1024 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 1025 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 1026 1027 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 1028 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 1029 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 1030 1031 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 1032 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 1033 1034 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 1035 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 1036 1037 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 1038 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 1039 1040 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 1041 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 1042 1043 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 1044 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 1045 1046 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 1047 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 1048 1049 /* TPI ITATBCTR2 Register Definitions */ 1050 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ 1051 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ 1052 1053 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ 1054 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ 1055 1056 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 1057 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 1058 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 1059 1060 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 1061 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 1062 1063 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 1064 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 1065 1066 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 1067 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 1068 1069 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 1070 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 1071 1072 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 1073 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 1074 1075 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 1076 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 1077 1078 /* TPI ITATBCTR0 Register Definitions */ 1079 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ 1080 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ 1081 1082 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ 1083 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ 1084 1085 /* TPI Integration Mode Control Register Definitions */ 1086 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 1087 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 1088 1089 /* TPI DEVID Register Definitions */ 1090 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 1091 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 1092 1093 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 1094 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 1095 1096 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 1097 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 1098 1099 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 1100 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 1101 1102 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 1103 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 1104 1105 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 1106 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 1107 1108 /* TPI DEVTYPE Register Definitions */ 1109 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 1110 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 1111 1112 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 1113 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 1114 1115 /*@}*//* end of group CMSIS_TPI */ 1116 1117 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1118 /** 1119 \ingroup CMSIS_core_register 1120 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 1121 \brief Type definitions for the Memory Protection Unit (MPU) 1122 @{ 1123 */ 1124 1125 /** 1126 \brief Structure type to access the Memory Protection Unit (MPU). 1127 */ 1128 typedef struct 1129 { 1130 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 1131 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 1132 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 1133 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 1134 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 1135 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 1136 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 1137 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 1138 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 1139 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 1140 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 1141 } MPU_Type; 1142 1143 #define MPU_TYPE_RALIASES 4U 1144 1145 /* MPU Type Register Definitions */ 1146 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 1147 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 1148 1149 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 1150 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 1151 1152 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 1153 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 1154 1155 /* MPU Control Register Definitions */ 1156 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 1157 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 1158 1159 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 1160 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 1161 1162 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 1163 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 1164 1165 /* MPU Region Number Register Definitions */ 1166 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 1167 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 1168 1169 /* MPU Region Base Address Register Definitions */ 1170 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1171 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1172 1173 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1174 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1175 1176 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1177 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 1178 1179 /* MPU Region Attribute and Size Register Definitions */ 1180 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 1181 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 1182 1183 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 1184 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 1185 1186 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 1187 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 1188 1189 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 1190 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 1191 1192 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 1193 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 1194 1195 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 1196 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 1197 1198 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 1199 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 1200 1201 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 1202 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 1203 1204 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 1205 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 1206 1207 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 1208 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 1209 1210 /*@} end of group CMSIS_MPU */ 1211 #endif 1212 1213 /** 1214 \ingroup CMSIS_core_register 1215 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1216 \brief Type definitions for the Core Debug Registers 1217 @{ 1218 */ 1219 1220 /** 1221 \brief Structure type to access the Core Debug Register (CoreDebug). 1222 */ 1223 typedef struct { 1224 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1225 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1226 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1227 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1228 } CoreDebug_Type; 1229 1230 /* Debug Halting Control and Status Register Definitions */ 1231 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 1232 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1233 1234 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1235 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1236 1237 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1238 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1239 1240 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1241 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1242 1243 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 1244 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1245 1246 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 1247 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1248 1249 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 1250 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1251 1252 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 1253 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 1254 1255 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1256 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1257 1258 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 1259 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1260 1261 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 1262 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1263 1264 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1265 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1266 1267 /* Debug Core Register Selector Register Definitions */ 1268 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 1269 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1270 1271 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 1272 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 1273 1274 /* Debug Exception and Monitor Control Register Definitions */ 1275 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 1276 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 1277 1278 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 1279 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 1280 1281 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 1282 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 1283 1284 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 1285 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 1286 1287 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 1288 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 1289 1290 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1291 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1292 1293 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 1294 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 1295 1296 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 1297 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 1298 1299 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 1300 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 1301 1302 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 1303 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 1304 1305 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 1306 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 1307 1308 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 1309 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 1310 1311 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1312 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1313 1314 /*@} end of group CMSIS_CoreDebug */ 1315 1316 /** 1317 \ingroup CMSIS_core_register 1318 \defgroup CMSIS_core_bitfield Core register bit field macros 1319 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1320 @{ 1321 */ 1322 1323 /** 1324 \brief Mask and shift a bit field value for use in a register bit range. 1325 \param[in] field Name of the register bit field. 1326 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1327 \return Masked and shifted value. 1328 */ 1329 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1330 1331 /** 1332 \brief Mask and shift a register value to extract a bit filed value. 1333 \param[in] field Name of the register bit field. 1334 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1335 \return Masked and shifted bit field value. 1336 */ 1337 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1338 1339 /*@} end of group CMSIS_core_bitfield */ 1340 1341 /** 1342 \ingroup CMSIS_core_register 1343 \defgroup CMSIS_core_base Core Definitions 1344 \brief Definitions for base addresses, unions, and structures. 1345 @{ 1346 */ 1347 1348 /* Memory mapping of Core Hardware */ 1349 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1350 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 1351 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1352 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1353 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1354 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1355 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1356 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1357 1358 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 1359 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1360 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1361 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1362 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 1363 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1364 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1365 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 1366 1367 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1368 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1369 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1370 #endif 1371 1372 /*@} */ 1373 1374 /******************************************************************************* 1375 * Hardware Abstraction Layer 1376 Core Function Interface contains: 1377 - Core NVIC Functions 1378 - Core SysTick Functions 1379 - Core Debug Functions 1380 - Core Register Access Functions 1381 ******************************************************************************/ 1382 /** 1383 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1384 */ 1385 1386 /* ########################## NVIC functions #################################### */ 1387 /** 1388 \ingroup CMSIS_Core_FunctionInterface 1389 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1390 \brief Functions that manage interrupts and exceptions via the NVIC. 1391 @{ 1392 */ 1393 1394 #ifdef CMSIS_NVIC_VIRTUAL 1395 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1396 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1397 #endif 1398 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1399 #else 1400 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 1401 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 1402 #define NVIC_EnableIRQ __NVIC_EnableIRQ 1403 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1404 #define NVIC_DisableIRQ __NVIC_DisableIRQ 1405 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1406 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1407 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1408 #define NVIC_GetActive __NVIC_GetActive 1409 #define NVIC_SetPriority __NVIC_SetPriority 1410 #define NVIC_GetPriority __NVIC_GetPriority 1411 #define NVIC_SystemReset __NVIC_SystemReset 1412 #endif /* CMSIS_NVIC_VIRTUAL */ 1413 1414 #ifdef CMSIS_VECTAB_VIRTUAL 1415 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1416 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1417 #endif 1418 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1419 #else 1420 #define NVIC_SetVector __NVIC_SetVector 1421 #define NVIC_GetVector __NVIC_GetVector 1422 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1423 1424 #define NVIC_USER_IRQ_OFFSET 16 1425 1426 /* The following EXC_RETURN values are saved the LR on exception entry */ 1427 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 1428 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 1429 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 1430 1431 /** 1432 \brief Set Priority Grouping 1433 \details Sets the priority grouping field using the required unlock sequence. 1434 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 1435 Only values from 0..7 are used. 1436 In case of a conflict between priority grouping and available 1437 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1438 \param [in] PriorityGroup Priority grouping field. 1439 */ 1440 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 1441 { 1442 uint32_t reg_value; 1443 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1444 1445 reg_value = SCB->AIRCR; /* read old register configuration */ 1446 reg_value &= ~((uint32_t) (SCB_AIRCR_VECTKEY_Msk 1447 | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 1448 reg_value = (reg_value | ((uint32_t) 0x5FAUL << SCB_AIRCR_VECTKEY_Pos) 1449 | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */ 1450 SCB->AIRCR = reg_value; 1451 } 1452 1453 /** 1454 \brief Get Priority Grouping 1455 \details Reads the priority grouping field from the NVIC Interrupt Controller. 1456 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 1457 */ 1458 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 1459 { 1460 return ((uint32_t) ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) 1461 >> SCB_AIRCR_PRIGROUP_Pos)); 1462 } 1463 1464 /** 1465 \brief Enable Interrupt 1466 \details Enables a device specific interrupt in the NVIC interrupt controller. 1467 \param [in] IRQn Device specific interrupt number. 1468 \note IRQn must not be negative. 1469 */ 1470 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1471 { 1472 if ((int32_t) (IRQn) >= 0) { 1473 NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1474 << (((uint32_t) IRQn) & 0x1FUL)); 1475 } 1476 } 1477 1478 /** 1479 \brief Get Interrupt Enable status 1480 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1481 \param [in] IRQn Device specific interrupt number. 1482 \return 0 Interrupt is not enabled. 1483 \return 1 Interrupt is enabled. 1484 \note IRQn must not be negative. 1485 */ 1486 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1487 { 1488 if ((int32_t) (IRQn) >= 0) { 1489 return ((uint32_t) ( 1490 ((NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] 1491 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1492 1UL : 0UL)); 1493 } else { 1494 return (0U); 1495 } 1496 } 1497 1498 /** 1499 \brief Disable Interrupt 1500 \details Disables a device specific interrupt in the NVIC interrupt controller. 1501 \param [in] IRQn Device specific interrupt number. 1502 \note IRQn must not be negative. 1503 */ 1504 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1505 { 1506 if ((int32_t) (IRQn) >= 0) { 1507 NVIC->ICER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1508 << (((uint32_t) IRQn) & 0x1FUL)); 1509 __DSB(); 1510 __ISB(); 1511 } 1512 } 1513 1514 /** 1515 \brief Get Pending Interrupt 1516 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 1517 \param [in] IRQn Device specific interrupt number. 1518 \return 0 Interrupt status is not pending. 1519 \return 1 Interrupt status is pending. 1520 \note IRQn must not be negative. 1521 */ 1522 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1523 { 1524 if ((int32_t) (IRQn) >= 0) { 1525 return ((uint32_t) ( 1526 ((NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] 1527 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1528 1UL : 0UL)); 1529 } else { 1530 return (0U); 1531 } 1532 } 1533 1534 /** 1535 \brief Set Pending Interrupt 1536 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1537 \param [in] IRQn Device specific interrupt number. 1538 \note IRQn must not be negative. 1539 */ 1540 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1541 { 1542 if ((int32_t) (IRQn) >= 0) { 1543 NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1544 << (((uint32_t) IRQn) & 0x1FUL)); 1545 } 1546 } 1547 1548 /** 1549 \brief Clear Pending Interrupt 1550 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1551 \param [in] IRQn Device specific interrupt number. 1552 \note IRQn must not be negative. 1553 */ 1554 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1555 { 1556 if ((int32_t) (IRQn) >= 0) { 1557 NVIC->ICPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1558 << (((uint32_t) IRQn) & 0x1FUL)); 1559 } 1560 } 1561 1562 /** 1563 \brief Get Active Interrupt 1564 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 1565 \param [in] IRQn Device specific interrupt number. 1566 \return 0 Interrupt status is not active. 1567 \return 1 Interrupt status is active. 1568 \note IRQn must not be negative. 1569 */ 1570 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1571 { 1572 if ((int32_t) (IRQn) >= 0) { 1573 return ((uint32_t) ( 1574 ((NVIC->IABR[(((uint32_t) IRQn) >> 5UL)] 1575 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1576 1UL : 0UL)); 1577 } else { 1578 return (0U); 1579 } 1580 } 1581 1582 /** 1583 \brief Set Interrupt Priority 1584 \details Sets the priority of a device specific interrupt or a processor exception. 1585 The interrupt number can be positive to specify a device specific interrupt, 1586 or negative to specify a processor exception. 1587 \param [in] IRQn Interrupt number. 1588 \param [in] priority Priority to set. 1589 \note The priority cannot be set for every processor exception. 1590 */ 1591 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1592 { 1593 if ((int32_t) (IRQn) >= 0) { 1594 NVIC->IP[((uint32_t) IRQn)] = (uint8_t) ((priority 1595 << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL); 1596 } else { 1597 SCB->SHP[(((uint32_t) IRQn) & 0xFUL) - 4UL] = (uint8_t) ((priority 1598 << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL); 1599 } 1600 } 1601 1602 /** 1603 \brief Get Interrupt Priority 1604 \details Reads the priority of a device specific interrupt or a processor exception. 1605 The interrupt number can be positive to specify a device specific interrupt, 1606 or negative to specify a processor exception. 1607 \param [in] IRQn Interrupt number. 1608 \return Interrupt Priority. 1609 Value is aligned automatically to the implemented priority bits of the microcontroller. 1610 */ 1611 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1612 { 1613 1614 if ((int32_t) (IRQn) >= 0) { 1615 return (((uint32_t) NVIC->IP[((uint32_t) IRQn)] 1616 >> (8U - __NVIC_PRIO_BITS))); 1617 } else { 1618 return (((uint32_t) SCB->SHP[(((uint32_t) IRQn) & 0xFUL) - 4UL] 1619 >> (8U - __NVIC_PRIO_BITS))); 1620 } 1621 } 1622 1623 /** 1624 \brief Encode Priority 1625 \details Encodes the priority for an interrupt with the given priority group, 1626 preemptive priority value, and subpriority value. 1627 In case of a conflict between priority grouping and available 1628 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1629 \param [in] PriorityGroup Used priority group. 1630 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1631 \param [in] SubPriority Subpriority value (starting from 0). 1632 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1633 */ 1634 __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, 1635 uint32_t PreemptPriority, uint32_t SubPriority) 1636 { 1637 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1638 uint32_t PreemptPriorityBits; 1639 uint32_t SubPriorityBits; 1640 1641 PreemptPriorityBits = 1642 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 1643 (uint32_t) (__NVIC_PRIO_BITS) : 1644 (uint32_t) (7UL - PriorityGroupTmp); 1645 SubPriorityBits = 1646 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) 1647 < (uint32_t) 7UL) ? 1648 (uint32_t) 0UL : 1649 (uint32_t) ((PriorityGroupTmp - 7UL) 1650 + (uint32_t) (__NVIC_PRIO_BITS)); 1651 1652 return (((PreemptPriority 1653 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL)) 1654 << SubPriorityBits) 1655 | ((SubPriority & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL)))); 1656 } 1657 1658 /** 1659 \brief Decode Priority 1660 \details Decodes an interrupt priority value with a given priority group to 1661 preemptive priority value and subpriority value. 1662 In case of a conflict between priority grouping and available 1663 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1664 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1665 \param [in] PriorityGroup Used priority group. 1666 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1667 \param [out] pSubPriority Subpriority value (starting from 0). 1668 */ 1669 __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, 1670 uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 1671 uint32_t *const pSubPriority) 1672 { 1673 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1674 uint32_t PreemptPriorityBits; 1675 uint32_t SubPriorityBits; 1676 1677 PreemptPriorityBits = 1678 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 1679 (uint32_t) (__NVIC_PRIO_BITS) : 1680 (uint32_t) (7UL - PriorityGroupTmp); 1681 SubPriorityBits = 1682 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) 1683 < (uint32_t) 7UL) ? 1684 (uint32_t) 0UL : 1685 (uint32_t) ((PriorityGroupTmp - 7UL) 1686 + (uint32_t) (__NVIC_PRIO_BITS)); 1687 1688 *pPreemptPriority = (Priority >> SubPriorityBits) 1689 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL); 1690 *pSubPriority = (Priority) 1691 & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL); 1692 } 1693 1694 /** 1695 \brief Set Interrupt Vector 1696 \details Sets an interrupt vector in SRAM based interrupt vector table. 1697 The interrupt number can be positive to specify a device specific interrupt, 1698 or negative to specify a processor exception. 1699 VTOR must been relocated to SRAM before. 1700 \param [in] IRQn Interrupt number 1701 \param [in] vector Address of interrupt handler function 1702 */ 1703 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 1704 { 1705 uint32_t *vectors = (uint32_t*) SCB->VTOR; 1706 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 1707 } 1708 1709 /** 1710 \brief Get Interrupt Vector 1711 \details Reads an interrupt vector from interrupt vector table. 1712 The interrupt number can be positive to specify a device specific interrupt, 1713 or negative to specify a processor exception. 1714 \param [in] IRQn Interrupt number. 1715 \return Address of interrupt handler function 1716 */ 1717 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 1718 { 1719 uint32_t *vectors = (uint32_t*) SCB->VTOR; 1720 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 1721 } 1722 1723 /** 1724 \brief System Reset 1725 \details Initiates a system reset request to reset the MCU. 1726 */ 1727 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 1728 { 1729 __DSB(); /* Ensure all outstanding memory accesses included 1730 buffered write are completed before reset */ 1731 SCB->AIRCR = (uint32_t) ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) 1732 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 1733 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 1734 __DSB(); /* Ensure completion of memory access */ 1735 1736 for (;;) /* wait until reset */ 1737 { 1738 __NOP(); 1739 } 1740 } 1741 1742 /*@} end of CMSIS_Core_NVICFunctions */ 1743 1744 /* ########################## MPU functions #################################### */ 1745 1746 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1747 1748 #include "mpu_armv7.h" 1749 1750 #endif 1751 1752 /* ########################## FPU functions #################################### */ 1753 /** 1754 \ingroup CMSIS_Core_FunctionInterface 1755 \defgroup CMSIS_Core_FpuFunctions FPU Functions 1756 \brief Function that provides FPU type. 1757 @{ 1758 */ 1759 1760 /** 1761 \brief get FPU type 1762 \details returns the FPU type 1763 \returns 1764 - \b 0: No FPU 1765 - \b 1: Single precision FPU 1766 - \b 2: Double + Single precision FPU 1767 */ 1768 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 1769 { 1770 return 0U; /* No FPU */ 1771 } 1772 1773 /*@} end of CMSIS_Core_FpuFunctions */ 1774 1775 /* ################################## SysTick function ############################################ */ 1776 /** 1777 \ingroup CMSIS_Core_FunctionInterface 1778 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 1779 \brief Functions that configure the System. 1780 @{ 1781 */ 1782 1783 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 1784 1785 /** 1786 \brief System Tick Configuration 1787 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 1788 Counter is in free running mode to generate periodic interrupts. 1789 \param [in] ticks Number of ticks between two interrupts. 1790 \return 0 Function succeeded. 1791 \return 1 Function failed. 1792 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1793 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 1794 must contain a vendor-specific implementation of this function. 1795 */ 1796 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 1797 { 1798 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1799 { 1800 return (1UL); /* Reload value impossible */ 1801 } 1802 1803 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1804 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1805 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 1806 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1807 SysTick_CTRL_TICKINT_Msk | 1808 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1809 return (0UL); /* Function successful */ 1810 } 1811 1812 #endif 1813 1814 /*@} end of CMSIS_Core_SysTickFunctions */ 1815 1816 /* ##################################### Debug In/Output function ########################################### */ 1817 /** 1818 \ingroup CMSIS_Core_FunctionInterface 1819 \defgroup CMSIS_core_DebugFunctions ITM Functions 1820 \brief Functions that access the ITM debug interface. 1821 @{ 1822 */ 1823 1824 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 1825 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 1826 1827 /** 1828 \brief ITM Send Character 1829 \details Transmits a character via the ITM channel 0, and 1830 \li Just returns when no debugger is connected that has booked the output. 1831 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 1832 \param [in] ch Character to transmit. 1833 \returns Character to transmit. 1834 */ 1835 __STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) 1836 { 1837 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 1838 ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ 1839 { 1840 while (ITM->PORT[0U].u32 == 0UL) { 1841 __NOP(); 1842 } 1843 ITM->PORT[0U].u8 = (uint8_t) ch; 1844 } 1845 return (ch); 1846 } 1847 1848 /** 1849 \brief ITM Receive Character 1850 \details Inputs a character via the external variable \ref ITM_RxBuffer. 1851 \return Received character. 1852 \return -1 No character pending. 1853 */ 1854 __STATIC_INLINE int32_t ITM_ReceiveChar(void) 1855 { 1856 int32_t ch = -1; /* no character available */ 1857 1858 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 1859 ch = ITM_RxBuffer; 1860 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 1861 } 1862 1863 return (ch); 1864 } 1865 1866 /** 1867 \brief ITM Check Character 1868 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 1869 \return 0 No character available. 1870 \return 1 Character available. 1871 */ 1872 __STATIC_INLINE int32_t ITM_CheckChar(void) 1873 { 1874 1875 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 1876 return (0); /* no character available */ 1877 } else { 1878 return (1); /* character available */ 1879 } 1880 } 1881 1882 /*@} end of CMSIS_core_DebugFunctions */ 1883 1884 #ifdef __cplusplus 1885 } 1886 #endif 1887 1888 #endif /* __CORE_CM3_H_DEPENDANT */ 1889 1890 #endif /* __CMSIS_GENERIC */