Drivers/CMSIS/Include/core_cm23.h (101685B)
1 /**************************************************************************//** 2 * @file core_cm23.h 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File 4 * @version V5.0.7 5 * @date 22. June 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_CM23_H_GENERIC 32 #define __CORE_CM23_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup Cortex_M23 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS definitions */ 65 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ 68 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_M (23U) /*!< Cortex-M Core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 This core does not support an FPU at all 74 */ 75 #define __FPU_USED 0U 76 77 #if defined ( __CC_ARM ) 78 #if defined __TARGET_FPU_VFP 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 80 #endif 81 82 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 83 #if defined __ARM_PCS_VFP 84 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 85 #endif 86 87 #elif defined ( __GNUC__ ) 88 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 90 #endif 91 92 #elif defined ( __ICCARM__ ) 93 #if defined __ARMVFP__ 94 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 95 #endif 96 97 #elif defined ( __TI_ARM__ ) 98 #if defined __TI_VFP_SUPPORT__ 99 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 100 #endif 101 102 #elif defined ( __TASKING__ ) 103 #if defined __FPU_VFP__ 104 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 105 #endif 106 107 #elif defined ( __CSMC__ ) 108 #if ( __CSMC__ & 0x400U) 109 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 110 #endif 111 112 #endif 113 114 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 115 116 #ifdef __cplusplus 117 } 118 #endif 119 120 #endif /* __CORE_CM23_H_GENERIC */ 121 122 #ifndef __CMSIS_GENERIC 123 124 #ifndef __CORE_CM23_H_DEPENDANT 125 #define __CORE_CM23_H_DEPENDANT 126 127 #ifdef __cplusplus 128 extern "C" { 129 #endif 130 131 /* check device defines and use defaults */ 132 #if defined __CHECK_DEVICE_DEFINES 133 #ifndef __CM23_REV 134 #define __CM23_REV 0x0000U 135 #warning "__CM23_REV not defined in device header file; using default!" 136 #endif 137 138 #ifndef __FPU_PRESENT 139 #define __FPU_PRESENT 0U 140 #warning "__FPU_PRESENT not defined in device header file; using default!" 141 #endif 142 143 #ifndef __MPU_PRESENT 144 #define __MPU_PRESENT 0U 145 #warning "__MPU_PRESENT not defined in device header file; using default!" 146 #endif 147 148 #ifndef __SAUREGION_PRESENT 149 #define __SAUREGION_PRESENT 0U 150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!" 151 #endif 152 153 #ifndef __VTOR_PRESENT 154 #define __VTOR_PRESENT 0U 155 #warning "__VTOR_PRESENT not defined in device header file; using default!" 156 #endif 157 158 #ifndef __NVIC_PRIO_BITS 159 #define __NVIC_PRIO_BITS 2U 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 161 #endif 162 163 #ifndef __Vendor_SysTickConfig 164 #define __Vendor_SysTickConfig 0U 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 166 #endif 167 168 #ifndef __ETM_PRESENT 169 #define __ETM_PRESENT 0U 170 #warning "__ETM_PRESENT not defined in device header file; using default!" 171 #endif 172 173 #ifndef __MTB_PRESENT 174 #define __MTB_PRESENT 0U 175 #warning "__MTB_PRESENT not defined in device header file; using default!" 176 #endif 177 178 #endif 179 180 /* IO definitions (access restrictions to peripheral registers) */ 181 /** 182 \defgroup CMSIS_glob_defs CMSIS Global Defines 183 184 <strong>IO Type Qualifiers</strong> are used 185 \li to specify the access to peripheral variables. 186 \li for automatic generation of peripheral register debug information. 187 */ 188 #ifdef __cplusplus 189 #define __I volatile /*!< Defines 'read only' permissions */ 190 #else 191 #define __I volatile const /*!< Defines 'read only' permissions */ 192 #endif 193 #define __O volatile /*!< Defines 'write only' permissions */ 194 #define __IO volatile /*!< Defines 'read / write' permissions */ 195 196 /* following defines should be used for structure members */ 197 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 198 #define __OM volatile /*! Defines 'write only' structure member permissions */ 199 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 200 201 /*@} end of group Cortex_M23 */ 202 203 /******************************************************************************* 204 * Register Abstraction 205 Core Register contain: 206 - Core Register 207 - Core NVIC Register 208 - Core SCB Register 209 - Core SysTick Register 210 - Core Debug Register 211 - Core MPU Register 212 - Core SAU Register 213 ******************************************************************************/ 214 /** 215 \defgroup CMSIS_core_register Defines and Type Definitions 216 \brief Type definitions and defines for Cortex-M processor based devices. 217 */ 218 219 /** 220 \ingroup CMSIS_core_register 221 \defgroup CMSIS_CORE Status and Control Registers 222 \brief Core Register type definitions. 223 @{ 224 */ 225 226 /** 227 \brief Union type to access the Application Program Status Register (APSR). 228 */ 229 typedef union { 230 struct { 231 uint32_t _reserved0 :28; /*!< bit: 0..27 Reserved */ 232 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 233 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 234 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 235 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 236 } b; /*!< Structure used for bit access */ 237 uint32_t w; /*!< Type used for word access */ 238 } APSR_Type; 239 240 /* APSR Register Definitions */ 241 #define APSR_N_Pos 31U /*!< APSR: N Position */ 242 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 243 244 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 245 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 246 247 #define APSR_C_Pos 29U /*!< APSR: C Position */ 248 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 249 250 #define APSR_V_Pos 28U /*!< APSR: V Position */ 251 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 252 253 /** 254 \brief Union type to access the Interrupt Program Status Register (IPSR). 255 */ 256 typedef union { 257 struct { 258 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 259 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 260 } b; /*!< Structure used for bit access */ 261 uint32_t w; /*!< Type used for word access */ 262 } IPSR_Type; 263 264 /* IPSR Register Definitions */ 265 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 266 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 267 268 /** 269 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 270 */ 271 typedef union { 272 struct { 273 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 274 uint32_t _reserved0 :15; /*!< bit: 9..23 Reserved */ 275 uint32_t T :1; /*!< bit: 24 Thumb bit (read 0) */ 276 uint32_t _reserved1 :3; /*!< bit: 25..27 Reserved */ 277 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 278 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 279 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 280 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 281 } b; /*!< Structure used for bit access */ 282 uint32_t w; /*!< Type used for word access */ 283 } xPSR_Type; 284 285 /* xPSR Register Definitions */ 286 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 287 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 288 289 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 290 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 291 292 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 293 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 294 295 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 296 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 297 298 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 299 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 300 301 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 302 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 303 304 /** 305 \brief Union type to access the Control Registers (CONTROL). 306 */ 307 typedef union { 308 struct { 309 uint32_t nPRIV :1; /*!< bit: 0 Execution privilege in Thread mode */ 310 uint32_t SPSEL :1; /*!< bit: 1 Stack-pointer select */ 311 uint32_t _reserved1 :30; /*!< bit: 2..31 Reserved */ 312 } b; /*!< Structure used for bit access */ 313 uint32_t w; /*!< Type used for word access */ 314 } CONTROL_Type; 315 316 /* CONTROL Register Definitions */ 317 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 318 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 319 320 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 321 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 322 323 /*@} end of group CMSIS_CORE */ 324 325 /** 326 \ingroup CMSIS_core_register 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 328 \brief Type definitions for the NVIC Registers 329 @{ 330 */ 331 332 /** 333 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 334 */ 335 typedef struct { 336 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 337 uint32_t RESERVED0[16U]; 338 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 339 uint32_t RSERVED1[16U]; 340 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 341 uint32_t RESERVED2[16U]; 342 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 343 uint32_t RESERVED3[16U]; 344 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 345 uint32_t RESERVED4[16U]; 346 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ 347 uint32_t RESERVED5[16U]; 348 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 349 } NVIC_Type; 350 351 /*@} end of group CMSIS_NVIC */ 352 353 /** 354 \ingroup CMSIS_core_register 355 \defgroup CMSIS_SCB System Control Block (SCB) 356 \brief Type definitions for the System Control Block Registers 357 @{ 358 */ 359 360 /** 361 \brief Structure type to access the System Control Block (SCB). 362 */ 363 typedef struct { 364 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 365 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 366 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 367 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 368 #else 369 uint32_t RESERVED0; 370 #endif 371 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 372 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 373 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 374 uint32_t RESERVED1; 375 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 376 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 377 } SCB_Type; 378 379 /* SCB CPUID Register Definitions */ 380 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 381 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 382 383 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 384 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 385 386 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 387 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 388 389 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 390 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 391 392 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 393 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 394 395 /* SCB Interrupt Control State Register Definitions */ 396 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ 397 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ 398 399 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ 400 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ 401 402 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ 403 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ 404 405 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 406 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 407 408 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 409 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 410 411 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 412 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 413 414 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 415 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 416 417 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ 418 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ 419 420 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 421 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 422 423 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 424 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 425 426 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 427 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 428 429 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 430 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 431 432 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 433 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 434 435 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 436 /* SCB Vector Table Offset Register Definitions */ 437 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 438 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 439 #endif 440 441 /* SCB Application Interrupt and Reset Control Register Definitions */ 442 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 443 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 444 445 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 446 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 447 448 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 449 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 450 451 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ 452 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ 453 454 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ 455 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ 456 457 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ 458 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ 459 460 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 461 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 462 463 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 464 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 465 466 /* SCB System Control Register Definitions */ 467 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 469 470 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ 471 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ 472 473 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 474 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 475 476 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 477 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 478 479 /* SCB Configuration Control Register Definitions */ 480 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ 481 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ 482 483 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ 484 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ 485 486 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ 487 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ 488 489 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ 490 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ 491 492 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 493 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 494 495 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 496 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 497 498 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 499 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 500 501 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 502 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 503 504 /* SCB System Handler Control and State Register Definitions */ 505 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ 506 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ 507 508 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 509 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 510 511 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 512 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 513 514 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 515 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 516 517 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 518 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 519 520 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ 521 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ 522 523 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ 524 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ 525 526 /*@} end of group CMSIS_SCB */ 527 528 /** 529 \ingroup CMSIS_core_register 530 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 531 \brief Type definitions for the System Timer Registers. 532 @{ 533 */ 534 535 /** 536 \brief Structure type to access the System Timer (SysTick). 537 */ 538 typedef struct { 539 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 540 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 541 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 542 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 543 } SysTick_Type; 544 545 /* SysTick Control / Status Register Definitions */ 546 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 547 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 548 549 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 550 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 551 552 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 553 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 554 555 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 556 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 557 558 /* SysTick Reload Register Definitions */ 559 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 560 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 561 562 /* SysTick Current Register Definitions */ 563 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 564 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 565 566 /* SysTick Calibration Register Definitions */ 567 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 568 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 569 570 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 571 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 572 573 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 574 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 575 576 /*@} end of group CMSIS_SysTick */ 577 578 /** 579 \ingroup CMSIS_core_register 580 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 581 \brief Type definitions for the Data Watchpoint and Trace (DWT) 582 @{ 583 */ 584 585 /** 586 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 587 */ 588 typedef struct { 589 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 590 uint32_t RESERVED0[6U]; 591 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 592 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 593 uint32_t RESERVED1[1U]; 594 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 595 uint32_t RESERVED2[1U]; 596 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 597 uint32_t RESERVED3[1U]; 598 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 599 uint32_t RESERVED4[1U]; 600 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 601 uint32_t RESERVED5[1U]; 602 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 603 uint32_t RESERVED6[1U]; 604 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 605 uint32_t RESERVED7[1U]; 606 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 607 uint32_t RESERVED8[1U]; 608 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ 609 uint32_t RESERVED9[1U]; 610 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ 611 uint32_t RESERVED10[1U]; 612 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ 613 uint32_t RESERVED11[1U]; 614 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ 615 uint32_t RESERVED12[1U]; 616 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ 617 uint32_t RESERVED13[1U]; 618 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ 619 uint32_t RESERVED14[1U]; 620 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ 621 uint32_t RESERVED15[1U]; 622 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ 623 uint32_t RESERVED16[1U]; 624 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ 625 uint32_t RESERVED17[1U]; 626 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ 627 uint32_t RESERVED18[1U]; 628 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ 629 uint32_t RESERVED19[1U]; 630 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ 631 uint32_t RESERVED20[1U]; 632 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ 633 uint32_t RESERVED21[1U]; 634 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ 635 uint32_t RESERVED22[1U]; 636 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ 637 uint32_t RESERVED23[1U]; 638 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ 639 uint32_t RESERVED24[1U]; 640 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ 641 uint32_t RESERVED25[1U]; 642 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ 643 uint32_t RESERVED26[1U]; 644 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ 645 uint32_t RESERVED27[1U]; 646 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ 647 uint32_t RESERVED28[1U]; 648 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ 649 uint32_t RESERVED29[1U]; 650 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ 651 uint32_t RESERVED30[1U]; 652 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ 653 uint32_t RESERVED31[1U]; 654 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ 655 } DWT_Type; 656 657 /* DWT Control Register Definitions */ 658 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 659 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 660 661 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 662 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 663 664 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 665 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 666 667 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 668 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 669 670 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 671 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 672 673 /* DWT Comparator Function Register Definitions */ 674 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ 675 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ 676 677 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 678 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 679 680 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 681 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 682 683 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ 684 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ 685 686 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ 687 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ 688 689 /*@}*//* end of group CMSIS_DWT */ 690 691 /** 692 \ingroup CMSIS_core_register 693 \defgroup CMSIS_TPI Trace Port Interface (TPI) 694 \brief Type definitions for the Trace Port Interface (TPI) 695 @{ 696 */ 697 698 /** 699 \brief Structure type to access the Trace Port Interface Register (TPI). 700 */ 701 typedef struct { 702 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 703 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 704 uint32_t RESERVED0[2U]; 705 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 706 uint32_t RESERVED1[55U]; 707 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 708 uint32_t RESERVED2[131U]; 709 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 710 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 711 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ 712 uint32_t RESERVED3[759U]; 713 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 714 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ 715 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ 716 uint32_t RESERVED4[1U]; 717 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ 718 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ 719 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 720 uint32_t RESERVED5[39U]; 721 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 722 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 723 uint32_t RESERVED7[8U]; 724 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ 725 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ 726 } TPI_Type; 727 728 /* TPI Asynchronous Clock Prescaler Register Definitions */ 729 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 730 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 731 732 /* TPI Selected Pin Protocol Register Definitions */ 733 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 734 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 735 736 /* TPI Formatter and Flush Status Register Definitions */ 737 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 738 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 739 740 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 741 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 742 743 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 744 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 745 746 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 747 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 748 749 /* TPI Formatter and Flush Control Register Definitions */ 750 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 751 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 752 753 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ 754 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ 755 756 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 757 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 758 759 /* TPI TRIGGER Register Definitions */ 760 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 761 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 762 763 /* TPI Integration Test FIFO Test Data 0 Register Definitions */ 764 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ 765 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ 766 767 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ 768 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ 769 770 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ 771 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ 772 773 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ 774 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ 775 776 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ 777 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ 778 779 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ 780 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ 781 782 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ 783 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ 784 785 /* TPI Integration Test ATB Control Register 2 Register Definitions */ 786 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ 787 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ 788 789 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ 790 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ 791 792 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ 793 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ 794 795 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ 796 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ 797 798 /* TPI Integration Test FIFO Test Data 1 Register Definitions */ 799 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ 800 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ 801 802 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ 803 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ 804 805 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ 806 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ 807 808 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ 809 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ 810 811 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ 812 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ 813 814 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ 815 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ 816 817 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ 818 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ 819 820 /* TPI Integration Test ATB Control Register 0 Definitions */ 821 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ 822 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ 823 824 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ 825 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ 826 827 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ 828 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ 829 830 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ 831 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ 832 833 /* TPI Integration Mode Control Register Definitions */ 834 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 835 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 836 837 /* TPI DEVID Register Definitions */ 838 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 839 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 840 841 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 842 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 843 844 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 845 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 846 847 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ 848 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ 849 850 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 851 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 852 853 /* TPI DEVTYPE Register Definitions */ 854 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ 855 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 856 857 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ 858 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 859 860 /*@}*//* end of group CMSIS_TPI */ 861 862 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 863 /** 864 \ingroup CMSIS_core_register 865 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 866 \brief Type definitions for the Memory Protection Unit (MPU) 867 @{ 868 */ 869 870 /** 871 \brief Structure type to access the Memory Protection Unit (MPU). 872 */ 873 typedef struct 874 { 875 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 876 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 877 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ 878 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 879 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ 880 uint32_t RESERVED0[7U]; 881 union { 882 __IOM uint32_t MAIR[2]; 883 struct { 884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ 885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ 886 }; 887 }; 888 } MPU_Type; 889 890 #define MPU_TYPE_RALIASES 1U 891 892 /* MPU Type Register Definitions */ 893 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 894 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 895 896 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 897 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 898 899 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 900 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 901 902 /* MPU Control Register Definitions */ 903 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 904 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 905 906 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 907 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 908 909 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 910 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 911 912 /* MPU Region Number Register Definitions */ 913 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 914 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 915 916 /* MPU Region Base Address Register Definitions */ 917 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 918 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 919 920 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 921 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 922 923 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 924 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 925 926 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 927 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 928 929 /* MPU Region Limit Address Register Definitions */ 930 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ 931 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ 932 933 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ 934 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ 935 936 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ 937 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ 938 939 /* MPU Memory Attribute Indirection Register 0 Definitions */ 940 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ 941 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ 942 943 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ 944 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ 945 946 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ 947 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ 948 949 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ 950 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ 951 952 /* MPU Memory Attribute Indirection Register 1 Definitions */ 953 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ 954 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ 955 956 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ 957 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ 958 959 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ 960 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ 961 962 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ 963 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ 964 965 /*@} end of group CMSIS_MPU */ 966 #endif 967 968 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 969 /** 970 \ingroup CMSIS_core_register 971 \defgroup CMSIS_SAU Security Attribution Unit (SAU) 972 \brief Type definitions for the Security Attribution Unit (SAU) 973 @{ 974 */ 975 976 /** 977 \brief Structure type to access the Security Attribution Unit (SAU). 978 */ 979 typedef struct 980 { 981 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ 982 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ 983 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 984 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ 985 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ 986 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ 987 #endif 988 } SAU_Type; 989 990 /* SAU Control Register Definitions */ 991 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ 992 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ 993 994 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ 995 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ 996 997 /* SAU Type Register Definitions */ 998 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ 999 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ 1000 1001 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) 1002 /* SAU Region Number Register Definitions */ 1003 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ 1004 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ 1005 1006 /* SAU Region Base Address Register Definitions */ 1007 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ 1008 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ 1009 1010 /* SAU Region Limit Address Register Definitions */ 1011 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ 1012 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ 1013 1014 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ 1015 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ 1016 1017 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ 1018 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ 1019 1020 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ 1021 1022 /*@} end of group CMSIS_SAU */ 1023 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1024 1025 /** 1026 \ingroup CMSIS_core_register 1027 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 1028 \brief Type definitions for the Core Debug Registers 1029 @{ 1030 */ 1031 1032 /** 1033 \brief Structure type to access the Core Debug Register (CoreDebug). 1034 */ 1035 typedef struct { 1036 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 1037 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1038 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 1039 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 1040 uint32_t RESERVED4[1U]; 1041 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ 1042 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ 1043 } CoreDebug_Type; 1044 1045 /* Debug Halting Control and Status Register Definitions */ 1046 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 1047 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 1048 1049 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ 1050 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ 1051 1052 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 1053 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 1054 1055 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 1056 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 1057 1058 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 1059 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 1060 1061 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 1062 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 1063 1064 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 1065 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 1066 1067 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 1068 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 1069 1070 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 1071 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 1072 1073 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 1074 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 1075 1076 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 1077 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 1078 1079 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 1080 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 1081 1082 /* Debug Core Register Selector Register Definitions */ 1083 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 1084 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 1085 1086 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 1087 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 1088 1089 /* Debug Exception and Monitor Control Register */ 1090 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ 1091 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ 1092 1093 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 1094 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 1095 1096 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 1097 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 1098 1099 /* Debug Authentication Control Register Definitions */ 1100 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ 1101 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ 1102 1103 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ 1104 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ 1105 1106 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ 1107 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ 1108 1109 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ 1110 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ 1111 1112 /* Debug Security Control and Status Register Definitions */ 1113 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ 1114 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ 1115 1116 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ 1117 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ 1118 1119 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ 1120 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ 1121 1122 /*@} end of group CMSIS_CoreDebug */ 1123 1124 /** 1125 \ingroup CMSIS_core_register 1126 \defgroup CMSIS_core_bitfield Core register bit field macros 1127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 1128 @{ 1129 */ 1130 1131 /** 1132 \brief Mask and shift a bit field value for use in a register bit range. 1133 \param[in] field Name of the register bit field. 1134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 1135 \return Masked and shifted value. 1136 */ 1137 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 1138 1139 /** 1140 \brief Mask and shift a register value to extract a bit filed value. 1141 \param[in] field Name of the register bit field. 1142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 1143 \return Masked and shifted bit field value. 1144 */ 1145 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 1146 1147 /*@} end of group CMSIS_core_bitfield */ 1148 1149 /** 1150 \ingroup CMSIS_core_register 1151 \defgroup CMSIS_core_base Core Definitions 1152 \brief Definitions for base addresses, unions, and structures. 1153 @{ 1154 */ 1155 1156 /* Memory mapping of Core Hardware */ 1157 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 1158 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 1159 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 1160 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 1161 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 1162 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 1163 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 1164 1165 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 1166 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 1167 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 1168 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 1169 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 1170 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ 1171 1172 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1173 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 1174 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 1175 #endif 1176 1177 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1178 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ 1179 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ 1180 #endif 1181 1182 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1183 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ 1184 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ 1185 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ 1186 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ 1187 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ 1188 1189 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ 1190 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ 1191 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ 1192 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ 1193 1194 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1195 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ 1196 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ 1197 #endif 1198 1199 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1200 /*@} */ 1201 1202 /******************************************************************************* 1203 * Hardware Abstraction Layer 1204 Core Function Interface contains: 1205 - Core NVIC Functions 1206 - Core SysTick Functions 1207 - Core Register Access Functions 1208 ******************************************************************************/ 1209 /** 1210 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 1211 */ 1212 1213 /* ########################## NVIC functions #################################### */ 1214 /** 1215 \ingroup CMSIS_Core_FunctionInterface 1216 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 1217 \brief Functions that manage interrupts and exceptions via the NVIC. 1218 @{ 1219 */ 1220 1221 #ifdef CMSIS_NVIC_VIRTUAL 1222 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 1223 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 1224 #endif 1225 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 1226 #else 1227 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ 1228 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ 1229 #define NVIC_EnableIRQ __NVIC_EnableIRQ 1230 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 1231 #define NVIC_DisableIRQ __NVIC_DisableIRQ 1232 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 1233 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 1234 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 1235 #define NVIC_GetActive __NVIC_GetActive 1236 #define NVIC_SetPriority __NVIC_SetPriority 1237 #define NVIC_GetPriority __NVIC_GetPriority 1238 #define NVIC_SystemReset __NVIC_SystemReset 1239 #endif /* CMSIS_NVIC_VIRTUAL */ 1240 1241 #ifdef CMSIS_VECTAB_VIRTUAL 1242 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1243 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 1244 #endif 1245 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 1246 #else 1247 #define NVIC_SetVector __NVIC_SetVector 1248 #define NVIC_GetVector __NVIC_GetVector 1249 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 1250 1251 #define NVIC_USER_IRQ_OFFSET 16 1252 1253 /* Special LR values for Secure/Non-Secure call handling and exception handling */ 1254 1255 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ 1256 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ 1257 1258 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ 1259 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ 1260 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ 1261 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ 1262 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ 1263 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ 1264 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ 1265 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ 1266 1267 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ 1268 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ 1269 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ 1270 #else 1271 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ 1272 #endif 1273 1274 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 1275 /* The following MACROS handle generation of the register offset and byte masks */ 1276 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 1277 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 1278 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 1279 1280 #define __NVIC_SetPriorityGrouping(X) (void)(X) 1281 #define __NVIC_GetPriorityGrouping() (0U) 1282 1283 /** 1284 \brief Enable Interrupt 1285 \details Enables a device specific interrupt in the NVIC interrupt controller. 1286 \param [in] IRQn Device specific interrupt number. 1287 \note IRQn must not be negative. 1288 */ 1289 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 1290 { 1291 if ((int32_t) (IRQn) >= 0) { 1292 NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1293 << (((uint32_t) IRQn) & 0x1FUL)); 1294 } 1295 } 1296 1297 /** 1298 \brief Get Interrupt Enable status 1299 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 1300 \param [in] IRQn Device specific interrupt number. 1301 \return 0 Interrupt is not enabled. 1302 \return 1 Interrupt is enabled. 1303 \note IRQn must not be negative. 1304 */ 1305 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 1306 { 1307 if ((int32_t) (IRQn) >= 0) { 1308 return ((uint32_t) ( 1309 ((NVIC->ISER[(((uint32_t) IRQn) >> 5UL)] 1310 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1311 1UL : 0UL)); 1312 } else { 1313 return (0U); 1314 } 1315 } 1316 1317 /** 1318 \brief Disable Interrupt 1319 \details Disables a device specific interrupt in the NVIC interrupt controller. 1320 \param [in] IRQn Device specific interrupt number. 1321 \note IRQn must not be negative. 1322 */ 1323 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 1324 { 1325 if ((int32_t) (IRQn) >= 0) { 1326 NVIC->ICER[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1327 << (((uint32_t) IRQn) & 0x1FUL)); 1328 __DSB(); 1329 __ISB(); 1330 } 1331 } 1332 1333 /** 1334 \brief Get Pending Interrupt 1335 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 1336 \param [in] IRQn Device specific interrupt number. 1337 \return 0 Interrupt status is not pending. 1338 \return 1 Interrupt status is pending. 1339 \note IRQn must not be negative. 1340 */ 1341 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 1342 { 1343 if ((int32_t) (IRQn) >= 0) { 1344 return ((uint32_t) ( 1345 ((NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] 1346 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1347 1UL : 0UL)); 1348 } else { 1349 return (0U); 1350 } 1351 } 1352 1353 /** 1354 \brief Set Pending Interrupt 1355 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 1356 \param [in] IRQn Device specific interrupt number. 1357 \note IRQn must not be negative. 1358 */ 1359 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 1360 { 1361 if ((int32_t) (IRQn) >= 0) { 1362 NVIC->ISPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1363 << (((uint32_t) IRQn) & 0x1FUL)); 1364 } 1365 } 1366 1367 /** 1368 \brief Clear Pending Interrupt 1369 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 1370 \param [in] IRQn Device specific interrupt number. 1371 \note IRQn must not be negative. 1372 */ 1373 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 1374 { 1375 if ((int32_t) (IRQn) >= 0) { 1376 NVIC->ICPR[(((uint32_t) IRQn) >> 5UL)] = (uint32_t) (1UL 1377 << (((uint32_t) IRQn) & 0x1FUL)); 1378 } 1379 } 1380 1381 /** 1382 \brief Get Active Interrupt 1383 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 1384 \param [in] IRQn Device specific interrupt number. 1385 \return 0 Interrupt status is not active. 1386 \return 1 Interrupt status is active. 1387 \note IRQn must not be negative. 1388 */ 1389 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 1390 { 1391 if ((int32_t) (IRQn) >= 0) { 1392 return ((uint32_t) ( 1393 ((NVIC->IABR[(((uint32_t) IRQn) >> 5UL)] 1394 & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 1395 1UL : 0UL)); 1396 } else { 1397 return (0U); 1398 } 1399 } 1400 1401 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1402 /** 1403 \brief Get Interrupt Target State 1404 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1405 \param [in] IRQn Device specific interrupt number. 1406 \return 0 if interrupt is assigned to Secure 1407 \return 1 if interrupt is assigned to Non Secure 1408 \note IRQn must not be negative. 1409 */ 1410 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) 1411 { 1412 if ((int32_t)(IRQn) >= 0) 1413 { 1414 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1415 } 1416 else 1417 { 1418 return(0U); 1419 } 1420 } 1421 1422 /** 1423 \brief Set Interrupt Target State 1424 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1425 \param [in] IRQn Device specific interrupt number. 1426 \return 0 if interrupt is assigned to Secure 1427 1 if interrupt is assigned to Non Secure 1428 \note IRQn must not be negative. 1429 */ 1430 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) 1431 { 1432 if ((int32_t)(IRQn) >= 0) 1433 { 1434 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 1435 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1436 } 1437 else 1438 { 1439 return(0U); 1440 } 1441 } 1442 1443 /** 1444 \brief Clear Interrupt Target State 1445 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. 1446 \param [in] IRQn Device specific interrupt number. 1447 \return 0 if interrupt is assigned to Secure 1448 1 if interrupt is assigned to Non Secure 1449 \note IRQn must not be negative. 1450 */ 1451 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) 1452 { 1453 if ((int32_t)(IRQn) >= 0) 1454 { 1455 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); 1456 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1457 } 1458 else 1459 { 1460 return(0U); 1461 } 1462 } 1463 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1464 1465 /** 1466 \brief Set Interrupt Priority 1467 \details Sets the priority of a device specific interrupt or a processor exception. 1468 The interrupt number can be positive to specify a device specific interrupt, 1469 or negative to specify a processor exception. 1470 \param [in] IRQn Interrupt number. 1471 \param [in] priority Priority to set. 1472 \note The priority cannot be set for every processor exception. 1473 */ 1474 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1475 { 1476 if ((int32_t) (IRQn) >= 0) { 1477 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t) (NVIC->IPR[_IP_IDX(IRQn)] 1478 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 1479 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 1480 << _BIT_SHIFT(IRQn))); 1481 } else { 1482 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t) (SCB->SHPR[_SHP_IDX(IRQn)] 1483 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 1484 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 1485 << _BIT_SHIFT(IRQn))); 1486 } 1487 } 1488 1489 /** 1490 \brief Get Interrupt Priority 1491 \details Reads the priority of a device specific interrupt or a processor exception. 1492 The interrupt number can be positive to specify a device specific interrupt, 1493 or negative to specify a processor exception. 1494 \param [in] IRQn Interrupt number. 1495 \return Interrupt Priority. 1496 Value is aligned automatically to the implemented priority bits of the microcontroller. 1497 */ 1498 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 1499 { 1500 1501 if ((int32_t) (IRQn) >= 0) { 1502 return ((uint32_t) (((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 1503 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1504 } else { 1505 return ((uint32_t) (((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 1506 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1507 } 1508 } 1509 1510 /** 1511 \brief Encode Priority 1512 \details Encodes the priority for an interrupt with the given priority group, 1513 preemptive priority value, and subpriority value. 1514 In case of a conflict between priority grouping and available 1515 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 1516 \param [in] PriorityGroup Used priority group. 1517 \param [in] PreemptPriority Preemptive priority value (starting from 0). 1518 \param [in] SubPriority Subpriority value (starting from 0). 1519 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 1520 */ 1521 __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, 1522 uint32_t PreemptPriority, uint32_t SubPriority) 1523 { 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1525 uint32_t PreemptPriorityBits; 1526 uint32_t SubPriorityBits; 1527 1528 PreemptPriorityBits = 1529 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 1530 (uint32_t) (__NVIC_PRIO_BITS) : 1531 (uint32_t) (7UL - PriorityGroupTmp); 1532 SubPriorityBits = 1533 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) < (uint32_t) 7UL) ? 1534 (uint32_t) 0UL : 1535 (uint32_t) ((PriorityGroupTmp - 7UL) 1536 + (uint32_t) (__NVIC_PRIO_BITS)); 1537 1538 return (((PreemptPriority 1539 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL)) 1540 << SubPriorityBits) 1541 | ((SubPriority & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL)))); 1542 } 1543 1544 /** 1545 \brief Decode Priority 1546 \details Decodes an interrupt priority value with a given priority group to 1547 preemptive priority value and subpriority value. 1548 In case of a conflict between priority grouping and available 1549 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 1550 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 1551 \param [in] PriorityGroup Used priority group. 1552 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 1553 \param [out] pSubPriority Subpriority value (starting from 0). 1554 */ 1555 __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, 1556 uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 1557 uint32_t *const pSubPriority) 1558 { 1559 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 1560 uint32_t PreemptPriorityBits; 1561 uint32_t SubPriorityBits; 1562 1563 PreemptPriorityBits = 1564 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 1565 (uint32_t) (__NVIC_PRIO_BITS) : 1566 (uint32_t) (7UL - PriorityGroupTmp); 1567 SubPriorityBits = 1568 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) < (uint32_t) 7UL) ? 1569 (uint32_t) 0UL : 1570 (uint32_t) ((PriorityGroupTmp - 7UL) 1571 + (uint32_t) (__NVIC_PRIO_BITS)); 1572 1573 *pPreemptPriority = (Priority >> SubPriorityBits) 1574 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL); 1575 *pSubPriority = (Priority) & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL); 1576 } 1577 1578 /** 1579 \brief Set Interrupt Vector 1580 \details Sets an interrupt vector in SRAM based interrupt vector table. 1581 The interrupt number can be positive to specify a device specific interrupt, 1582 or negative to specify a processor exception. 1583 VTOR must been relocated to SRAM before. 1584 If VTOR is not present address 0 must be mapped to SRAM. 1585 \param [in] IRQn Interrupt number 1586 \param [in] vector Address of interrupt handler function 1587 */ 1588 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 1589 { 1590 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 1591 uint32_t *vectors = (uint32_t *)SCB->VTOR; 1592 #else 1593 uint32_t *vectors = (uint32_t*) 0x0U; 1594 #endif 1595 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 1596 } 1597 1598 /** 1599 \brief Get Interrupt Vector 1600 \details Reads an interrupt vector from interrupt vector table. 1601 The interrupt number can be positive to specify a device specific interrupt, 1602 or negative to specify a processor exception. 1603 \param [in] IRQn Interrupt number. 1604 \return Address of interrupt handler function 1605 */ 1606 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 1607 { 1608 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 1609 uint32_t *vectors = (uint32_t *)SCB->VTOR; 1610 #else 1611 uint32_t *vectors = (uint32_t*) 0x0U; 1612 #endif 1613 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 1614 } 1615 1616 /** 1617 \brief System Reset 1618 \details Initiates a system reset request to reset the MCU. 1619 */ 1620 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 1621 { 1622 __DSB(); /* Ensure all outstanding memory accesses included 1623 buffered write are completed before reset */ 1624 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 1625 SCB_AIRCR_SYSRESETREQ_Msk); 1626 __DSB(); /* Ensure completion of memory access */ 1627 1628 for (;;) /* wait until reset */ 1629 { 1630 __NOP(); 1631 } 1632 } 1633 1634 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1635 /** 1636 \brief Enable Interrupt (non-secure) 1637 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 1638 \param [in] IRQn Device specific interrupt number. 1639 \note IRQn must not be negative. 1640 */ 1641 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) 1642 { 1643 if ((int32_t)(IRQn) >= 0) 1644 { 1645 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1646 } 1647 } 1648 1649 /** 1650 \brief Get Interrupt Enable status (non-secure) 1651 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. 1652 \param [in] IRQn Device specific interrupt number. 1653 \return 0 Interrupt is not enabled. 1654 \return 1 Interrupt is enabled. 1655 \note IRQn must not be negative. 1656 */ 1657 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) 1658 { 1659 if ((int32_t)(IRQn) >= 0) 1660 { 1661 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1662 } 1663 else 1664 { 1665 return(0U); 1666 } 1667 } 1668 1669 /** 1670 \brief Disable Interrupt (non-secure) 1671 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. 1672 \param [in] IRQn Device specific interrupt number. 1673 \note IRQn must not be negative. 1674 */ 1675 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) 1676 { 1677 if ((int32_t)(IRQn) >= 0) 1678 { 1679 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1680 } 1681 } 1682 1683 /** 1684 \brief Get Pending Interrupt (non-secure) 1685 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. 1686 \param [in] IRQn Device specific interrupt number. 1687 \return 0 Interrupt status is not pending. 1688 \return 1 Interrupt status is pending. 1689 \note IRQn must not be negative. 1690 */ 1691 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) 1692 { 1693 if ((int32_t)(IRQn) >= 0) 1694 { 1695 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1696 } 1697 else 1698 { 1699 return(0U); 1700 } 1701 } 1702 1703 /** 1704 \brief Set Pending Interrupt (non-secure) 1705 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 1706 \param [in] IRQn Device specific interrupt number. 1707 \note IRQn must not be negative. 1708 */ 1709 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) 1710 { 1711 if ((int32_t)(IRQn) >= 0) 1712 { 1713 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1714 } 1715 } 1716 1717 /** 1718 \brief Clear Pending Interrupt (non-secure) 1719 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. 1720 \param [in] IRQn Device specific interrupt number. 1721 \note IRQn must not be negative. 1722 */ 1723 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) 1724 { 1725 if ((int32_t)(IRQn) >= 0) 1726 { 1727 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 1728 } 1729 } 1730 1731 /** 1732 \brief Get Active Interrupt (non-secure) 1733 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. 1734 \param [in] IRQn Device specific interrupt number. 1735 \return 0 Interrupt status is not active. 1736 \return 1 Interrupt status is active. 1737 \note IRQn must not be negative. 1738 */ 1739 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) 1740 { 1741 if ((int32_t)(IRQn) >= 0) 1742 { 1743 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 1744 } 1745 else 1746 { 1747 return(0U); 1748 } 1749 } 1750 1751 /** 1752 \brief Set Interrupt Priority (non-secure) 1753 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 1754 The interrupt number can be positive to specify a device specific interrupt, 1755 or negative to specify a processor exception. 1756 \param [in] IRQn Interrupt number. 1757 \param [in] priority Priority to set. 1758 \note The priority cannot be set for every non-secure processor exception. 1759 */ 1760 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) 1761 { 1762 if ((int32_t)(IRQn) >= 0) 1763 { 1764 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1765 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1766 } 1767 else 1768 { 1769 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 1770 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 1771 } 1772 } 1773 1774 /** 1775 \brief Get Interrupt Priority (non-secure) 1776 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. 1777 The interrupt number can be positive to specify a device specific interrupt, 1778 or negative to specify a processor exception. 1779 \param [in] IRQn Interrupt number. 1780 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. 1781 */ 1782 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) 1783 { 1784 1785 if ((int32_t)(IRQn) >= 0) 1786 { 1787 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1788 } 1789 else 1790 { 1791 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 1792 } 1793 } 1794 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ 1795 1796 /*@} end of CMSIS_Core_NVICFunctions */ 1797 1798 /* ########################## MPU functions #################################### */ 1799 1800 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 1801 1802 #include "mpu_armv8.h" 1803 1804 #endif 1805 1806 /* ########################## FPU functions #################################### */ 1807 /** 1808 \ingroup CMSIS_Core_FunctionInterface 1809 \defgroup CMSIS_Core_FpuFunctions FPU Functions 1810 \brief Function that provides FPU type. 1811 @{ 1812 */ 1813 1814 /** 1815 \brief get FPU type 1816 \details returns the FPU type 1817 \returns 1818 - \b 0: No FPU 1819 - \b 1: Single precision FPU 1820 - \b 2: Double + Single precision FPU 1821 */ 1822 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 1823 { 1824 return 0U; /* No FPU */ 1825 } 1826 1827 /*@} end of CMSIS_Core_FpuFunctions */ 1828 1829 /* ########################## SAU functions #################################### */ 1830 /** 1831 \ingroup CMSIS_Core_FunctionInterface 1832 \defgroup CMSIS_Core_SAUFunctions SAU Functions 1833 \brief Functions that configure the SAU. 1834 @{ 1835 */ 1836 1837 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1838 1839 /** 1840 \brief Enable SAU 1841 \details Enables the Security Attribution Unit (SAU). 1842 */ 1843 __STATIC_INLINE void TZ_SAU_Enable(void) 1844 { 1845 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); 1846 } 1847 1848 1849 1850 /** 1851 \brief Disable SAU 1852 \details Disables the Security Attribution Unit (SAU). 1853 */ 1854 __STATIC_INLINE void TZ_SAU_Disable(void) 1855 { 1856 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); 1857 } 1858 1859 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1860 1861 /*@} end of CMSIS_Core_SAUFunctions */ 1862 1863 /* ################################## SysTick function ############################################ */ 1864 /** 1865 \ingroup CMSIS_Core_FunctionInterface 1866 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 1867 \brief Functions that configure the System. 1868 @{ 1869 */ 1870 1871 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 1872 1873 /** 1874 \brief System Tick Configuration 1875 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 1876 Counter is in free running mode to generate periodic interrupts. 1877 \param [in] ticks Number of ticks between two interrupts. 1878 \return 0 Function succeeded. 1879 \return 1 Function failed. 1880 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1881 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 1882 must contain a vendor-specific implementation of this function. 1883 */ 1884 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 1885 { 1886 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1887 { 1888 return (1UL); /* Reload value impossible */ 1889 } 1890 1891 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1892 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1893 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 1894 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1895 SysTick_CTRL_TICKINT_Msk | 1896 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1897 return (0UL); /* Function successful */ 1898 } 1899 1900 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 1901 /** 1902 \brief System Tick Configuration (non-secure) 1903 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. 1904 Counter is in free running mode to generate periodic interrupts. 1905 \param [in] ticks Number of ticks between two interrupts. 1906 \return 0 Function succeeded. 1907 \return 1 Function failed. 1908 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1909 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> 1910 must contain a vendor-specific implementation of this function. 1911 1912 */ 1913 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) 1914 { 1915 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1916 { 1917 return (1UL); /* Reload value impossible */ 1918 } 1919 1920 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1921 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1922 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ 1923 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1924 SysTick_CTRL_TICKINT_Msk | 1925 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1926 return (0UL); /* Function successful */ 1927 } 1928 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 1929 1930 #endif 1931 1932 /*@} end of CMSIS_Core_SysTickFunctions */ 1933 1934 #ifdef __cplusplus 1935 } 1936 #endif 1937 1938 #endif /* __CORE_CM23_H_DEPENDANT */ 1939 1940 #endif /* __CMSIS_GENERIC */