Drivers/CMSIS/Include/core_cm0plus.h (48921B)
1 /**************************************************************************//** 2 * @file core_cm0plus.h 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File 4 * @version V5.0.6 5 * @date 28. May 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #if defined ( __ICCARM__ ) 26 #pragma system_include /* treat file as system include file for MISRA check */ 27 #elif defined (__clang__) 28 #pragma clang system_header /* treat file as system include file */ 29 #endif 30 31 #ifndef __CORE_CM0PLUS_H_GENERIC 32 #define __CORE_CM0PLUS_H_GENERIC 33 34 #include <stdint.h> 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /** 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42 CMSIS violates the following MISRA-C:2004 rules: 43 44 \li Required Rule 8.5, object/function definition in header file.<br> 45 Function definitions in header files are used to allow 'inlining'. 46 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 48 Unions are used for effective representation of core registers. 49 50 \li Advisory Rule 19.7, Function-like macro defined.<br> 51 Function-like macros are used to allow more efficient code. 52 */ 53 54 /******************************************************************************* 55 * CMSIS definitions 56 ******************************************************************************/ 57 /** 58 \ingroup Cortex-M0+ 59 @{ 60 */ 61 62 #include "cmsis_version.h" 63 64 /* CMSIS CM0+ definitions */ 65 #define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ 66 #define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ 67 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ 68 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ 69 70 #define __CORTEX_M (0U) /*!< Cortex-M Core */ 71 72 /** __FPU_USED indicates whether an FPU is used or not. 73 This core does not support an FPU at all 74 */ 75 #define __FPU_USED 0U 76 77 #if defined ( __CC_ARM ) 78 #if defined __TARGET_FPU_VFP 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 80 #endif 81 82 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 83 #if defined __ARM_PCS_VFP 84 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 85 #endif 86 87 #elif defined ( __GNUC__ ) 88 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 90 #endif 91 92 #elif defined ( __ICCARM__ ) 93 #if defined __ARMVFP__ 94 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 95 #endif 96 97 #elif defined ( __TI_ARM__ ) 98 #if defined __TI_VFP_SUPPORT__ 99 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 100 #endif 101 102 #elif defined ( __TASKING__ ) 103 #if defined __FPU_VFP__ 104 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 105 #endif 106 107 #elif defined ( __CSMC__ ) 108 #if ( __CSMC__ & 0x400U) 109 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 110 #endif 111 112 #endif 113 114 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 115 116 #ifdef __cplusplus 117 } 118 #endif 119 120 #endif /* __CORE_CM0PLUS_H_GENERIC */ 121 122 #ifndef __CMSIS_GENERIC 123 124 #ifndef __CORE_CM0PLUS_H_DEPENDANT 125 #define __CORE_CM0PLUS_H_DEPENDANT 126 127 #ifdef __cplusplus 128 extern "C" { 129 #endif 130 131 /* check device defines and use defaults */ 132 #if defined __CHECK_DEVICE_DEFINES 133 #ifndef __CM0PLUS_REV 134 #define __CM0PLUS_REV 0x0000U 135 #warning "__CM0PLUS_REV not defined in device header file; using default!" 136 #endif 137 138 #ifndef __MPU_PRESENT 139 #define __MPU_PRESENT 0U 140 #warning "__MPU_PRESENT not defined in device header file; using default!" 141 #endif 142 143 #ifndef __VTOR_PRESENT 144 #define __VTOR_PRESENT 0U 145 #warning "__VTOR_PRESENT not defined in device header file; using default!" 146 #endif 147 148 #ifndef __NVIC_PRIO_BITS 149 #define __NVIC_PRIO_BITS 2U 150 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 151 #endif 152 153 #ifndef __Vendor_SysTickConfig 154 #define __Vendor_SysTickConfig 0U 155 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 156 #endif 157 #endif 158 159 /* IO definitions (access restrictions to peripheral registers) */ 160 /** 161 \defgroup CMSIS_glob_defs CMSIS Global Defines 162 163 <strong>IO Type Qualifiers</strong> are used 164 \li to specify the access to peripheral variables. 165 \li for automatic generation of peripheral register debug information. 166 */ 167 #ifdef __cplusplus 168 #define __I volatile /*!< Defines 'read only' permissions */ 169 #else 170 #define __I volatile const /*!< Defines 'read only' permissions */ 171 #endif 172 #define __O volatile /*!< Defines 'write only' permissions */ 173 #define __IO volatile /*!< Defines 'read / write' permissions */ 174 175 /* following defines should be used for structure members */ 176 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 177 #define __OM volatile /*! Defines 'write only' structure member permissions */ 178 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 179 180 /*@} end of group Cortex-M0+ */ 181 182 /******************************************************************************* 183 * Register Abstraction 184 Core Register contain: 185 - Core Register 186 - Core NVIC Register 187 - Core SCB Register 188 - Core SysTick Register 189 - Core MPU Register 190 ******************************************************************************/ 191 /** 192 \defgroup CMSIS_core_register Defines and Type Definitions 193 \brief Type definitions and defines for Cortex-M processor based devices. 194 */ 195 196 /** 197 \ingroup CMSIS_core_register 198 \defgroup CMSIS_CORE Status and Control Registers 199 \brief Core Register type definitions. 200 @{ 201 */ 202 203 /** 204 \brief Union type to access the Application Program Status Register (APSR). 205 */ 206 typedef union { 207 struct { 208 uint32_t _reserved0 :28; /*!< bit: 0..27 Reserved */ 209 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 210 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 211 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 212 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 213 } b; /*!< Structure used for bit access */ 214 uint32_t w; /*!< Type used for word access */ 215 } APSR_Type; 216 217 /* APSR Register Definitions */ 218 #define APSR_N_Pos 31U /*!< APSR: N Position */ 219 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 220 221 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 222 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 223 224 #define APSR_C_Pos 29U /*!< APSR: C Position */ 225 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 226 227 #define APSR_V_Pos 28U /*!< APSR: V Position */ 228 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 229 230 /** 231 \brief Union type to access the Interrupt Program Status Register (IPSR). 232 */ 233 typedef union { 234 struct { 235 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 236 uint32_t _reserved0 :23; /*!< bit: 9..31 Reserved */ 237 } b; /*!< Structure used for bit access */ 238 uint32_t w; /*!< Type used for word access */ 239 } IPSR_Type; 240 241 /* IPSR Register Definitions */ 242 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 243 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 244 245 /** 246 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 247 */ 248 typedef union { 249 struct { 250 uint32_t ISR :9; /*!< bit: 0.. 8 Exception number */ 251 uint32_t _reserved0 :15; /*!< bit: 9..23 Reserved */ 252 uint32_t T :1; /*!< bit: 24 Thumb bit (read 0) */ 253 uint32_t _reserved1 :3; /*!< bit: 25..27 Reserved */ 254 uint32_t V :1; /*!< bit: 28 Overflow condition code flag */ 255 uint32_t C :1; /*!< bit: 29 Carry condition code flag */ 256 uint32_t Z :1; /*!< bit: 30 Zero condition code flag */ 257 uint32_t N :1; /*!< bit: 31 Negative condition code flag */ 258 } b; /*!< Structure used for bit access */ 259 uint32_t w; /*!< Type used for word access */ 260 } xPSR_Type; 261 262 /* xPSR Register Definitions */ 263 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 264 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 265 266 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 267 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 268 269 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 270 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 271 272 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 273 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 274 275 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 276 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 277 278 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 279 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 280 281 /** 282 \brief Union type to access the Control Registers (CONTROL). 283 */ 284 typedef union { 285 struct { 286 uint32_t nPRIV :1; /*!< bit: 0 Execution privilege in Thread mode */ 287 uint32_t SPSEL :1; /*!< bit: 1 Stack to be used */ 288 uint32_t _reserved1 :30; /*!< bit: 2..31 Reserved */ 289 } b; /*!< Structure used for bit access */ 290 uint32_t w; /*!< Type used for word access */ 291 } CONTROL_Type; 292 293 /* CONTROL Register Definitions */ 294 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 295 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 296 297 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 298 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 299 300 /*@} end of group CMSIS_CORE */ 301 302 /** 303 \ingroup CMSIS_core_register 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 305 \brief Type definitions for the NVIC Registers 306 @{ 307 */ 308 309 /** 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 311 */ 312 typedef struct { 313 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 314 uint32_t RESERVED0[31U]; 315 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 316 uint32_t RSERVED1[31U]; 317 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 318 uint32_t RESERVED2[31U]; 319 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 320 uint32_t RESERVED3[31U]; 321 uint32_t RESERVED4[64U]; 322 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 323 } NVIC_Type; 324 325 /*@} end of group CMSIS_NVIC */ 326 327 /** 328 \ingroup CMSIS_core_register 329 \defgroup CMSIS_SCB System Control Block (SCB) 330 \brief Type definitions for the System Control Block Registers 331 @{ 332 */ 333 334 /** 335 \brief Structure type to access the System Control Block (SCB). 336 */ 337 typedef struct { 338 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 339 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 340 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 341 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 342 #else 343 uint32_t RESERVED0; 344 #endif 345 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 346 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 347 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 348 uint32_t RESERVED1; 349 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 350 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 351 } SCB_Type; 352 353 /* SCB CPUID Register Definitions */ 354 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 356 357 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 359 360 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 362 363 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 365 366 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 367 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 368 369 /* SCB Interrupt Control State Register Definitions */ 370 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 372 373 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 375 376 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 378 379 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 381 382 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 384 385 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 387 388 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 390 391 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 393 394 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 395 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 396 397 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 398 /* SCB Interrupt Control State Register Definitions */ 399 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ 400 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 401 #endif 402 403 /* SCB Application Interrupt and Reset Control Register Definitions */ 404 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 405 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 406 407 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 408 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 409 410 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 411 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 412 413 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 414 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 415 416 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 417 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 418 419 /* SCB System Control Register Definitions */ 420 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 421 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 422 423 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 424 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 425 426 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 427 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 428 429 /* SCB Configuration Control Register Definitions */ 430 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 431 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 432 433 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 434 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 435 436 /* SCB System Handler Control and State Register Definitions */ 437 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 438 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 439 440 /*@} end of group CMSIS_SCB */ 441 442 /** 443 \ingroup CMSIS_core_register 444 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 445 \brief Type definitions for the System Timer Registers. 446 @{ 447 */ 448 449 /** 450 \brief Structure type to access the System Timer (SysTick). 451 */ 452 typedef struct { 453 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 454 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 455 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 456 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 457 } SysTick_Type; 458 459 /* SysTick Control / Status Register Definitions */ 460 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 461 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 462 463 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 464 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 465 466 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 467 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 468 469 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 470 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 471 472 /* SysTick Reload Register Definitions */ 473 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 474 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 475 476 /* SysTick Current Register Definitions */ 477 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 478 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 479 480 /* SysTick Calibration Register Definitions */ 481 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 482 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 483 484 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 485 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 486 487 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 488 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 489 490 /*@} end of group CMSIS_SysTick */ 491 492 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 493 /** 494 \ingroup CMSIS_core_register 495 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 496 \brief Type definitions for the Memory Protection Unit (MPU) 497 @{ 498 */ 499 500 /** 501 \brief Structure type to access the Memory Protection Unit (MPU). 502 */ 503 typedef struct 504 { 505 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 506 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 507 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 508 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 509 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 510 }MPU_Type; 511 512 #define MPU_TYPE_RALIASES 1U 513 514 /* MPU Type Register Definitions */ 515 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 516 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 517 518 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 519 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 520 521 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 522 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 523 524 /* MPU Control Register Definitions */ 525 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 526 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 527 528 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 529 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 530 531 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 532 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 533 534 /* MPU Region Number Register Definitions */ 535 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 536 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 537 538 /* MPU Region Base Address Register Definitions */ 539 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ 540 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 541 542 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 543 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 544 545 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 546 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 547 548 /* MPU Region Attribute and Size Register Definitions */ 549 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 550 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 551 552 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 553 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 554 555 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 556 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 557 558 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 559 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 560 561 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 562 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 563 564 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 565 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 566 567 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 568 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 569 570 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 571 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 572 573 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 574 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 575 576 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 577 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 578 579 /*@} end of group CMSIS_MPU */ 580 #endif 581 582 /** 583 \ingroup CMSIS_core_register 584 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 585 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. 586 Therefore they are not covered by the Cortex-M0+ header file. 587 @{ 588 */ 589 /*@} end of group CMSIS_CoreDebug */ 590 591 /** 592 \ingroup CMSIS_core_register 593 \defgroup CMSIS_core_bitfield Core register bit field macros 594 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 595 @{ 596 */ 597 598 /** 599 \brief Mask and shift a bit field value for use in a register bit range. 600 \param[in] field Name of the register bit field. 601 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 602 \return Masked and shifted value. 603 */ 604 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 605 606 /** 607 \brief Mask and shift a register value to extract a bit filed value. 608 \param[in] field Name of the register bit field. 609 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 610 \return Masked and shifted bit field value. 611 */ 612 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 613 614 /*@} end of group CMSIS_core_bitfield */ 615 616 /** 617 \ingroup CMSIS_core_register 618 \defgroup CMSIS_core_base Core Definitions 619 \brief Definitions for base addresses, unions, and structures. 620 @{ 621 */ 622 623 /* Memory mapping of Core Hardware */ 624 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 625 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 626 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 627 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 628 629 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 630 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 631 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 632 633 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 634 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 635 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 636 #endif 637 638 /*@} */ 639 640 /******************************************************************************* 641 * Hardware Abstraction Layer 642 Core Function Interface contains: 643 - Core NVIC Functions 644 - Core SysTick Functions 645 - Core Register Access Functions 646 ******************************************************************************/ 647 /** 648 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 649 */ 650 651 /* ########################## NVIC functions #################################### */ 652 /** 653 \ingroup CMSIS_Core_FunctionInterface 654 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 655 \brief Functions that manage interrupts and exceptions via the NVIC. 656 @{ 657 */ 658 659 #ifdef CMSIS_NVIC_VIRTUAL 660 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 661 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 662 #endif 663 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 664 #else 665 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 666 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 667 #define NVIC_EnableIRQ __NVIC_EnableIRQ 668 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 669 #define NVIC_DisableIRQ __NVIC_DisableIRQ 670 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 671 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 672 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 673 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ 674 #define NVIC_SetPriority __NVIC_SetPriority 675 #define NVIC_GetPriority __NVIC_GetPriority 676 #define NVIC_SystemReset __NVIC_SystemReset 677 #endif /* CMSIS_NVIC_VIRTUAL */ 678 679 #ifdef CMSIS_VECTAB_VIRTUAL 680 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 681 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 682 #endif 683 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 684 #else 685 #define NVIC_SetVector __NVIC_SetVector 686 #define NVIC_GetVector __NVIC_GetVector 687 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 688 689 #define NVIC_USER_IRQ_OFFSET 16 690 691 /* The following EXC_RETURN values are saved the LR on exception entry */ 692 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ 693 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ 694 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ 695 696 /* Interrupt Priorities are WORD accessible only under Armv6-M */ 697 /* The following MACROS handle generation of the register offset and byte masks */ 698 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 699 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 700 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 701 702 #define __NVIC_SetPriorityGrouping(X) (void)(X) 703 #define __NVIC_GetPriorityGrouping() (0U) 704 705 /** 706 \brief Enable Interrupt 707 \details Enables a device specific interrupt in the NVIC interrupt controller. 708 \param [in] IRQn Device specific interrupt number. 709 \note IRQn must not be negative. 710 */ 711 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 712 { 713 if ((int32_t) (IRQn) >= 0) { 714 NVIC->ISER[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 715 } 716 } 717 718 /** 719 \brief Get Interrupt Enable status 720 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 721 \param [in] IRQn Device specific interrupt number. 722 \return 0 Interrupt is not enabled. 723 \return 1 Interrupt is enabled. 724 \note IRQn must not be negative. 725 */ 726 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 727 { 728 if ((int32_t) (IRQn) >= 0) { 729 return ((uint32_t) ( 730 ((NVIC->ISER[0U] & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 731 1UL : 0UL)); 732 } else { 733 return (0U); 734 } 735 } 736 737 /** 738 \brief Disable Interrupt 739 \details Disables a device specific interrupt in the NVIC interrupt controller. 740 \param [in] IRQn Device specific interrupt number. 741 \note IRQn must not be negative. 742 */ 743 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 744 { 745 if ((int32_t) (IRQn) >= 0) { 746 NVIC->ICER[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 747 __DSB(); 748 __ISB(); 749 } 750 } 751 752 /** 753 \brief Get Pending Interrupt 754 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 755 \param [in] IRQn Device specific interrupt number. 756 \return 0 Interrupt status is not pending. 757 \return 1 Interrupt status is pending. 758 \note IRQn must not be negative. 759 */ 760 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 761 { 762 if ((int32_t) (IRQn) >= 0) { 763 return ((uint32_t) ( 764 ((NVIC->ISPR[0U] & (1UL << (((uint32_t) IRQn) & 0x1FUL))) != 0UL) ? 765 1UL : 0UL)); 766 } else { 767 return (0U); 768 } 769 } 770 771 /** 772 \brief Set Pending Interrupt 773 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 774 \param [in] IRQn Device specific interrupt number. 775 \note IRQn must not be negative. 776 */ 777 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 778 { 779 if ((int32_t) (IRQn) >= 0) { 780 NVIC->ISPR[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 781 } 782 } 783 784 /** 785 \brief Clear Pending Interrupt 786 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 787 \param [in] IRQn Device specific interrupt number. 788 \note IRQn must not be negative. 789 */ 790 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 791 { 792 if ((int32_t) (IRQn) >= 0) { 793 NVIC->ICPR[0U] = (uint32_t) (1UL << (((uint32_t) IRQn) & 0x1FUL)); 794 } 795 } 796 797 /** 798 \brief Set Interrupt Priority 799 \details Sets the priority of a device specific interrupt or a processor exception. 800 The interrupt number can be positive to specify a device specific interrupt, 801 or negative to specify a processor exception. 802 \param [in] IRQn Interrupt number. 803 \param [in] priority Priority to set. 804 \note The priority cannot be set for every processor exception. 805 */ 806 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 807 { 808 if ((int32_t) (IRQn) >= 0) { 809 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t) (NVIC->IP[_IP_IDX(IRQn)] 810 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 811 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 812 << _BIT_SHIFT(IRQn))); 813 } else { 814 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t) (SCB->SHP[_SHP_IDX(IRQn)] 815 & ~(0xFFUL << _BIT_SHIFT(IRQn))) 816 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t) 0xFFUL) 817 << _BIT_SHIFT(IRQn))); 818 } 819 } 820 821 /** 822 \brief Get Interrupt Priority 823 \details Reads the priority of a device specific interrupt or a processor exception. 824 The interrupt number can be positive to specify a device specific interrupt, 825 or negative to specify a processor exception. 826 \param [in] IRQn Interrupt number. 827 \return Interrupt Priority. 828 Value is aligned automatically to the implemented priority bits of the microcontroller. 829 */ 830 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 831 { 832 833 if ((int32_t) (IRQn) >= 0) { 834 return ((uint32_t) (((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 835 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 836 } else { 837 return ((uint32_t) (((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn)) 838 & (uint32_t) 0xFFUL) >> (8U - __NVIC_PRIO_BITS))); 839 } 840 } 841 842 /** 843 \brief Encode Priority 844 \details Encodes the priority for an interrupt with the given priority group, 845 preemptive priority value, and subpriority value. 846 In case of a conflict between priority grouping and available 847 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 848 \param [in] PriorityGroup Used priority group. 849 \param [in] PreemptPriority Preemptive priority value (starting from 0). 850 \param [in] SubPriority Subpriority value (starting from 0). 851 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 852 */ 853 __STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, 854 uint32_t PreemptPriority, uint32_t SubPriority) 855 { 856 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 857 uint32_t PreemptPriorityBits; 858 uint32_t SubPriorityBits; 859 860 PreemptPriorityBits = 861 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 862 (uint32_t) (__NVIC_PRIO_BITS) : 863 (uint32_t) (7UL - PriorityGroupTmp); 864 SubPriorityBits = 865 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) < (uint32_t) 7UL) ? 866 (uint32_t) 0UL : 867 (uint32_t) ((PriorityGroupTmp - 7UL) 868 + (uint32_t) (__NVIC_PRIO_BITS)); 869 870 return (((PreemptPriority 871 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL)) 872 << SubPriorityBits) 873 | ((SubPriority & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL)))); 874 } 875 876 /** 877 \brief Decode Priority 878 \details Decodes an interrupt priority value with a given priority group to 879 preemptive priority value and subpriority value. 880 In case of a conflict between priority grouping and available 881 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 882 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 883 \param [in] PriorityGroup Used priority group. 884 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 885 \param [out] pSubPriority Subpriority value (starting from 0). 886 */ 887 __STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, 888 uint32_t PriorityGroup, uint32_t *const pPreemptPriority, 889 uint32_t *const pSubPriority) 890 { 891 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t) 0x07UL); /* only values 0..7 are used */ 892 uint32_t PreemptPriorityBits; 893 uint32_t SubPriorityBits; 894 895 PreemptPriorityBits = 896 ((7UL - PriorityGroupTmp) > (uint32_t) (__NVIC_PRIO_BITS)) ? 897 (uint32_t) (__NVIC_PRIO_BITS) : 898 (uint32_t) (7UL - PriorityGroupTmp); 899 SubPriorityBits = 900 ((PriorityGroupTmp + (uint32_t) (__NVIC_PRIO_BITS)) < (uint32_t) 7UL) ? 901 (uint32_t) 0UL : 902 (uint32_t) ((PriorityGroupTmp - 7UL) 903 + (uint32_t) (__NVIC_PRIO_BITS)); 904 905 *pPreemptPriority = (Priority >> SubPriorityBits) 906 & (uint32_t) ((1UL << (PreemptPriorityBits)) - 1UL); 907 *pSubPriority = (Priority) & (uint32_t) ((1UL << (SubPriorityBits)) - 1UL); 908 } 909 910 /** 911 \brief Set Interrupt Vector 912 \details Sets an interrupt vector in SRAM based interrupt vector table. 913 The interrupt number can be positive to specify a device specific interrupt, 914 or negative to specify a processor exception. 915 VTOR must been relocated to SRAM before. 916 If VTOR is not present address 0 must be mapped to SRAM. 917 \param [in] IRQn Interrupt number 918 \param [in] vector Address of interrupt handler function 919 */ 920 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 921 { 922 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 923 uint32_t *vectors = (uint32_t *)SCB->VTOR; 924 #else 925 uint32_t *vectors = (uint32_t*) 0x0U; 926 #endif 927 vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET] = vector; 928 } 929 930 /** 931 \brief Get Interrupt Vector 932 \details Reads an interrupt vector from interrupt vector table. 933 The interrupt number can be positive to specify a device specific interrupt, 934 or negative to specify a processor exception. 935 \param [in] IRQn Interrupt number. 936 \return Address of interrupt handler function 937 */ 938 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 939 { 940 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 941 uint32_t *vectors = (uint32_t *)SCB->VTOR; 942 #else 943 uint32_t *vectors = (uint32_t*) 0x0U; 944 #endif 945 return vectors[(int32_t) IRQn + NVIC_USER_IRQ_OFFSET]; 946 947 } 948 949 /** 950 \brief System Reset 951 \details Initiates a system reset request to reset the MCU. 952 */ 953 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 954 { 955 __DSB(); /* Ensure all outstanding memory accesses included 956 buffered write are completed before reset */ 957 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 958 SCB_AIRCR_SYSRESETREQ_Msk); 959 __DSB(); /* Ensure completion of memory access */ 960 961 for (;;) /* wait until reset */ 962 { 963 __NOP(); 964 } 965 } 966 967 /*@} end of CMSIS_Core_NVICFunctions */ 968 969 /* ########################## MPU functions #################################### */ 970 971 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 972 973 #include "mpu_armv7.h" 974 975 #endif 976 977 /* ########################## FPU functions #################################### */ 978 /** 979 \ingroup CMSIS_Core_FunctionInterface 980 \defgroup CMSIS_Core_FpuFunctions FPU Functions 981 \brief Function that provides FPU type. 982 @{ 983 */ 984 985 /** 986 \brief get FPU type 987 \details returns the FPU type 988 \returns 989 - \b 0: No FPU 990 - \b 1: Single precision FPU 991 - \b 2: Double + Single precision FPU 992 */ 993 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 994 { 995 return 0U; /* No FPU */ 996 } 997 998 /*@} end of CMSIS_Core_FpuFunctions */ 999 1000 /* ################################## SysTick function ############################################ */ 1001 /** 1002 \ingroup CMSIS_Core_FunctionInterface 1003 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 1004 \brief Functions that configure the System. 1005 @{ 1006 */ 1007 1008 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 1009 1010 /** 1011 \brief System Tick Configuration 1012 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 1013 Counter is in free running mode to generate periodic interrupts. 1014 \param [in] ticks Number of ticks between two interrupts. 1015 \return 0 Function succeeded. 1016 \return 1 Function failed. 1017 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 1018 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 1019 must contain a vendor-specific implementation of this function. 1020 */ 1021 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 1022 { 1023 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 1024 { 1025 return (1UL); /* Reload value impossible */ 1026 } 1027 1028 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 1029 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 1030 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 1031 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1032 SysTick_CTRL_TICKINT_Msk | 1033 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1034 return (0UL); /* Function successful */ 1035 } 1036 1037 #endif 1038 1039 /*@} end of CMSIS_Core_SysTickFunctions */ 1040 1041 #ifdef __cplusplus 1042 } 1043 #endif 1044 1045 #endif /* __CORE_CM0PLUS_H_DEPENDANT */ 1046 1047 #endif /* __CMSIS_GENERIC */