Drivers/CMSIS/Include/cmsis_iccarm.h (28193B)
1 /**************************************************************************//** 2 * @file cmsis_iccarm.h 3 * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file 4 * @version V5.0.7 5 * @date 19. June 2018 6 ******************************************************************************/ 7 8 //------------------------------------------------------------------------------ 9 // 10 // Copyright (c) 2017-2018 IAR Systems 11 // 12 // Licensed under the Apache License, Version 2.0 (the "License") 13 // you may not use this file except in compliance with the License. 14 // You may obtain a copy of the License at 15 // http://www.apache.org/licenses/LICENSE-2.0 16 // 17 // Unless required by applicable law or agreed to in writing, software 18 // distributed under the License is distributed on an "AS IS" BASIS, 19 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 // See the License for the specific language governing permissions and 21 // limitations under the License. 22 // 23 //------------------------------------------------------------------------------ 24 25 #ifndef __CMSIS_ICCARM_H__ 26 #define __CMSIS_ICCARM_H__ 27 28 #ifndef __ICCARM__ 29 #error This file should only be compiled by ICCARM 30 #endif 31 32 #pragma system_include 33 34 #define __IAR_FT _Pragma("inline=forced") __intrinsic 35 36 #if (__VER__ >= 8000000) 37 #define __ICCARM_V8 1 38 #else 39 #define __ICCARM_V8 0 40 #endif 41 42 #ifndef __ALIGNED 43 #if __ICCARM_V8 44 #define __ALIGNED(x) __attribute__((aligned(x))) 45 #elif (__VER__ >= 7080000) 46 /* Needs IAR language extensions */ 47 #define __ALIGNED(x) __attribute__((aligned(x))) 48 #else 49 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. 50 #define __ALIGNED(x) 51 #endif 52 #endif 53 54 /* Define compiler macros for CPU architecture, used in CMSIS 5. 55 */ 56 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ 57 /* Macros already defined */ 58 #else 59 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) 60 #define __ARM_ARCH_8M_MAIN__ 1 61 #elif defined(__ARM8M_BASELINE__) 62 #define __ARM_ARCH_8M_BASE__ 1 63 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' 64 #if __ARM_ARCH == 6 65 #define __ARM_ARCH_6M__ 1 66 #elif __ARM_ARCH == 7 67 #if __ARM_FEATURE_DSP 68 #define __ARM_ARCH_7EM__ 1 69 #else 70 #define __ARM_ARCH_7M__ 1 71 #endif 72 #endif /* __ARM_ARCH */ 73 #endif /* __ARM_ARCH_PROFILE == 'M' */ 74 #endif 75 76 /* Alternativ core deduction for older ICCARM's */ 77 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ 78 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) 79 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) 80 #define __ARM_ARCH_6M__ 1 81 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) 82 #define __ARM_ARCH_7M__ 1 83 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) 84 #define __ARM_ARCH_7EM__ 1 85 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) 86 #define __ARM_ARCH_8M_BASE__ 1 87 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) 88 #define __ARM_ARCH_8M_MAIN__ 1 89 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) 90 #define __ARM_ARCH_8M_MAIN__ 1 91 #else 92 #error "Unknown target." 93 #endif 94 #endif 95 96 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 97 #define __IAR_M0_FAMILY 1 98 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 99 #define __IAR_M0_FAMILY 1 100 #else 101 #define __IAR_M0_FAMILY 0 102 #endif 103 104 #ifndef __ASM 105 #define __ASM __asm 106 #endif 107 108 #ifndef __INLINE 109 #define __INLINE inline 110 #endif 111 112 #ifndef __NO_RETURN 113 #if __ICCARM_V8 114 #define __NO_RETURN __attribute__((__noreturn__)) 115 #else 116 #define __NO_RETURN _Pragma("object_attribute=__noreturn") 117 #endif 118 #endif 119 120 #ifndef __PACKED 121 #if __ICCARM_V8 122 #define __PACKED __attribute__((packed, aligned(1))) 123 #else 124 /* Needs IAR language extensions */ 125 #define __PACKED __packed 126 #endif 127 #endif 128 129 #ifndef __PACKED_STRUCT 130 #if __ICCARM_V8 131 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 132 #else 133 /* Needs IAR language extensions */ 134 #define __PACKED_STRUCT __packed struct 135 #endif 136 #endif 137 138 #ifndef __PACKED_UNION 139 #if __ICCARM_V8 140 #define __PACKED_UNION union __attribute__((packed, aligned(1))) 141 #else 142 /* Needs IAR language extensions */ 143 #define __PACKED_UNION __packed union 144 #endif 145 #endif 146 147 #ifndef __RESTRICT 148 #define __RESTRICT __restrict 149 #endif 150 151 #ifndef __STATIC_INLINE 152 #define __STATIC_INLINE static inline 153 #endif 154 155 #ifndef __FORCEINLINE 156 #define __FORCEINLINE _Pragma("inline=forced") 157 #endif 158 159 #ifndef __STATIC_FORCEINLINE 160 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE 161 #endif 162 163 #ifndef __UNALIGNED_UINT16_READ 164 #pragma language=save 165 #pragma language=extended 166 __IAR_FT uint16_t __iar_uint16_read(void const *ptr) 167 { 168 return *(__packed uint16_t*)(ptr); 169 } 170 #pragma language=restore 171 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) 172 #endif 173 174 #ifndef __UNALIGNED_UINT16_WRITE 175 #pragma language=save 176 #pragma language=extended 177 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) 178 { 179 *(__packed uint16_t*)(ptr) = val;; 180 } 181 #pragma language=restore 182 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) 183 #endif 184 185 #ifndef __UNALIGNED_UINT32_READ 186 #pragma language=save 187 #pragma language=extended 188 __IAR_FT uint32_t __iar_uint32_read(void const *ptr) 189 { 190 return *(__packed uint32_t*)(ptr); 191 } 192 #pragma language=restore 193 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) 194 #endif 195 196 #ifndef __UNALIGNED_UINT32_WRITE 197 #pragma language=save 198 #pragma language=extended 199 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) 200 { 201 *(__packed uint32_t*)(ptr) = val;; 202 } 203 #pragma language=restore 204 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) 205 #endif 206 207 #ifndef __UNALIGNED_UINT32 /* deprecated */ 208 #pragma language=save 209 #pragma language=extended 210 __packed struct __iar_u32 { 211 uint32_t v; 212 }; 213 #pragma language=restore 214 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) 215 #endif 216 217 #ifndef __USED 218 #if __ICCARM_V8 219 #define __USED __attribute__((used)) 220 #else 221 #define __USED _Pragma("__root") 222 #endif 223 #endif 224 225 #ifndef __WEAK 226 #if __ICCARM_V8 227 #define __WEAK __attribute__((weak)) 228 #else 229 #define __WEAK _Pragma("__weak") 230 #endif 231 #endif 232 233 #ifndef __ICCARM_INTRINSICS_VERSION__ 234 #define __ICCARM_INTRINSICS_VERSION__ 0 235 #endif 236 237 #if __ICCARM_INTRINSICS_VERSION__ == 2 238 239 #if defined(__CLZ) 240 #undef __CLZ 241 #endif 242 #if defined(__REVSH) 243 #undef __REVSH 244 #endif 245 #if defined(__RBIT) 246 #undef __RBIT 247 #endif 248 #if defined(__SSAT) 249 #undef __SSAT 250 #endif 251 #if defined(__USAT) 252 #undef __USAT 253 #endif 254 255 #include "iccarm_builtin.h" 256 257 #define __disable_fault_irq __iar_builtin_disable_fiq 258 #define __disable_irq __iar_builtin_disable_interrupt 259 #define __enable_fault_irq __iar_builtin_enable_fiq 260 #define __enable_irq __iar_builtin_enable_interrupt 261 #define __arm_rsr __iar_builtin_rsr 262 #define __arm_wsr __iar_builtin_wsr 263 264 265 #define __get_APSR() (__arm_rsr("APSR")) 266 #define __get_BASEPRI() (__arm_rsr("BASEPRI")) 267 #define __get_CONTROL() (__arm_rsr("CONTROL")) 268 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) 269 270 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 271 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 272 #define __get_FPSCR() (__arm_rsr("FPSCR")) 273 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) 274 #else 275 #define __get_FPSCR() ( 0 ) 276 #define __set_FPSCR(VALUE) ((void)VALUE) 277 #endif 278 279 #define __get_IPSR() (__arm_rsr("IPSR")) 280 #define __get_MSP() (__arm_rsr("MSP")) 281 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 282 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 283 // without main extensions, the non-secure MSPLIM is RAZ/WI 284 #define __get_MSPLIM() (0U) 285 #else 286 #define __get_MSPLIM() (__arm_rsr("MSPLIM")) 287 #endif 288 #define __get_PRIMASK() (__arm_rsr("PRIMASK")) 289 #define __get_PSP() (__arm_rsr("PSP")) 290 291 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 292 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 293 // without main extensions, the non-secure PSPLIM is RAZ/WI 294 #define __get_PSPLIM() (0U) 295 #else 296 #define __get_PSPLIM() (__arm_rsr("PSPLIM")) 297 #endif 298 299 #define __get_xPSR() (__arm_rsr("xPSR")) 300 301 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) 302 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) 303 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) 304 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) 305 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) 306 307 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 308 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 309 // without main extensions, the non-secure MSPLIM is RAZ/WI 310 #define __set_MSPLIM(VALUE) ((void)(VALUE)) 311 #else 312 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) 313 #endif 314 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) 315 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) 316 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 317 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 318 // without main extensions, the non-secure PSPLIM is RAZ/WI 319 #define __set_PSPLIM(VALUE) ((void)(VALUE)) 320 #else 321 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) 322 #endif 323 324 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) 325 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) 326 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) 327 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) 328 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) 329 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) 330 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) 331 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) 332 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) 333 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) 334 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) 335 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) 336 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) 337 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) 338 339 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 340 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 341 // without main extensions, the non-secure PSPLIM is RAZ/WI 342 #define __TZ_get_PSPLIM_NS() (0U) 343 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) 344 #else 345 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) 346 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) 347 #endif 348 349 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) 350 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) 351 352 #define __NOP __iar_builtin_no_operation 353 354 #define __CLZ __iar_builtin_CLZ 355 #define __CLREX __iar_builtin_CLREX 356 357 #define __DMB __iar_builtin_DMB 358 #define __DSB __iar_builtin_DSB 359 #define __ISB __iar_builtin_ISB 360 361 #define __LDREXB __iar_builtin_LDREXB 362 #define __LDREXH __iar_builtin_LDREXH 363 #define __LDREXW __iar_builtin_LDREX 364 365 #define __RBIT __iar_builtin_RBIT 366 #define __REV __iar_builtin_REV 367 #define __REV16 __iar_builtin_REV16 368 369 __IAR_FT int16_t __REVSH(int16_t val) 370 { 371 return (int16_t) __iar_builtin_REVSH(val); 372 } 373 374 #define __ROR __iar_builtin_ROR 375 #define __RRX __iar_builtin_RRX 376 377 #define __SEV __iar_builtin_SEV 378 379 #if !__IAR_M0_FAMILY 380 #define __SSAT __iar_builtin_SSAT 381 #endif 382 383 #define __STREXB __iar_builtin_STREXB 384 #define __STREXH __iar_builtin_STREXH 385 #define __STREXW __iar_builtin_STREX 386 387 #if !__IAR_M0_FAMILY 388 #define __USAT __iar_builtin_USAT 389 #endif 390 391 #define __WFE __iar_builtin_WFE 392 #define __WFI __iar_builtin_WFI 393 394 #if __ARM_MEDIA__ 395 #define __SADD8 __iar_builtin_SADD8 396 #define __QADD8 __iar_builtin_QADD8 397 #define __SHADD8 __iar_builtin_SHADD8 398 #define __UADD8 __iar_builtin_UADD8 399 #define __UQADD8 __iar_builtin_UQADD8 400 #define __UHADD8 __iar_builtin_UHADD8 401 #define __SSUB8 __iar_builtin_SSUB8 402 #define __QSUB8 __iar_builtin_QSUB8 403 #define __SHSUB8 __iar_builtin_SHSUB8 404 #define __USUB8 __iar_builtin_USUB8 405 #define __UQSUB8 __iar_builtin_UQSUB8 406 #define __UHSUB8 __iar_builtin_UHSUB8 407 #define __SADD16 __iar_builtin_SADD16 408 #define __QADD16 __iar_builtin_QADD16 409 #define __SHADD16 __iar_builtin_SHADD16 410 #define __UADD16 __iar_builtin_UADD16 411 #define __UQADD16 __iar_builtin_UQADD16 412 #define __UHADD16 __iar_builtin_UHADD16 413 #define __SSUB16 __iar_builtin_SSUB16 414 #define __QSUB16 __iar_builtin_QSUB16 415 #define __SHSUB16 __iar_builtin_SHSUB16 416 #define __USUB16 __iar_builtin_USUB16 417 #define __UQSUB16 __iar_builtin_UQSUB16 418 #define __UHSUB16 __iar_builtin_UHSUB16 419 #define __SASX __iar_builtin_SASX 420 #define __QASX __iar_builtin_QASX 421 #define __SHASX __iar_builtin_SHASX 422 #define __UASX __iar_builtin_UASX 423 #define __UQASX __iar_builtin_UQASX 424 #define __UHASX __iar_builtin_UHASX 425 #define __SSAX __iar_builtin_SSAX 426 #define __QSAX __iar_builtin_QSAX 427 #define __SHSAX __iar_builtin_SHSAX 428 #define __USAX __iar_builtin_USAX 429 #define __UQSAX __iar_builtin_UQSAX 430 #define __UHSAX __iar_builtin_UHSAX 431 #define __USAD8 __iar_builtin_USAD8 432 #define __USADA8 __iar_builtin_USADA8 433 #define __SSAT16 __iar_builtin_SSAT16 434 #define __USAT16 __iar_builtin_USAT16 435 #define __UXTB16 __iar_builtin_UXTB16 436 #define __UXTAB16 __iar_builtin_UXTAB16 437 #define __SXTB16 __iar_builtin_SXTB16 438 #define __SXTAB16 __iar_builtin_SXTAB16 439 #define __SMUAD __iar_builtin_SMUAD 440 #define __SMUADX __iar_builtin_SMUADX 441 #define __SMMLA __iar_builtin_SMMLA 442 #define __SMLAD __iar_builtin_SMLAD 443 #define __SMLADX __iar_builtin_SMLADX 444 #define __SMLALD __iar_builtin_SMLALD 445 #define __SMLALDX __iar_builtin_SMLALDX 446 #define __SMUSD __iar_builtin_SMUSD 447 #define __SMUSDX __iar_builtin_SMUSDX 448 #define __SMLSD __iar_builtin_SMLSD 449 #define __SMLSDX __iar_builtin_SMLSDX 450 #define __SMLSLD __iar_builtin_SMLSLD 451 #define __SMLSLDX __iar_builtin_SMLSLDX 452 #define __SEL __iar_builtin_SEL 453 #define __QADD __iar_builtin_QADD 454 #define __QSUB __iar_builtin_QSUB 455 #define __PKHBT __iar_builtin_PKHBT 456 #define __PKHTB __iar_builtin_PKHTB 457 #endif 458 459 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ 460 461 #if __IAR_M0_FAMILY 462 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ 463 #define __CLZ __cmsis_iar_clz_not_active 464 #define __SSAT __cmsis_iar_ssat_not_active 465 #define __USAT __cmsis_iar_usat_not_active 466 #define __RBIT __cmsis_iar_rbit_not_active 467 #define __get_APSR __cmsis_iar_get_APSR_not_active 468 #endif 469 470 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 471 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) 472 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active 473 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active 474 #endif 475 476 #ifdef __INTRINSICS_INCLUDED 477 #error intrinsics.h is already included previously! 478 #endif 479 480 #include <intrinsics.h> 481 482 #if __IAR_M0_FAMILY 483 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ 484 #undef __CLZ 485 #undef __SSAT 486 #undef __USAT 487 #undef __RBIT 488 #undef __get_APSR 489 490 __STATIC_INLINE uint8_t __CLZ(uint32_t data) 491 { 492 if (data == 0U) { return 32U; } 493 494 uint32_t count = 0U; 495 uint32_t mask = 0x80000000U; 496 497 while ((data & mask) == 0U) 498 { 499 count += 1U; 500 mask = mask >> 1U; 501 } 502 return count; 503 } 504 505 __STATIC_INLINE uint32_t __RBIT(uint32_t v) 506 { 507 uint8_t sc = 31U; 508 uint32_t r = v; 509 for (v >>= 1U; v; v >>= 1U) 510 { 511 r <<= 1U; 512 r |= v & 1U; 513 sc--; 514 } 515 return (r << sc); 516 } 517 518 __STATIC_INLINE uint32_t __get_APSR(void) 519 { 520 uint32_t res; 521 __asm("MRS %0,APSR" : "=r" (res)); 522 return res; 523 } 524 525 #endif 526 527 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 528 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) 529 #undef __get_FPSCR 530 #undef __set_FPSCR 531 #define __get_FPSCR() (0) 532 #define __set_FPSCR(VALUE) ((void)VALUE) 533 #endif 534 535 #pragma diag_suppress=Pe940 536 #pragma diag_suppress=Pe177 537 538 #define __enable_irq __enable_interrupt 539 #define __disable_irq __disable_interrupt 540 #define __NOP __no_operation 541 542 #define __get_xPSR __get_PSR 543 544 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) 545 546 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) 547 { 548 return __LDREX((unsigned long*) ptr); 549 } 550 551 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) 552 { 553 return __STREX(value, (unsigned long*) ptr); 554 } 555 #endif 556 557 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ 558 #if (__CORTEX_M >= 0x03) 559 560 __IAR_FT uint32_t __RRX(uint32_t value) 561 { 562 uint32_t result; 563 __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); 564 return(result); 565 } 566 567 __IAR_FT void __set_BASEPRI_MAX(uint32_t value) 568 { 569 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); 570 } 571 572 573 #define __enable_fault_irq __enable_fiq 574 #define __disable_fault_irq __disable_fiq 575 576 577 #endif /* (__CORTEX_M >= 0x03) */ 578 579 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) 580 { 581 return (op1 >> op2) | (op1 << ((sizeof(op1) * 8) - op2)); 582 } 583 584 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 585 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 586 587 __IAR_FT uint32_t __get_MSPLIM(void) 588 { 589 uint32_t res; 590 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 591 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 592 // without main extensions, the non-secure MSPLIM is RAZ/WI 593 res = 0U; 594 #else 595 __asm volatile("MRS %0,MSPLIM" : "=r" (res)); 596 #endif 597 return res; 598 } 599 600 __IAR_FT void __set_MSPLIM(uint32_t value) 601 { 602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 603 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 604 // without main extensions, the non-secure MSPLIM is RAZ/WI 605 (void)value; 606 #else 607 __asm volatile("MSR MSPLIM,%0" :: "r" (value)); 608 #endif 609 } 610 611 __IAR_FT uint32_t __get_PSPLIM(void) 612 { 613 uint32_t res; 614 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 615 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 616 // without main extensions, the non-secure PSPLIM is RAZ/WI 617 res = 0U; 618 #else 619 __asm volatile("MRS %0,PSPLIM" : "=r" (res)); 620 #endif 621 return res; 622 } 623 624 __IAR_FT void __set_PSPLIM(uint32_t value) 625 { 626 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 627 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 628 // without main extensions, the non-secure PSPLIM is RAZ/WI 629 (void)value; 630 #else 631 __asm volatile("MSR PSPLIM,%0" :: "r" (value)); 632 #endif 633 } 634 635 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) 636 { 637 uint32_t res; 638 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); 639 return res; 640 } 641 642 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) 643 { 644 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); 645 } 646 647 __IAR_FT uint32_t __TZ_get_PSP_NS(void) 648 { 649 uint32_t res; 650 __asm volatile("MRS %0,PSP_NS" : "=r" (res)); 651 return res; 652 } 653 654 __IAR_FT void __TZ_set_PSP_NS(uint32_t value) 655 { 656 __asm volatile("MSR PSP_NS,%0" :: "r" (value)); 657 } 658 659 __IAR_FT uint32_t __TZ_get_MSP_NS(void) 660 { 661 uint32_t res; 662 __asm volatile("MRS %0,MSP_NS" : "=r" (res)); 663 return res; 664 } 665 666 __IAR_FT void __TZ_set_MSP_NS(uint32_t value) 667 { 668 __asm volatile("MSR MSP_NS,%0" :: "r" (value)); 669 } 670 671 __IAR_FT uint32_t __TZ_get_SP_NS(void) 672 { 673 uint32_t res; 674 __asm volatile("MRS %0,SP_NS" : "=r" (res)); 675 return res; 676 } 677 __IAR_FT void __TZ_set_SP_NS(uint32_t value) 678 { 679 __asm volatile("MSR SP_NS,%0" :: "r" (value)); 680 } 681 682 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) 683 { 684 uint32_t res; 685 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); 686 return res; 687 } 688 689 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) 690 { 691 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); 692 } 693 694 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) 695 { 696 uint32_t res; 697 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); 698 return res; 699 } 700 701 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) 702 { 703 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); 704 } 705 706 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) 707 { 708 uint32_t res; 709 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); 710 return res; 711 } 712 713 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) 714 { 715 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); 716 } 717 718 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) 719 { 720 uint32_t res; 721 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 722 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 723 // without main extensions, the non-secure PSPLIM is RAZ/WI 724 res = 0U; 725 #else 726 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); 727 #endif 728 return res; 729 } 730 731 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) 732 { 733 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 734 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) 735 // without main extensions, the non-secure PSPLIM is RAZ/WI 736 (void)value; 737 #else 738 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); 739 #endif 740 } 741 742 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) 743 { 744 uint32_t res; 745 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); 746 return res; 747 } 748 749 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) 750 { 751 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); 752 } 753 754 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ 755 756 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ 757 758 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) 759 760 #if __IAR_M0_FAMILY 761 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) 762 { 763 if ((sat >= 1U) && (sat <= 32U)) 764 { 765 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 766 const int32_t min = -1 - max ; 767 if (val > max) 768 { 769 return max; 770 } 771 else if (val < min) 772 { 773 return min; 774 } 775 } 776 return val; 777 } 778 779 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) 780 { 781 if (sat <= 31U) 782 { 783 const uint32_t max = ((1U << sat) - 1U); 784 if (val > (int32_t)max) 785 { 786 return max; 787 } 788 else if (val < 0) 789 { 790 return 0U; 791 } 792 } 793 return (uint32_t)val; 794 } 795 #endif 796 797 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ 798 799 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) 800 { 801 uint32_t res; 802 __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 803 return ((uint8_t)res); 804 } 805 806 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) 807 { 808 uint32_t res; 809 __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 810 return ((uint16_t)res); 811 } 812 813 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) 814 { 815 uint32_t res; 816 __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); 817 return res; 818 } 819 820 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) 821 { 822 __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); 823 } 824 825 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) 826 { 827 __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); 828 } 829 830 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) 831 { 832 __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); 833 } 834 835 #endif /* (__CORTEX_M >= 0x03) */ 836 837 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 838 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 839 840 841 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) 842 { 843 uint32_t res; 844 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 845 return ((uint8_t)res); 846 } 847 848 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) 849 { 850 uint32_t res; 851 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 852 return ((uint16_t)res); 853 } 854 855 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) 856 { 857 uint32_t res; 858 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 859 return res; 860 } 861 862 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) 863 { 864 __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); 865 } 866 867 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) 868 { 869 __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); 870 } 871 872 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) 873 { 874 __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); 875 } 876 877 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) 878 { 879 uint32_t res; 880 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 881 return ((uint8_t)res); 882 } 883 884 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) 885 { 886 uint32_t res; 887 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 888 return ((uint16_t)res); 889 } 890 891 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) 892 { 893 uint32_t res; 894 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); 895 return res; 896 } 897 898 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) 899 { 900 uint32_t res; 901 __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); 902 return res; 903 } 904 905 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) 906 { 907 uint32_t res; 908 __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); 909 return res; 910 } 911 912 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 913 { 914 uint32_t res; 915 __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); 916 return res; 917 } 918 919 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ 920 921 #undef __IAR_FT 922 #undef __IAR_M0_FAMILY 923 #undef __ICCARM_V8 924 925 #pragma diag_default=Pe940 926 #pragma diag_default=Pe177 927 928 #endif /* __CMSIS_ICCARM_H__ */