Drivers/CMSIS/Include/cmsis_armcc.h (27575B)
1 /**************************************************************************//** 2 * @file cmsis_armcc.h 3 * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file 4 * @version V5.0.4 5 * @date 10. January 2018 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 * 10 * SPDX-License-Identifier: Apache-2.0 11 * 12 * Licensed under the Apache License, Version 2.0 (the License); you may 13 * not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 */ 24 25 #ifndef __CMSIS_ARMCC_H 26 #define __CMSIS_ARMCC_H 27 28 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) 29 #error "Please use Arm Compiler Toolchain V4.0.677 or later!" 30 #endif 31 32 /* CMSIS compiler control architecture macros */ 33 #if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ 34 (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) 35 #define __ARM_ARCH_6M__ 1 36 #endif 37 38 #if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) 39 #define __ARM_ARCH_7M__ 1 40 #endif 41 42 #if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) 43 #define __ARM_ARCH_7EM__ 1 44 #endif 45 46 /* __ARM_ARCH_8M_BASE__ not applicable */ 47 /* __ARM_ARCH_8M_MAIN__ not applicable */ 48 49 /* CMSIS compiler specific defines */ 50 #ifndef __ASM 51 #define __ASM __asm 52 #endif 53 #ifndef __INLINE 54 #define __INLINE __inline 55 #endif 56 #ifndef __STATIC_INLINE 57 #define __STATIC_INLINE static __inline 58 #endif 59 #ifndef __STATIC_FORCEINLINE 60 #define __STATIC_FORCEINLINE static __forceinline 61 #endif 62 #ifndef __NO_RETURN 63 #define __NO_RETURN __declspec(noreturn) 64 #endif 65 #ifndef __USED 66 #define __USED __attribute__((used)) 67 #endif 68 #ifndef __WEAK 69 #define __WEAK __attribute__((weak)) 70 #endif 71 #ifndef __PACKED 72 #define __PACKED __attribute__((packed)) 73 #endif 74 #ifndef __PACKED_STRUCT 75 #define __PACKED_STRUCT __packed struct 76 #endif 77 #ifndef __PACKED_UNION 78 #define __PACKED_UNION __packed union 79 #endif 80 #ifndef __UNALIGNED_UINT32 /* deprecated */ 81 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) 82 #endif 83 #ifndef __UNALIGNED_UINT16_WRITE 84 #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) 85 #endif 86 #ifndef __UNALIGNED_UINT16_READ 87 #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) 88 #endif 89 #ifndef __UNALIGNED_UINT32_WRITE 90 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) 91 #endif 92 #ifndef __UNALIGNED_UINT32_READ 93 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) 94 #endif 95 #ifndef __ALIGNED 96 #define __ALIGNED(x) __attribute__((aligned(x))) 97 #endif 98 #ifndef __RESTRICT 99 #define __RESTRICT __restrict 100 #endif 101 102 /* ########################### Core Function Access ########################### */ 103 /** \ingroup CMSIS_Core_FunctionInterface 104 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 105 @{ 106 */ 107 108 /** 109 \brief Enable IRQ Interrupts 110 \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 111 Can only be executed in Privileged modes. 112 */ 113 /* intrinsic void __enable_irq(); */ 114 115 /** 116 \brief Disable IRQ Interrupts 117 \details Disables IRQ interrupts by setting the I-bit in the CPSR. 118 Can only be executed in Privileged modes. 119 */ 120 /* intrinsic void __disable_irq(); */ 121 122 /** 123 \brief Get Control Register 124 \details Returns the content of the Control Register. 125 \return Control Register value 126 */ 127 __STATIC_INLINE uint32_t __get_CONTROL(void) 128 { 129 register uint32_t __regControl __ASM("control"); 130 return (__regControl); 131 } 132 133 /** 134 \brief Set Control Register 135 \details Writes the given value to the Control Register. 136 \param [in] control Control Register value to set 137 */ 138 __STATIC_INLINE void __set_CONTROL(uint32_t control) 139 { 140 register uint32_t __regControl __ASM("control"); 141 __regControl = control; 142 } 143 144 /** 145 \brief Get IPSR Register 146 \details Returns the content of the IPSR Register. 147 \return IPSR Register value 148 */ 149 __STATIC_INLINE uint32_t __get_IPSR(void) 150 { 151 register uint32_t __regIPSR __ASM("ipsr"); 152 return (__regIPSR); 153 } 154 155 /** 156 \brief Get APSR Register 157 \details Returns the content of the APSR Register. 158 \return APSR Register value 159 */ 160 __STATIC_INLINE uint32_t __get_APSR(void) 161 { 162 register uint32_t __regAPSR __ASM("apsr"); 163 return (__regAPSR); 164 } 165 166 /** 167 \brief Get xPSR Register 168 \details Returns the content of the xPSR Register. 169 \return xPSR Register value 170 */ 171 __STATIC_INLINE uint32_t __get_xPSR(void) 172 { 173 register uint32_t __regXPSR __ASM("xpsr"); 174 return (__regXPSR); 175 } 176 177 /** 178 \brief Get Process Stack Pointer 179 \details Returns the current value of the Process Stack Pointer (PSP). 180 \return PSP Register value 181 */ 182 __STATIC_INLINE uint32_t __get_PSP(void) 183 { 184 register uint32_t __regProcessStackPointer __ASM("psp"); 185 return (__regProcessStackPointer); 186 } 187 188 /** 189 \brief Set Process Stack Pointer 190 \details Assigns the given value to the Process Stack Pointer (PSP). 191 \param [in] topOfProcStack Process Stack Pointer value to set 192 */ 193 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 194 { 195 register uint32_t __regProcessStackPointer __ASM("psp"); 196 __regProcessStackPointer = topOfProcStack; 197 } 198 199 /** 200 \brief Get Main Stack Pointer 201 \details Returns the current value of the Main Stack Pointer (MSP). 202 \return MSP Register value 203 */ 204 __STATIC_INLINE uint32_t __get_MSP(void) 205 { 206 register uint32_t __regMainStackPointer __ASM("msp"); 207 return (__regMainStackPointer); 208 } 209 210 /** 211 \brief Set Main Stack Pointer 212 \details Assigns the given value to the Main Stack Pointer (MSP). 213 \param [in] topOfMainStack Main Stack Pointer value to set 214 */ 215 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 216 { 217 register uint32_t __regMainStackPointer __ASM("msp"); 218 __regMainStackPointer = topOfMainStack; 219 } 220 221 /** 222 \brief Get Priority Mask 223 \details Returns the current state of the priority mask bit from the Priority Mask Register. 224 \return Priority Mask value 225 */ 226 __STATIC_INLINE uint32_t __get_PRIMASK(void) 227 { 228 register uint32_t __regPriMask __ASM("primask"); 229 return (__regPriMask); 230 } 231 232 /** 233 \brief Set Priority Mask 234 \details Assigns the given value to the Priority Mask Register. 235 \param [in] priMask Priority Mask 236 */ 237 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 238 { 239 register uint32_t __regPriMask __ASM("primask"); 240 __regPriMask = (priMask); 241 } 242 243 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 244 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 245 246 /** 247 \brief Enable FIQ 248 \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 249 Can only be executed in Privileged modes. 250 */ 251 #define __enable_fault_irq __enable_fiq 252 253 /** 254 \brief Disable FIQ 255 \details Disables FIQ interrupts by setting the F-bit in the CPSR. 256 Can only be executed in Privileged modes. 257 */ 258 #define __disable_fault_irq __disable_fiq 259 260 /** 261 \brief Get Base Priority 262 \details Returns the current value of the Base Priority register. 263 \return Base Priority register value 264 */ 265 __STATIC_INLINE uint32_t __get_BASEPRI(void) 266 { 267 register uint32_t __regBasePri __ASM("basepri"); 268 return (__regBasePri); 269 } 270 271 /** 272 \brief Set Base Priority 273 \details Assigns the given value to the Base Priority register. 274 \param [in] basePri Base Priority value to set 275 */ 276 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) 277 { 278 register uint32_t __regBasePri __ASM("basepri"); 279 __regBasePri = (basePri & 0xFFU); 280 } 281 282 /** 283 \brief Set Base Priority with condition 284 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, 285 or the new value increases the BASEPRI priority level. 286 \param [in] basePri Base Priority value to set 287 */ 288 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) 289 { 290 register uint32_t __regBasePriMax __ASM("basepri_max"); 291 __regBasePriMax = (basePri & 0xFFU); 292 } 293 294 /** 295 \brief Get Fault Mask 296 \details Returns the current value of the Fault Mask register. 297 \return Fault Mask register value 298 */ 299 __STATIC_INLINE uint32_t __get_FAULTMASK(void) 300 { 301 register uint32_t __regFaultMask __ASM("faultmask"); 302 return (__regFaultMask); 303 } 304 305 /** 306 \brief Set Fault Mask 307 \details Assigns the given value to the Fault Mask register. 308 \param [in] faultMask Fault Mask value to set 309 */ 310 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 311 { 312 register uint32_t __regFaultMask __ASM("faultmask"); 313 __regFaultMask = (faultMask & (uint32_t) 1U); 314 } 315 316 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 317 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 318 319 /** 320 \brief Get FPSCR 321 \details Returns the current value of the Floating Point Status/Control register. 322 \return Floating Point Status/Control register value 323 */ 324 __STATIC_INLINE uint32_t __get_FPSCR(void) 325 { 326 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 327 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 328 register uint32_t __regfpscr __ASM("fpscr"); 329 return(__regfpscr); 330 #else 331 return (0U); 332 #endif 333 } 334 335 /** 336 \brief Set FPSCR 337 \details Assigns the given value to the Floating Point Status/Control register. 338 \param [in] fpscr Floating Point Status/Control value to set 339 */ 340 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 341 { 342 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 343 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 344 register uint32_t __regfpscr __ASM("fpscr"); 345 __regfpscr = (fpscr); 346 #else 347 (void) fpscr; 348 #endif 349 } 350 351 /*@} end of CMSIS_Core_RegAccFunctions */ 352 353 /* ########################## Core Instruction Access ######################### */ 354 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 355 Access to dedicated instructions 356 @{ 357 */ 358 359 /** 360 \brief No Operation 361 \details No Operation does nothing. This instruction can be used for code alignment purposes. 362 */ 363 #define __NOP __nop 364 365 /** 366 \brief Wait For Interrupt 367 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. 368 */ 369 #define __WFI __wfi 370 371 /** 372 \brief Wait For Event 373 \details Wait For Event is a hint instruction that permits the processor to enter 374 a low-power state until one of a number of events occurs. 375 */ 376 #define __WFE __wfe 377 378 /** 379 \brief Send Event 380 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 381 */ 382 #define __SEV __sev 383 384 /** 385 \brief Instruction Synchronization Barrier 386 \details Instruction Synchronization Barrier flushes the pipeline in the processor, 387 so that all instructions following the ISB are fetched from cache or memory, 388 after the instruction has been completed. 389 */ 390 #define __ISB() do {\ 391 __schedule_barrier();\ 392 __isb(0xF);\ 393 __schedule_barrier();\ 394 } while (0U) 395 396 /** 397 \brief Data Synchronization Barrier 398 \details Acts as a special kind of Data Memory Barrier. 399 It completes when all explicit memory accesses before this instruction complete. 400 */ 401 #define __DSB() do {\ 402 __schedule_barrier();\ 403 __dsb(0xF);\ 404 __schedule_barrier();\ 405 } while (0U) 406 407 /** 408 \brief Data Memory Barrier 409 \details Ensures the apparent order of the explicit memory operations before 410 and after the instruction, without ensuring their completion. 411 */ 412 #define __DMB() do {\ 413 __schedule_barrier();\ 414 __dmb(0xF);\ 415 __schedule_barrier();\ 416 } while (0U) 417 418 /** 419 \brief Reverse byte order (32 bit) 420 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. 421 \param [in] value Value to reverse 422 \return Reversed value 423 */ 424 #define __REV __rev 425 426 /** 427 \brief Reverse byte order (16 bit) 428 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. 429 \param [in] value Value to reverse 430 \return Reversed value 431 */ 432 #ifndef __NO_EMBEDDED_ASM 433 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) 434 { 435 rev16 r0, r0 436 bx lr 437 } 438 #endif 439 440 /** 441 \brief Reverse byte order (16 bit) 442 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. 443 \param [in] value Value to reverse 444 \return Reversed value 445 */ 446 #ifndef __NO_EMBEDDED_ASM 447 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) 448 { 449 revsh r0, r0 450 bx lr 451 } 452 #endif 453 454 /** 455 \brief Rotate Right in unsigned value (32 bit) 456 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 457 \param [in] op1 Value to rotate 458 \param [in] op2 Number of Bits to rotate 459 \return Rotated value 460 */ 461 #define __ROR __ror 462 463 /** 464 \brief Breakpoint 465 \details Causes the processor to enter Debug state. 466 Debug tools can use this to investigate system state when the instruction at a particular address is reached. 467 \param [in] value is ignored by the processor. 468 If required, a debugger can use it to store additional information about the breakpoint. 469 */ 470 #define __BKPT(value) __breakpoint(value) 471 472 /** 473 \brief Reverse bit order of value 474 \details Reverses the bit order of the given value. 475 \param [in] value Value to reverse 476 \return Reversed value 477 */ 478 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 479 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 480 #define __RBIT __rbit 481 #else 482 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) 483 { 484 uint32_t result; 485 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 486 487 result = value; /* r will be reversed bits of v; first get LSB of v */ 488 for (value >>= 1U; value != 0U; value >>= 1U) 489 { 490 result <<= 1U; 491 result |= value & 1U; 492 s--; 493 } 494 result <<= s; /* shift when v's highest bits are zero */ 495 return result; 496 } 497 #endif 498 499 /** 500 \brief Count leading zeros 501 \details Counts the number of leading zeros of a data value. 502 \param [in] value Value to count the leading zeros 503 \return number of leading zeros in value 504 */ 505 #define __CLZ __clz 506 507 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 508 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 509 510 /** 511 \brief LDR Exclusive (8 bit) 512 \details Executes a exclusive LDR instruction for 8 bit value. 513 \param [in] ptr Pointer to data 514 \return value of type uint8_t at (*ptr) 515 */ 516 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 517 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) 518 #else 519 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") 520 #endif 521 522 /** 523 \brief LDR Exclusive (16 bit) 524 \details Executes a exclusive LDR instruction for 16 bit values. 525 \param [in] ptr Pointer to data 526 \return value of type uint16_t at (*ptr) 527 */ 528 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 529 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) 530 #else 531 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") 532 #endif 533 534 /** 535 \brief LDR Exclusive (32 bit) 536 \details Executes a exclusive LDR instruction for 32 bit values. 537 \param [in] ptr Pointer to data 538 \return value of type uint32_t at (*ptr) 539 */ 540 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 541 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) 542 #else 543 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") 544 #endif 545 546 /** 547 \brief STR Exclusive (8 bit) 548 \details Executes a exclusive STR instruction for 8 bit values. 549 \param [in] value Value to store 550 \param [in] ptr Pointer to location 551 \return 0 Function succeeded 552 \return 1 Function failed 553 */ 554 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 555 #define __STREXB(value, ptr) __strex(value, ptr) 556 #else 557 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 558 #endif 559 560 /** 561 \brief STR Exclusive (16 bit) 562 \details Executes a exclusive STR instruction for 16 bit values. 563 \param [in] value Value to store 564 \param [in] ptr Pointer to location 565 \return 0 Function succeeded 566 \return 1 Function failed 567 */ 568 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 569 #define __STREXH(value, ptr) __strex(value, ptr) 570 #else 571 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 572 #endif 573 574 /** 575 \brief STR Exclusive (32 bit) 576 \details Executes a exclusive STR instruction for 32 bit values. 577 \param [in] value Value to store 578 \param [in] ptr Pointer to location 579 \return 0 Function succeeded 580 \return 1 Function failed 581 */ 582 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) 583 #define __STREXW(value, ptr) __strex(value, ptr) 584 #else 585 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") 586 #endif 587 588 /** 589 \brief Remove the exclusive lock 590 \details Removes the exclusive lock which is created by LDREX. 591 */ 592 #define __CLREX __clrex 593 594 /** 595 \brief Signed Saturate 596 \details Saturates a signed value. 597 \param [in] value Value to be saturated 598 \param [in] sat Bit position to saturate to (1..32) 599 \return Saturated value 600 */ 601 #define __SSAT __ssat 602 603 /** 604 \brief Unsigned Saturate 605 \details Saturates an unsigned value. 606 \param [in] value Value to be saturated 607 \param [in] sat Bit position to saturate to (0..31) 608 \return Saturated value 609 */ 610 #define __USAT __usat 611 612 /** 613 \brief Rotate Right with Extend (32 bit) 614 \details Moves each bit of a bitstring right by one bit. 615 The carry input is shifted in at the left end of the bitstring. 616 \param [in] value Value to rotate 617 \return Rotated value 618 */ 619 #ifndef __NO_EMBEDDED_ASM 620 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) 621 { 622 rrx r0, r0 623 bx lr 624 } 625 #endif 626 627 /** 628 \brief LDRT Unprivileged (8 bit) 629 \details Executes a Unprivileged LDRT instruction for 8 bit value. 630 \param [in] ptr Pointer to data 631 \return value of type uint8_t at (*ptr) 632 */ 633 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) 634 635 /** 636 \brief LDRT Unprivileged (16 bit) 637 \details Executes a Unprivileged LDRT instruction for 16 bit values. 638 \param [in] ptr Pointer to data 639 \return value of type uint16_t at (*ptr) 640 */ 641 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) 642 643 /** 644 \brief LDRT Unprivileged (32 bit) 645 \details Executes a Unprivileged LDRT instruction for 32 bit values. 646 \param [in] ptr Pointer to data 647 \return value of type uint32_t at (*ptr) 648 */ 649 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) 650 651 /** 652 \brief STRT Unprivileged (8 bit) 653 \details Executes a Unprivileged STRT instruction for 8 bit values. 654 \param [in] value Value to store 655 \param [in] ptr Pointer to location 656 */ 657 #define __STRBT(value, ptr) __strt(value, ptr) 658 659 /** 660 \brief STRT Unprivileged (16 bit) 661 \details Executes a Unprivileged STRT instruction for 16 bit values. 662 \param [in] value Value to store 663 \param [in] ptr Pointer to location 664 */ 665 #define __STRHT(value, ptr) __strt(value, ptr) 666 667 /** 668 \brief STRT Unprivileged (32 bit) 669 \details Executes a Unprivileged STRT instruction for 32 bit values. 670 \param [in] value Value to store 671 \param [in] ptr Pointer to location 672 */ 673 #define __STRT(value, ptr) __strt(value, ptr) 674 675 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 676 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 677 678 /** 679 \brief Signed Saturate 680 \details Saturates a signed value. 681 \param [in] value Value to be saturated 682 \param [in] sat Bit position to saturate to (1..32) 683 \return Saturated value 684 */ 685 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) 686 { 687 if ((sat >= 1U) && (sat <= 32U)) 688 { 689 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 690 const int32_t min = -1 - max ; 691 if (val > max) 692 { 693 return max; 694 } 695 else if (val < min) 696 { 697 return min; 698 } 699 } 700 return val; 701 } 702 703 /** 704 \brief Unsigned Saturate 705 \details Saturates an unsigned value. 706 \param [in] value Value to be saturated 707 \param [in] sat Bit position to saturate to (0..31) 708 \return Saturated value 709 */ 710 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) 711 { 712 if (sat <= 31U) 713 { 714 const uint32_t max = ((1U << sat) - 1U); 715 if (val > (int32_t)max) 716 { 717 return max; 718 } 719 else if (val < 0) 720 { 721 return 0U; 722 } 723 } 724 return (uint32_t)val; 725 } 726 727 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 728 (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 729 730 /*@}*//* end of group CMSIS_Core_InstructionInterface */ 731 732 /* ################### Compiler specific Intrinsics ########################### */ 733 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics 734 Access to dedicated SIMD instructions 735 @{ 736 */ 737 738 #if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) 739 740 #define __SADD8 __sadd8 741 #define __QADD8 __qadd8 742 #define __SHADD8 __shadd8 743 #define __UADD8 __uadd8 744 #define __UQADD8 __uqadd8 745 #define __UHADD8 __uhadd8 746 #define __SSUB8 __ssub8 747 #define __QSUB8 __qsub8 748 #define __SHSUB8 __shsub8 749 #define __USUB8 __usub8 750 #define __UQSUB8 __uqsub8 751 #define __UHSUB8 __uhsub8 752 #define __SADD16 __sadd16 753 #define __QADD16 __qadd16 754 #define __SHADD16 __shadd16 755 #define __UADD16 __uadd16 756 #define __UQADD16 __uqadd16 757 #define __UHADD16 __uhadd16 758 #define __SSUB16 __ssub16 759 #define __QSUB16 __qsub16 760 #define __SHSUB16 __shsub16 761 #define __USUB16 __usub16 762 #define __UQSUB16 __uqsub16 763 #define __UHSUB16 __uhsub16 764 #define __SASX __sasx 765 #define __QASX __qasx 766 #define __SHASX __shasx 767 #define __UASX __uasx 768 #define __UQASX __uqasx 769 #define __UHASX __uhasx 770 #define __SSAX __ssax 771 #define __QSAX __qsax 772 #define __SHSAX __shsax 773 #define __USAX __usax 774 #define __UQSAX __uqsax 775 #define __UHSAX __uhsax 776 #define __USAD8 __usad8 777 #define __USADA8 __usada8 778 #define __SSAT16 __ssat16 779 #define __USAT16 __usat16 780 #define __UXTB16 __uxtb16 781 #define __UXTAB16 __uxtab16 782 #define __SXTB16 __sxtb16 783 #define __SXTAB16 __sxtab16 784 #define __SMUAD __smuad 785 #define __SMUADX __smuadx 786 #define __SMLAD __smlad 787 #define __SMLADX __smladx 788 #define __SMLALD __smlald 789 #define __SMLALDX __smlaldx 790 #define __SMUSD __smusd 791 #define __SMUSDX __smusdx 792 #define __SMLSD __smlsd 793 #define __SMLSDX __smlsdx 794 #define __SMLSLD __smlsld 795 #define __SMLSLDX __smlsldx 796 #define __SEL __sel 797 #define __QADD __qadd 798 #define __QSUB __qsub 799 800 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ 801 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) 802 803 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ 804 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) 805 806 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ 807 ((int64_t)(ARG3) << 32U) ) >> 32U)) 808 809 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ 810 /*@} end of group CMSIS_SIMD_intrinsics */ 811 812 #endif /* __CMSIS_ARMCC_H */