firmware-nucleo/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c (253080B)
1 /** 2 ****************************************************************************** 3 * @file stm32f1xx_hal_i2c.c 4 * @author MCD Application Team 5 * @brief I2C HAL module driver. 6 * This file provides firmware functions to manage the following 7 * functionalities of the Inter Integrated Circuit (I2C) peripheral: 8 * + Initialization and de-initialization functions 9 * + IO operation functions 10 * + Peripheral State, Mode and Error functions 11 * 12 ****************************************************************************** 13 * @attention 14 * 15 * Copyright (c) 2016 STMicroelectronics. 16 * All rights reserved. 17 * 18 * This software is licensed under terms that can be found in the LICENSE file 19 * in the root directory of this software component. 20 * If no LICENSE file comes with this software, it is provided AS-IS. 21 * 22 ****************************************************************************** 23 @verbatim 24 ============================================================================== 25 ##### How to use this driver ##### 26 ============================================================================== 27 [..] 28 The I2C HAL driver can be used as follows: 29 30 (#) Declare a I2C_HandleTypeDef handle structure, for example: 31 I2C_HandleTypeDef hi2c; 32 33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: 34 (##) Enable the I2Cx interface clock 35 (##) I2C pins configuration 36 (+++) Enable the clock for the I2C GPIOs 37 (+++) Configure I2C pins as alternate function open-drain 38 (##) NVIC configuration if you need to use interrupt process 39 (+++) Configure the I2Cx interrupt priority 40 (+++) Enable the NVIC I2C IRQ Channel 41 (##) DMA Configuration if you need to use DMA process 42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel 43 (+++) Enable the DMAx interface clock using 44 (+++) Configure the DMA handle parameters 45 (+++) Configure the DMA Tx or Rx channel 46 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle 47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on 48 the DMA Tx or Rx channel 49 50 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, 51 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. 52 53 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware 54 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API. 55 56 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() 57 58 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : 59 60 *** Polling mode IO operation *** 61 ================================= 62 [..] 63 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() 64 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() 65 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() 66 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() 67 68 *** Polling mode IO MEM operation *** 69 ===================================== 70 [..] 71 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() 72 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() 73 74 75 *** Interrupt mode IO operation *** 76 =================================== 77 [..] 78 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() 79 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can 80 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() 81 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() 82 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can 83 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() 84 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() 85 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can 86 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() 87 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() 88 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can 89 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() 90 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 91 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 92 (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() 93 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can 94 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() 95 96 *** Interrupt mode or DMA mode IO sequential operation *** 97 ========================================================== 98 [..] 99 (@) These interfaces allow to manage a sequential transfer with a repeated start condition 100 when a direction change during transfer 101 [..] 102 (+) A specific option field manage the different steps of a sequential transfer 103 (+) Option field values are defined through I2C_XferOptions_definition and are listed below: 104 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode 105 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address 106 and data to transfer without a final stop condition 107 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address 108 and data to transfer without a final stop condition, an then permit a call the same master sequential interface 109 several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() 110 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) 111 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address 112 and with new data to transfer if the direction change or manage only the new data to transfer 113 if no direction change and without a final stop condition in both cases 114 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address 115 and with new data to transfer if the direction change or manage only the new data to transfer 116 if no direction change and with a final stop condition in both cases 117 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential 118 interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). 119 Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) 120 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) 121 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) 122 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). 123 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit 124 without stopping the communication and so generate a restart condition. 125 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential 126 interface. 127 Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) 128 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) 129 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) 130 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). 131 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. 132 133 (+) Different sequential I2C interfaces are listed below: 134 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT() 135 or using HAL_I2C_Master_Seq_Transmit_DMA() 136 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can 137 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() 138 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT() 139 or using HAL_I2C_Master_Seq_Receive_DMA() 140 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can 141 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() 142 (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() 143 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can 144 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() 145 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() 146 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can 147 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). 148 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can 149 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() 150 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT() 151 or using HAL_I2C_Slave_Seq_Transmit_DMA() 152 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can 153 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() 154 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT() 155 or using HAL_I2C_Slave_Seq_Receive_DMA() 156 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can 157 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() 158 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 159 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 160 161 *** Interrupt mode IO MEM operation *** 162 ======================================= 163 [..] 164 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using 165 HAL_I2C_Mem_Write_IT() 166 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can 167 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() 168 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using 169 HAL_I2C_Mem_Read_IT() 170 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can 171 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() 172 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 173 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 174 175 *** DMA mode IO operation *** 176 ============================== 177 [..] 178 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using 179 HAL_I2C_Master_Transmit_DMA() 180 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can 181 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() 182 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using 183 HAL_I2C_Master_Receive_DMA() 184 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can 185 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() 186 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using 187 HAL_I2C_Slave_Transmit_DMA() 188 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can 189 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() 190 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using 191 HAL_I2C_Slave_Receive_DMA() 192 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can 193 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() 194 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 195 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 196 (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() 197 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can 198 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() 199 200 *** DMA mode IO MEM operation *** 201 ================================= 202 [..] 203 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using 204 HAL_I2C_Mem_Write_DMA() 205 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can 206 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() 207 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using 208 HAL_I2C_Mem_Read_DMA() 209 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can 210 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() 211 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 212 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 213 214 215 *** I2C HAL driver macros list *** 216 ================================== 217 [..] 218 Below the list of most used macros in I2C HAL driver. 219 220 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral 221 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral 222 (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not 223 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag 224 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt 225 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt 226 227 *** Callback registration *** 228 ============================================= 229 [..] 230 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 231 allows the user to configure dynamically the driver callbacks. 232 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() 233 to register an interrupt callback. 234 [..] 235 Function HAL_I2C_RegisterCallback() allows to register following callbacks: 236 (+) MasterTxCpltCallback : callback for Master transmission end of transfer. 237 (+) MasterRxCpltCallback : callback for Master reception end of transfer. 238 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. 239 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. 240 (+) ListenCpltCallback : callback for end of listen mode. 241 (+) MemTxCpltCallback : callback for Memory transmission end of transfer. 242 (+) MemRxCpltCallback : callback for Memory reception end of transfer. 243 (+) ErrorCallback : callback for error detection. 244 (+) AbortCpltCallback : callback for abort completion process. 245 (+) MspInitCallback : callback for Msp Init. 246 (+) MspDeInitCallback : callback for Msp DeInit. 247 This function takes as parameters the HAL peripheral handle, the Callback ID 248 and a pointer to the user callback function. 249 [..] 250 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). 251 [..] 252 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default 253 weak function. 254 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, 255 and the Callback ID. 256 This function allows to reset following callbacks: 257 (+) MasterTxCpltCallback : callback for Master transmission end of transfer. 258 (+) MasterRxCpltCallback : callback for Master reception end of transfer. 259 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. 260 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. 261 (+) ListenCpltCallback : callback for end of listen mode. 262 (+) MemTxCpltCallback : callback for Memory transmission end of transfer. 263 (+) MemRxCpltCallback : callback for Memory reception end of transfer. 264 (+) ErrorCallback : callback for error detection. 265 (+) AbortCpltCallback : callback for abort completion process. 266 (+) MspInitCallback : callback for Msp Init. 267 (+) MspDeInitCallback : callback for Msp DeInit. 268 [..] 269 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). 270 [..] 271 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET 272 all callbacks are set to the corresponding weak functions: 273 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). 274 Exception done for MspInit and MspDeInit functions that are 275 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when 276 these callbacks are null (not registered beforehand). 277 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() 278 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. 279 [..] 280 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. 281 Exception done MspInit/MspDeInit functions that can be registered/unregistered 282 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, 283 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. 284 Then, the user first registers the MspInit/MspDeInit user callbacks 285 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() 286 or HAL_I2C_Init() function. 287 [..] 288 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or 289 not defined, the callback registration feature is not available and all callbacks 290 are set to the corresponding weak functions. 291 292 293 *** I2C Workarounds linked to Silicon Limitation *** 294 ==================================================== 295 [..] 296 Below the list of all silicon limitations implemented for HAL on STM32F1xx product. 297 (@) See ErrataSheet to know full silicon limitation list of your product. 298 299 (+) Workarounds Implemented inside I2C HAL Driver 300 (++) Wrong data read into data register (Polling and Interrupt mode) 301 (++) Start cannot be generated after a misplaced Stop 302 (++) Some software events must be managed before the current byte is being transferred: 303 Workaround: Use DMA in general, except when the Master is receiving a single byte. 304 For Interrupt mode, I2C should have the highest priority in the application. 305 (++) Mismatch on the "Setup time for a repeated Start condition" timing parameter: 306 Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if 307 supported by the slave. 308 (++) Data valid time (tVD;DAT) violated without the OVR flag being set: 309 Workaround: If the slave device allows it, use the clock stretching mechanism 310 by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init. 311 312 [..] 313 (@) You can refer to the I2C HAL driver header file for more useful macros 314 315 @endverbatim 316 */ 317 318 /* Includes ------------------------------------------------------------------*/ 319 #include "stm32f1xx_hal.h" 320 321 /** @addtogroup STM32F1xx_HAL_Driver 322 * @{ 323 */ 324 325 /** @defgroup I2C I2C 326 * @brief I2C HAL module driver 327 * @{ 328 */ 329 330 #ifdef HAL_I2C_MODULE_ENABLED 331 332 /* Private typedef -----------------------------------------------------------*/ 333 /* Private define ------------------------------------------------------------*/ 334 /** @defgroup I2C_Private_Define I2C Private Define 335 * @{ 336 */ 337 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ 338 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ 339 #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ 340 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ 341 342 /* Private define for @ref PreviousState usage */ 343 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ 344 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ 345 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ 346 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ 347 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ 348 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ 349 350 /** 351 * @} 352 */ 353 354 /* Private macro -------------------------------------------------------------*/ 355 /** @addtogroup I2C_Private_Macros 356 * @{ 357 */ 358 /* Macro to get remaining data to transfer on DMA side */ 359 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) 360 /** 361 * @} 362 */ 363 /* Private variables ---------------------------------------------------------*/ 364 /* Private function prototypes -----------------------------------------------*/ 365 366 /** @defgroup I2C_Private_Functions I2C Private Functions 367 * @{ 368 */ 369 /* Private functions to handle DMA transfer */ 370 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); 371 static void I2C_DMAError(DMA_HandleTypeDef *hdma); 372 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); 373 374 static void I2C_ITError(I2C_HandleTypeDef *hi2c); 375 376 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); 377 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); 378 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); 379 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); 380 381 /* Private functions to handle flags during polling transfer */ 382 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); 383 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); 384 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); 385 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); 386 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); 387 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); 388 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); 389 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); 390 391 /* Private functions for I2C transfer IRQ handler */ 392 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); 393 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); 394 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); 395 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); 396 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); 397 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); 398 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); 399 400 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); 401 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); 402 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); 403 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); 404 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); 405 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); 406 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); 407 408 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); 409 410 /* Private function to Convert Specific options */ 411 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); 412 413 /* Private function to flush DR register */ 414 static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c); 415 /** 416 * @} 417 */ 418 419 /* Exported functions --------------------------------------------------------*/ 420 421 /** @defgroup I2C_Exported_Functions I2C Exported Functions 422 * @{ 423 */ 424 425 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions 426 * @brief Initialization and Configuration functions 427 * 428 @verbatim 429 =============================================================================== 430 ##### Initialization and de-initialization functions ##### 431 =============================================================================== 432 [..] This subsection provides a set of functions allowing to initialize and 433 deinitialize the I2Cx peripheral: 434 435 (+) User must Implement HAL_I2C_MspInit() function in which he configures 436 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). 437 438 (+) Call the function HAL_I2C_Init() to configure the selected device with 439 the selected configuration: 440 (++) Communication Speed 441 (++) Duty cycle 442 (++) Addressing mode 443 (++) Own Address 1 444 (++) Dual Addressing mode 445 (++) Own Address 2 446 (++) General call mode 447 (++) Nostretch mode 448 449 (+) Call the function HAL_I2C_DeInit() to restore the default configuration 450 of the selected I2Cx peripheral. 451 452 @endverbatim 453 * @{ 454 */ 455 456 /** 457 * @brief Initializes the I2C according to the specified parameters 458 * in the I2C_InitTypeDef and initialize the associated handle. 459 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 460 * the configuration information for the specified I2C. 461 * @retval HAL status 462 */ 463 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) 464 { 465 uint32_t freqrange; 466 uint32_t pclk1; 467 468 /* Check the I2C handle allocation */ 469 if (hi2c == NULL) 470 { 471 return HAL_ERROR; 472 } 473 474 /* Check the parameters */ 475 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 476 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); 477 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); 478 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); 479 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); 480 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); 481 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); 482 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); 483 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); 484 485 if (hi2c->State == HAL_I2C_STATE_RESET) 486 { 487 /* Allocate lock resource and initialize it */ 488 hi2c->Lock = HAL_UNLOCKED; 489 490 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 491 /* Init the I2C Callback settings */ 492 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ 493 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ 494 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ 495 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ 496 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ 497 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ 498 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ 499 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ 500 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ 501 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ 502 503 if (hi2c->MspInitCallback == NULL) 504 { 505 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ 506 } 507 508 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 509 hi2c->MspInitCallback(hi2c); 510 #else 511 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 512 HAL_I2C_MspInit(hi2c); 513 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 514 } 515 516 hi2c->State = HAL_I2C_STATE_BUSY; 517 518 /* Disable the selected I2C peripheral */ 519 __HAL_I2C_DISABLE(hi2c); 520 521 /*Reset I2C*/ 522 hi2c->Instance->CR1 |= I2C_CR1_SWRST; 523 hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 524 525 /* Get PCLK1 frequency */ 526 pclk1 = HAL_RCC_GetPCLK1Freq(); 527 528 /* Check the minimum allowed PCLK1 frequency */ 529 if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 530 { 531 return HAL_ERROR; 532 } 533 534 /* Calculate frequency range */ 535 freqrange = I2C_FREQRANGE(pclk1); 536 537 /*---------------------------- I2Cx CR2 Configuration ----------------------*/ 538 /* Configure I2Cx: Frequency range */ 539 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 540 541 /*---------------------------- I2Cx TRISE Configuration --------------------*/ 542 /* Configure I2Cx: Rise Time */ 543 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 544 545 /*---------------------------- I2Cx CCR Configuration ----------------------*/ 546 /* Configure I2Cx: Speed */ 547 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 548 549 /*---------------------------- I2Cx CR1 Configuration ----------------------*/ 550 /* Configure I2Cx: Generalcall and NoStretch mode */ 551 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 552 553 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ 554 /* Configure I2Cx: Own Address1 and addressing mode */ 555 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 556 557 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ 558 /* Configure I2Cx: Dual mode and Own Address2 */ 559 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 560 561 /* Enable the selected I2C peripheral */ 562 __HAL_I2C_ENABLE(hi2c); 563 564 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 565 hi2c->State = HAL_I2C_STATE_READY; 566 hi2c->PreviousState = I2C_STATE_NONE; 567 hi2c->Mode = HAL_I2C_MODE_NONE; 568 569 return HAL_OK; 570 } 571 572 /** 573 * @brief DeInitialize the I2C peripheral. 574 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 575 * the configuration information for the specified I2C. 576 * @retval HAL status 577 */ 578 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) 579 { 580 /* Check the I2C handle allocation */ 581 if (hi2c == NULL) 582 { 583 return HAL_ERROR; 584 } 585 586 /* Check the parameters */ 587 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 588 589 hi2c->State = HAL_I2C_STATE_BUSY; 590 591 /* Disable the I2C Peripheral Clock */ 592 __HAL_I2C_DISABLE(hi2c); 593 594 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 595 if (hi2c->MspDeInitCallback == NULL) 596 { 597 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ 598 } 599 600 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 601 hi2c->MspDeInitCallback(hi2c); 602 #else 603 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 604 HAL_I2C_MspDeInit(hi2c); 605 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 606 607 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 608 hi2c->State = HAL_I2C_STATE_RESET; 609 hi2c->PreviousState = I2C_STATE_NONE; 610 hi2c->Mode = HAL_I2C_MODE_NONE; 611 612 /* Release Lock */ 613 __HAL_UNLOCK(hi2c); 614 615 return HAL_OK; 616 } 617 618 /** 619 * @brief Initialize the I2C MSP. 620 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 621 * the configuration information for the specified I2C. 622 * @retval None 623 */ 624 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) 625 { 626 /* Prevent unused argument(s) compilation warning */ 627 UNUSED(hi2c); 628 629 /* NOTE : This function should not be modified, when the callback is needed, 630 the HAL_I2C_MspInit could be implemented in the user file 631 */ 632 } 633 634 /** 635 * @brief DeInitialize the I2C MSP. 636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 637 * the configuration information for the specified I2C. 638 * @retval None 639 */ 640 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) 641 { 642 /* Prevent unused argument(s) compilation warning */ 643 UNUSED(hi2c); 644 645 /* NOTE : This function should not be modified, when the callback is needed, 646 the HAL_I2C_MspDeInit could be implemented in the user file 647 */ 648 } 649 650 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 651 /** 652 * @brief Register a User I2C Callback 653 * To be used instead of the weak predefined callback 654 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 655 * the configuration information for the specified I2C. 656 * @param CallbackID ID of the callback to be registered 657 * This parameter can be one of the following values: 658 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID 659 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID 660 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID 661 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID 662 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID 663 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID 664 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID 665 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID 666 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID 667 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID 668 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID 669 * @param pCallback pointer to the Callback function 670 * @retval HAL status 671 */ 672 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) 673 { 674 HAL_StatusTypeDef status = HAL_OK; 675 676 if (pCallback == NULL) 677 { 678 /* Update the error code */ 679 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 680 681 return HAL_ERROR; 682 } 683 /* Process locked */ 684 __HAL_LOCK(hi2c); 685 686 if (HAL_I2C_STATE_READY == hi2c->State) 687 { 688 switch (CallbackID) 689 { 690 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : 691 hi2c->MasterTxCpltCallback = pCallback; 692 break; 693 694 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : 695 hi2c->MasterRxCpltCallback = pCallback; 696 break; 697 698 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : 699 hi2c->SlaveTxCpltCallback = pCallback; 700 break; 701 702 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : 703 hi2c->SlaveRxCpltCallback = pCallback; 704 break; 705 706 case HAL_I2C_LISTEN_COMPLETE_CB_ID : 707 hi2c->ListenCpltCallback = pCallback; 708 break; 709 710 case HAL_I2C_MEM_TX_COMPLETE_CB_ID : 711 hi2c->MemTxCpltCallback = pCallback; 712 break; 713 714 case HAL_I2C_MEM_RX_COMPLETE_CB_ID : 715 hi2c->MemRxCpltCallback = pCallback; 716 break; 717 718 case HAL_I2C_ERROR_CB_ID : 719 hi2c->ErrorCallback = pCallback; 720 break; 721 722 case HAL_I2C_ABORT_CB_ID : 723 hi2c->AbortCpltCallback = pCallback; 724 break; 725 726 case HAL_I2C_MSPINIT_CB_ID : 727 hi2c->MspInitCallback = pCallback; 728 break; 729 730 case HAL_I2C_MSPDEINIT_CB_ID : 731 hi2c->MspDeInitCallback = pCallback; 732 break; 733 734 default : 735 /* Update the error code */ 736 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 737 738 /* Return error status */ 739 status = HAL_ERROR; 740 break; 741 } 742 } 743 else if (HAL_I2C_STATE_RESET == hi2c->State) 744 { 745 switch (CallbackID) 746 { 747 case HAL_I2C_MSPINIT_CB_ID : 748 hi2c->MspInitCallback = pCallback; 749 break; 750 751 case HAL_I2C_MSPDEINIT_CB_ID : 752 hi2c->MspDeInitCallback = pCallback; 753 break; 754 755 default : 756 /* Update the error code */ 757 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 758 759 /* Return error status */ 760 status = HAL_ERROR; 761 break; 762 } 763 } 764 else 765 { 766 /* Update the error code */ 767 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 768 769 /* Return error status */ 770 status = HAL_ERROR; 771 } 772 773 /* Release Lock */ 774 __HAL_UNLOCK(hi2c); 775 return status; 776 } 777 778 /** 779 * @brief Unregister an I2C Callback 780 * I2C callback is redirected to the weak predefined callback 781 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 782 * the configuration information for the specified I2C. 783 * @param CallbackID ID of the callback to be unregistered 784 * This parameter can be one of the following values: 785 * This parameter can be one of the following values: 786 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID 787 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID 788 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID 789 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID 790 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID 791 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID 792 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID 793 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID 794 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID 795 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID 796 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID 797 * @retval HAL status 798 */ 799 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) 800 { 801 HAL_StatusTypeDef status = HAL_OK; 802 803 /* Process locked */ 804 __HAL_LOCK(hi2c); 805 806 if (HAL_I2C_STATE_READY == hi2c->State) 807 { 808 switch (CallbackID) 809 { 810 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : 811 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ 812 break; 813 814 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : 815 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ 816 break; 817 818 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : 819 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ 820 break; 821 822 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : 823 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ 824 break; 825 826 case HAL_I2C_LISTEN_COMPLETE_CB_ID : 827 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ 828 break; 829 830 case HAL_I2C_MEM_TX_COMPLETE_CB_ID : 831 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ 832 break; 833 834 case HAL_I2C_MEM_RX_COMPLETE_CB_ID : 835 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ 836 break; 837 838 case HAL_I2C_ERROR_CB_ID : 839 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ 840 break; 841 842 case HAL_I2C_ABORT_CB_ID : 843 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ 844 break; 845 846 case HAL_I2C_MSPINIT_CB_ID : 847 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ 848 break; 849 850 case HAL_I2C_MSPDEINIT_CB_ID : 851 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ 852 break; 853 854 default : 855 /* Update the error code */ 856 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 857 858 /* Return error status */ 859 status = HAL_ERROR; 860 break; 861 } 862 } 863 else if (HAL_I2C_STATE_RESET == hi2c->State) 864 { 865 switch (CallbackID) 866 { 867 case HAL_I2C_MSPINIT_CB_ID : 868 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ 869 break; 870 871 case HAL_I2C_MSPDEINIT_CB_ID : 872 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ 873 break; 874 875 default : 876 /* Update the error code */ 877 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 878 879 /* Return error status */ 880 status = HAL_ERROR; 881 break; 882 } 883 } 884 else 885 { 886 /* Update the error code */ 887 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 888 889 /* Return error status */ 890 status = HAL_ERROR; 891 } 892 893 /* Release Lock */ 894 __HAL_UNLOCK(hi2c); 895 return status; 896 } 897 898 /** 899 * @brief Register the Slave Address Match I2C Callback 900 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback 901 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 902 * the configuration information for the specified I2C. 903 * @param pCallback pointer to the Address Match Callback function 904 * @retval HAL status 905 */ 906 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) 907 { 908 HAL_StatusTypeDef status = HAL_OK; 909 910 if (pCallback == NULL) 911 { 912 /* Update the error code */ 913 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 914 915 return HAL_ERROR; 916 } 917 /* Process locked */ 918 __HAL_LOCK(hi2c); 919 920 if (HAL_I2C_STATE_READY == hi2c->State) 921 { 922 hi2c->AddrCallback = pCallback; 923 } 924 else 925 { 926 /* Update the error code */ 927 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 928 929 /* Return error status */ 930 status = HAL_ERROR; 931 } 932 933 /* Release Lock */ 934 __HAL_UNLOCK(hi2c); 935 return status; 936 } 937 938 /** 939 * @brief UnRegister the Slave Address Match I2C Callback 940 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback 941 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 942 * the configuration information for the specified I2C. 943 * @retval HAL status 944 */ 945 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) 946 { 947 HAL_StatusTypeDef status = HAL_OK; 948 949 /* Process locked */ 950 __HAL_LOCK(hi2c); 951 952 if (HAL_I2C_STATE_READY == hi2c->State) 953 { 954 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ 955 } 956 else 957 { 958 /* Update the error code */ 959 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 960 961 /* Return error status */ 962 status = HAL_ERROR; 963 } 964 965 /* Release Lock */ 966 __HAL_UNLOCK(hi2c); 967 return status; 968 } 969 970 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 971 972 /** 973 * @brief I2C data register flush process. 974 * @param hi2c I2C handle. 975 * @retval None 976 */ 977 static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c) 978 { 979 /* Write a dummy data in DR to clear TXE flag */ 980 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET) 981 { 982 hi2c->Instance->DR = 0x00U; 983 } 984 } 985 986 /** 987 * @} 988 */ 989 990 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions 991 * @brief Data transfers functions 992 * 993 @verbatim 994 =============================================================================== 995 ##### IO operation functions ##### 996 =============================================================================== 997 [..] 998 This subsection provides a set of functions allowing to manage the I2C data 999 transfers. 1000 1001 (#) There are two modes of transfer: 1002 (++) Blocking mode : The communication is performed in the polling mode. 1003 The status of all data processing is returned by the same function 1004 after finishing transfer. 1005 (++) No-Blocking mode : The communication is performed using Interrupts 1006 or DMA. These functions return the status of the transfer startup. 1007 The end of the data processing will be indicated through the 1008 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when 1009 using DMA mode. 1010 1011 (#) Blocking mode functions are : 1012 (++) HAL_I2C_Master_Transmit() 1013 (++) HAL_I2C_Master_Receive() 1014 (++) HAL_I2C_Slave_Transmit() 1015 (++) HAL_I2C_Slave_Receive() 1016 (++) HAL_I2C_Mem_Write() 1017 (++) HAL_I2C_Mem_Read() 1018 (++) HAL_I2C_IsDeviceReady() 1019 1020 (#) No-Blocking mode functions with Interrupt are : 1021 (++) HAL_I2C_Master_Transmit_IT() 1022 (++) HAL_I2C_Master_Receive_IT() 1023 (++) HAL_I2C_Slave_Transmit_IT() 1024 (++) HAL_I2C_Slave_Receive_IT() 1025 (++) HAL_I2C_Mem_Write_IT() 1026 (++) HAL_I2C_Mem_Read_IT() 1027 (++) HAL_I2C_Master_Seq_Transmit_IT() 1028 (++) HAL_I2C_Master_Seq_Receive_IT() 1029 (++) HAL_I2C_Slave_Seq_Transmit_IT() 1030 (++) HAL_I2C_Slave_Seq_Receive_IT() 1031 (++) HAL_I2C_EnableListen_IT() 1032 (++) HAL_I2C_DisableListen_IT() 1033 (++) HAL_I2C_Master_Abort_IT() 1034 1035 (#) No-Blocking mode functions with DMA are : 1036 (++) HAL_I2C_Master_Transmit_DMA() 1037 (++) HAL_I2C_Master_Receive_DMA() 1038 (++) HAL_I2C_Slave_Transmit_DMA() 1039 (++) HAL_I2C_Slave_Receive_DMA() 1040 (++) HAL_I2C_Mem_Write_DMA() 1041 (++) HAL_I2C_Mem_Read_DMA() 1042 (++) HAL_I2C_Master_Seq_Transmit_DMA() 1043 (++) HAL_I2C_Master_Seq_Receive_DMA() 1044 (++) HAL_I2C_Slave_Seq_Transmit_DMA() 1045 (++) HAL_I2C_Slave_Seq_Receive_DMA() 1046 1047 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: 1048 (++) HAL_I2C_MasterTxCpltCallback() 1049 (++) HAL_I2C_MasterRxCpltCallback() 1050 (++) HAL_I2C_SlaveTxCpltCallback() 1051 (++) HAL_I2C_SlaveRxCpltCallback() 1052 (++) HAL_I2C_MemTxCpltCallback() 1053 (++) HAL_I2C_MemRxCpltCallback() 1054 (++) HAL_I2C_AddrCallback() 1055 (++) HAL_I2C_ListenCpltCallback() 1056 (++) HAL_I2C_ErrorCallback() 1057 (++) HAL_I2C_AbortCpltCallback() 1058 1059 @endverbatim 1060 * @{ 1061 */ 1062 1063 /** 1064 * @brief Transmits in master mode an amount of data in blocking mode. 1065 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 1066 * the configuration information for the specified I2C. 1067 * @param DevAddress Target device address: The device 7 bits address value 1068 * in datasheet must be shifted to the left before calling the interface 1069 * @param pData Pointer to data buffer 1070 * @param Size Amount of data to be sent 1071 * @param Timeout Timeout duration 1072 * @retval HAL status 1073 */ 1074 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) 1075 { 1076 /* Init tickstart for timeout management*/ 1077 uint32_t tickstart = HAL_GetTick(); 1078 1079 if (hi2c->State == HAL_I2C_STATE_READY) 1080 { 1081 /* Wait until BUSY flag is reset */ 1082 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 1083 { 1084 return HAL_BUSY; 1085 } 1086 1087 /* Process Locked */ 1088 __HAL_LOCK(hi2c); 1089 1090 /* Check if the I2C is already enabled */ 1091 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 1092 { 1093 /* Enable I2C peripheral */ 1094 __HAL_I2C_ENABLE(hi2c); 1095 } 1096 1097 /* Disable Pos */ 1098 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1099 1100 hi2c->State = HAL_I2C_STATE_BUSY_TX; 1101 hi2c->Mode = HAL_I2C_MODE_MASTER; 1102 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 1103 1104 /* Prepare transfer parameters */ 1105 hi2c->pBuffPtr = pData; 1106 hi2c->XferCount = Size; 1107 hi2c->XferSize = hi2c->XferCount; 1108 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 1109 1110 /* Send Slave Address */ 1111 if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) 1112 { 1113 return HAL_ERROR; 1114 } 1115 1116 /* Clear ADDR flag */ 1117 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 1118 1119 while (hi2c->XferSize > 0U) 1120 { 1121 /* Wait until TXE flag is set */ 1122 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 1123 { 1124 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 1125 { 1126 /* Generate Stop */ 1127 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 1128 } 1129 return HAL_ERROR; 1130 } 1131 1132 /* Write data to DR */ 1133 hi2c->Instance->DR = *hi2c->pBuffPtr; 1134 1135 /* Increment Buffer pointer */ 1136 hi2c->pBuffPtr++; 1137 1138 /* Update counter */ 1139 hi2c->XferCount--; 1140 hi2c->XferSize--; 1141 1142 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 1143 { 1144 /* Write data to DR */ 1145 hi2c->Instance->DR = *hi2c->pBuffPtr; 1146 1147 /* Increment Buffer pointer */ 1148 hi2c->pBuffPtr++; 1149 1150 /* Update counter */ 1151 hi2c->XferCount--; 1152 hi2c->XferSize--; 1153 } 1154 1155 /* Wait until BTF flag is set */ 1156 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 1157 { 1158 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 1159 { 1160 /* Generate Stop */ 1161 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 1162 } 1163 return HAL_ERROR; 1164 } 1165 } 1166 1167 /* Generate Stop */ 1168 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 1169 1170 hi2c->State = HAL_I2C_STATE_READY; 1171 hi2c->Mode = HAL_I2C_MODE_NONE; 1172 1173 /* Process Unlocked */ 1174 __HAL_UNLOCK(hi2c); 1175 1176 return HAL_OK; 1177 } 1178 else 1179 { 1180 return HAL_BUSY; 1181 } 1182 } 1183 1184 /** 1185 * @brief Receives in master mode an amount of data in blocking mode. 1186 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 1187 * the configuration information for the specified I2C. 1188 * @param DevAddress Target device address: The device 7 bits address value 1189 * in datasheet must be shifted to the left before calling the interface 1190 * @param pData Pointer to data buffer 1191 * @param Size Amount of data to be sent 1192 * @param Timeout Timeout duration 1193 * @retval HAL status 1194 */ 1195 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) 1196 { 1197 __IO uint32_t count = 0U; 1198 1199 /* Init tickstart for timeout management*/ 1200 uint32_t tickstart = HAL_GetTick(); 1201 1202 if (hi2c->State == HAL_I2C_STATE_READY) 1203 { 1204 /* Wait until BUSY flag is reset */ 1205 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 1206 { 1207 return HAL_BUSY; 1208 } 1209 1210 /* Process Locked */ 1211 __HAL_LOCK(hi2c); 1212 1213 /* Check if the I2C is already enabled */ 1214 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 1215 { 1216 /* Enable I2C peripheral */ 1217 __HAL_I2C_ENABLE(hi2c); 1218 } 1219 1220 /* Disable Pos */ 1221 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1222 1223 hi2c->State = HAL_I2C_STATE_BUSY_RX; 1224 hi2c->Mode = HAL_I2C_MODE_MASTER; 1225 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 1226 1227 /* Prepare transfer parameters */ 1228 hi2c->pBuffPtr = pData; 1229 hi2c->XferCount = Size; 1230 hi2c->XferSize = hi2c->XferCount; 1231 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 1232 1233 /* Send Slave Address */ 1234 if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) 1235 { 1236 return HAL_ERROR; 1237 } 1238 1239 if (hi2c->XferSize == 0U) 1240 { 1241 /* Clear ADDR flag */ 1242 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 1243 1244 /* Generate Stop */ 1245 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 1246 } 1247 else if (hi2c->XferSize == 1U) 1248 { 1249 /* Disable Acknowledge */ 1250 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1251 1252 /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 1253 software sequence must complete before the current byte end of transfer */ 1254 __disable_irq(); 1255 1256 /* Clear ADDR flag */ 1257 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 1258 1259 /* Generate Stop */ 1260 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 1261 1262 /* Re-enable IRQs */ 1263 __enable_irq(); 1264 } 1265 else if (hi2c->XferSize == 2U) 1266 { 1267 /* Enable Pos */ 1268 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1269 1270 /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 1271 software sequence must complete before the current byte end of transfer */ 1272 __disable_irq(); 1273 1274 /* Clear ADDR flag */ 1275 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 1276 1277 /* Disable Acknowledge */ 1278 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1279 1280 /* Re-enable IRQs */ 1281 __enable_irq(); 1282 } 1283 else 1284 { 1285 /* Enable Acknowledge */ 1286 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1287 1288 /* Clear ADDR flag */ 1289 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 1290 } 1291 1292 while (hi2c->XferSize > 0U) 1293 { 1294 if (hi2c->XferSize <= 3U) 1295 { 1296 /* One byte */ 1297 if (hi2c->XferSize == 1U) 1298 { 1299 /* Wait until RXNE flag is set */ 1300 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 1301 { 1302 return HAL_ERROR; 1303 } 1304 1305 /* Read data from DR */ 1306 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1307 1308 /* Increment Buffer pointer */ 1309 hi2c->pBuffPtr++; 1310 1311 /* Update counter */ 1312 hi2c->XferSize--; 1313 hi2c->XferCount--; 1314 } 1315 /* Two bytes */ 1316 else if (hi2c->XferSize == 2U) 1317 { 1318 /* Wait until BTF flag is set */ 1319 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 1320 { 1321 return HAL_ERROR; 1322 } 1323 1324 /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 1325 software sequence must complete before the current byte end of transfer */ 1326 __disable_irq(); 1327 1328 /* Generate Stop */ 1329 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 1330 1331 /* Read data from DR */ 1332 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1333 1334 /* Increment Buffer pointer */ 1335 hi2c->pBuffPtr++; 1336 1337 /* Update counter */ 1338 hi2c->XferSize--; 1339 hi2c->XferCount--; 1340 1341 /* Re-enable IRQs */ 1342 __enable_irq(); 1343 1344 /* Read data from DR */ 1345 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1346 1347 /* Increment Buffer pointer */ 1348 hi2c->pBuffPtr++; 1349 1350 /* Update counter */ 1351 hi2c->XferSize--; 1352 hi2c->XferCount--; 1353 } 1354 /* 3 Last bytes */ 1355 else 1356 { 1357 /* Wait until BTF flag is set */ 1358 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 1359 { 1360 return HAL_ERROR; 1361 } 1362 1363 /* Disable Acknowledge */ 1364 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1365 1366 /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 1367 software sequence must complete before the current byte end of transfer */ 1368 __disable_irq(); 1369 1370 /* Read data from DR */ 1371 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1372 1373 /* Increment Buffer pointer */ 1374 hi2c->pBuffPtr++; 1375 1376 /* Update counter */ 1377 hi2c->XferSize--; 1378 hi2c->XferCount--; 1379 1380 /* Wait until BTF flag is set */ 1381 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 1382 do 1383 { 1384 count--; 1385 if (count == 0U) 1386 { 1387 hi2c->PreviousState = I2C_STATE_NONE; 1388 hi2c->State = HAL_I2C_STATE_READY; 1389 hi2c->Mode = HAL_I2C_MODE_NONE; 1390 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 1391 1392 /* Re-enable IRQs */ 1393 __enable_irq(); 1394 1395 /* Process Unlocked */ 1396 __HAL_UNLOCK(hi2c); 1397 1398 return HAL_ERROR; 1399 } 1400 } 1401 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); 1402 1403 /* Generate Stop */ 1404 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 1405 1406 /* Read data from DR */ 1407 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1408 1409 /* Increment Buffer pointer */ 1410 hi2c->pBuffPtr++; 1411 1412 /* Update counter */ 1413 hi2c->XferSize--; 1414 hi2c->XferCount--; 1415 1416 /* Re-enable IRQs */ 1417 __enable_irq(); 1418 1419 /* Read data from DR */ 1420 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1421 1422 /* Increment Buffer pointer */ 1423 hi2c->pBuffPtr++; 1424 1425 /* Update counter */ 1426 hi2c->XferSize--; 1427 hi2c->XferCount--; 1428 } 1429 } 1430 else 1431 { 1432 /* Wait until RXNE flag is set */ 1433 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 1434 { 1435 return HAL_ERROR; 1436 } 1437 1438 /* Read data from DR */ 1439 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1440 1441 /* Increment Buffer pointer */ 1442 hi2c->pBuffPtr++; 1443 1444 /* Update counter */ 1445 hi2c->XferSize--; 1446 hi2c->XferCount--; 1447 1448 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 1449 { 1450 1451 if (hi2c->XferSize == 3U) 1452 { 1453 /* Disable Acknowledge */ 1454 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1455 } 1456 1457 /* Read data from DR */ 1458 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1459 1460 /* Increment Buffer pointer */ 1461 hi2c->pBuffPtr++; 1462 1463 /* Update counter */ 1464 hi2c->XferSize--; 1465 hi2c->XferCount--; 1466 } 1467 } 1468 } 1469 1470 hi2c->State = HAL_I2C_STATE_READY; 1471 hi2c->Mode = HAL_I2C_MODE_NONE; 1472 1473 /* Process Unlocked */ 1474 __HAL_UNLOCK(hi2c); 1475 1476 return HAL_OK; 1477 } 1478 else 1479 { 1480 return HAL_BUSY; 1481 } 1482 } 1483 1484 /** 1485 * @brief Transmits in slave mode an amount of data in blocking mode. 1486 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 1487 * the configuration information for the specified I2C. 1488 * @param pData Pointer to data buffer 1489 * @param Size Amount of data to be sent 1490 * @param Timeout Timeout duration 1491 * @retval HAL status 1492 */ 1493 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) 1494 { 1495 /* Init tickstart for timeout management*/ 1496 uint32_t tickstart = HAL_GetTick(); 1497 1498 if (hi2c->State == HAL_I2C_STATE_READY) 1499 { 1500 if ((pData == NULL) || (Size == 0U)) 1501 { 1502 return HAL_ERROR; 1503 } 1504 1505 /* Process Locked */ 1506 __HAL_LOCK(hi2c); 1507 1508 /* Check if the I2C is already enabled */ 1509 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 1510 { 1511 /* Enable I2C peripheral */ 1512 __HAL_I2C_ENABLE(hi2c); 1513 } 1514 1515 /* Disable Pos */ 1516 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1517 1518 hi2c->State = HAL_I2C_STATE_BUSY_TX; 1519 hi2c->Mode = HAL_I2C_MODE_SLAVE; 1520 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 1521 1522 /* Prepare transfer parameters */ 1523 hi2c->pBuffPtr = pData; 1524 hi2c->XferCount = Size; 1525 hi2c->XferSize = hi2c->XferCount; 1526 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 1527 1528 /* Enable Address Acknowledge */ 1529 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1530 1531 /* Wait until ADDR flag is set */ 1532 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) 1533 { 1534 return HAL_ERROR; 1535 } 1536 1537 /* Clear ADDR flag */ 1538 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 1539 1540 /* If 10bit addressing mode is selected */ 1541 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 1542 { 1543 /* Wait until ADDR flag is set */ 1544 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) 1545 { 1546 return HAL_ERROR; 1547 } 1548 1549 /* Clear ADDR flag */ 1550 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 1551 } 1552 1553 while (hi2c->XferSize > 0U) 1554 { 1555 /* Wait until TXE flag is set */ 1556 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 1557 { 1558 /* Disable Address Acknowledge */ 1559 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1560 1561 return HAL_ERROR; 1562 } 1563 1564 /* Write data to DR */ 1565 hi2c->Instance->DR = *hi2c->pBuffPtr; 1566 1567 /* Increment Buffer pointer */ 1568 hi2c->pBuffPtr++; 1569 1570 /* Update counter */ 1571 hi2c->XferCount--; 1572 hi2c->XferSize--; 1573 1574 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 1575 { 1576 /* Write data to DR */ 1577 hi2c->Instance->DR = *hi2c->pBuffPtr; 1578 1579 /* Increment Buffer pointer */ 1580 hi2c->pBuffPtr++; 1581 1582 /* Update counter */ 1583 hi2c->XferCount--; 1584 hi2c->XferSize--; 1585 } 1586 } 1587 1588 /* Wait until AF flag is set */ 1589 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) 1590 { 1591 return HAL_ERROR; 1592 } 1593 1594 /* Clear AF flag */ 1595 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 1596 1597 /* Disable Address Acknowledge */ 1598 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1599 1600 hi2c->State = HAL_I2C_STATE_READY; 1601 hi2c->Mode = HAL_I2C_MODE_NONE; 1602 1603 /* Process Unlocked */ 1604 __HAL_UNLOCK(hi2c); 1605 1606 return HAL_OK; 1607 } 1608 else 1609 { 1610 return HAL_BUSY; 1611 } 1612 } 1613 1614 /** 1615 * @brief Receive in slave mode an amount of data in blocking mode 1616 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 1617 * the configuration information for the specified I2C. 1618 * @param pData Pointer to data buffer 1619 * @param Size Amount of data to be sent 1620 * @param Timeout Timeout duration 1621 * @retval HAL status 1622 */ 1623 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) 1624 { 1625 /* Init tickstart for timeout management*/ 1626 uint32_t tickstart = HAL_GetTick(); 1627 1628 if (hi2c->State == HAL_I2C_STATE_READY) 1629 { 1630 if ((pData == NULL) || (Size == (uint16_t)0)) 1631 { 1632 return HAL_ERROR; 1633 } 1634 1635 /* Process Locked */ 1636 __HAL_LOCK(hi2c); 1637 1638 /* Check if the I2C is already enabled */ 1639 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 1640 { 1641 /* Enable I2C peripheral */ 1642 __HAL_I2C_ENABLE(hi2c); 1643 } 1644 1645 /* Disable Pos */ 1646 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1647 1648 hi2c->State = HAL_I2C_STATE_BUSY_RX; 1649 hi2c->Mode = HAL_I2C_MODE_SLAVE; 1650 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 1651 1652 /* Prepare transfer parameters */ 1653 hi2c->pBuffPtr = pData; 1654 hi2c->XferCount = Size; 1655 hi2c->XferSize = hi2c->XferCount; 1656 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 1657 1658 /* Enable Address Acknowledge */ 1659 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1660 1661 /* Wait until ADDR flag is set */ 1662 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) 1663 { 1664 return HAL_ERROR; 1665 } 1666 1667 /* Clear ADDR flag */ 1668 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 1669 1670 while (hi2c->XferSize > 0U) 1671 { 1672 /* Wait until RXNE flag is set */ 1673 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 1674 { 1675 /* Disable Address Acknowledge */ 1676 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1677 1678 return HAL_ERROR; 1679 } 1680 1681 /* Read data from DR */ 1682 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1683 1684 /* Increment Buffer pointer */ 1685 hi2c->pBuffPtr++; 1686 1687 /* Update counter */ 1688 hi2c->XferSize--; 1689 hi2c->XferCount--; 1690 1691 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 1692 { 1693 /* Read data from DR */ 1694 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 1695 1696 /* Increment Buffer pointer */ 1697 hi2c->pBuffPtr++; 1698 1699 /* Update counter */ 1700 hi2c->XferSize--; 1701 hi2c->XferCount--; 1702 } 1703 } 1704 1705 /* Wait until STOP flag is set */ 1706 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 1707 { 1708 /* Disable Address Acknowledge */ 1709 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1710 1711 return HAL_ERROR; 1712 } 1713 1714 /* Clear STOP flag */ 1715 __HAL_I2C_CLEAR_STOPFLAG(hi2c); 1716 1717 /* Disable Address Acknowledge */ 1718 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1719 1720 hi2c->State = HAL_I2C_STATE_READY; 1721 hi2c->Mode = HAL_I2C_MODE_NONE; 1722 1723 /* Process Unlocked */ 1724 __HAL_UNLOCK(hi2c); 1725 1726 return HAL_OK; 1727 } 1728 else 1729 { 1730 return HAL_BUSY; 1731 } 1732 } 1733 1734 /** 1735 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt 1736 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 1737 * the configuration information for the specified I2C. 1738 * @param DevAddress Target device address: The device 7 bits address value 1739 * in datasheet must be shifted to the left before calling the interface 1740 * @param pData Pointer to data buffer 1741 * @param Size Amount of data to be sent 1742 * @retval HAL status 1743 */ 1744 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) 1745 { 1746 __IO uint32_t count = 0U; 1747 1748 if (hi2c->State == HAL_I2C_STATE_READY) 1749 { 1750 /* Wait until BUSY flag is reset */ 1751 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 1752 do 1753 { 1754 count--; 1755 if (count == 0U) 1756 { 1757 hi2c->PreviousState = I2C_STATE_NONE; 1758 hi2c->State = HAL_I2C_STATE_READY; 1759 hi2c->Mode = HAL_I2C_MODE_NONE; 1760 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 1761 1762 return HAL_BUSY; 1763 } 1764 } 1765 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 1766 1767 /* Process Locked */ 1768 __HAL_LOCK(hi2c); 1769 1770 /* Check if the I2C is already enabled */ 1771 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 1772 { 1773 /* Enable I2C peripheral */ 1774 __HAL_I2C_ENABLE(hi2c); 1775 } 1776 1777 /* Disable Pos */ 1778 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1779 1780 hi2c->State = HAL_I2C_STATE_BUSY_TX; 1781 hi2c->Mode = HAL_I2C_MODE_MASTER; 1782 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 1783 1784 /* Prepare transfer parameters */ 1785 hi2c->pBuffPtr = pData; 1786 hi2c->XferCount = Size; 1787 hi2c->XferSize = hi2c->XferCount; 1788 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 1789 hi2c->Devaddress = DevAddress; 1790 1791 /* Process Unlocked */ 1792 __HAL_UNLOCK(hi2c); 1793 1794 /* Note : The I2C interrupts must be enabled after unlocking current process 1795 to avoid the risk of I2C interrupt handle execution before current 1796 process unlock */ 1797 /* Enable EVT, BUF and ERR interrupt */ 1798 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 1799 1800 /* Generate Start */ 1801 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 1802 1803 return HAL_OK; 1804 } 1805 else 1806 { 1807 return HAL_BUSY; 1808 } 1809 } 1810 1811 /** 1812 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt 1813 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 1814 * the configuration information for the specified I2C. 1815 * @param DevAddress Target device address: The device 7 bits address value 1816 * in datasheet must be shifted to the left before calling the interface 1817 * @param pData Pointer to data buffer 1818 * @param Size Amount of data to be sent 1819 * @retval HAL status 1820 */ 1821 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) 1822 { 1823 __IO uint32_t count = 0U; 1824 1825 if (hi2c->State == HAL_I2C_STATE_READY) 1826 { 1827 /* Wait until BUSY flag is reset */ 1828 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 1829 do 1830 { 1831 count--; 1832 if (count == 0U) 1833 { 1834 hi2c->PreviousState = I2C_STATE_NONE; 1835 hi2c->State = HAL_I2C_STATE_READY; 1836 hi2c->Mode = HAL_I2C_MODE_NONE; 1837 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 1838 1839 return HAL_BUSY; 1840 } 1841 } 1842 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 1843 1844 /* Process Locked */ 1845 __HAL_LOCK(hi2c); 1846 1847 /* Check if the I2C is already enabled */ 1848 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 1849 { 1850 /* Enable I2C peripheral */ 1851 __HAL_I2C_ENABLE(hi2c); 1852 } 1853 1854 /* Disable Pos */ 1855 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1856 1857 hi2c->State = HAL_I2C_STATE_BUSY_RX; 1858 hi2c->Mode = HAL_I2C_MODE_MASTER; 1859 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 1860 1861 /* Prepare transfer parameters */ 1862 hi2c->pBuffPtr = pData; 1863 hi2c->XferCount = Size; 1864 hi2c->XferSize = hi2c->XferCount; 1865 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 1866 hi2c->Devaddress = DevAddress; 1867 1868 1869 /* Process Unlocked */ 1870 __HAL_UNLOCK(hi2c); 1871 1872 /* Note : The I2C interrupts must be enabled after unlocking current process 1873 to avoid the risk of I2C interrupt handle execution before current 1874 process unlock */ 1875 1876 /* Enable EVT, BUF and ERR interrupt */ 1877 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 1878 1879 /* Enable Acknowledge */ 1880 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1881 1882 /* Generate Start */ 1883 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 1884 1885 return HAL_OK; 1886 } 1887 else 1888 { 1889 return HAL_BUSY; 1890 } 1891 } 1892 1893 /** 1894 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt 1895 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 1896 * the configuration information for the specified I2C. 1897 * @param pData Pointer to data buffer 1898 * @param Size Amount of data to be sent 1899 * @retval HAL status 1900 */ 1901 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) 1902 { 1903 1904 if (hi2c->State == HAL_I2C_STATE_READY) 1905 { 1906 if ((pData == NULL) || (Size == 0U)) 1907 { 1908 return HAL_ERROR; 1909 } 1910 1911 /* Process Locked */ 1912 __HAL_LOCK(hi2c); 1913 1914 /* Check if the I2C is already enabled */ 1915 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 1916 { 1917 /* Enable I2C peripheral */ 1918 __HAL_I2C_ENABLE(hi2c); 1919 } 1920 1921 /* Disable Pos */ 1922 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1923 1924 hi2c->State = HAL_I2C_STATE_BUSY_TX; 1925 hi2c->Mode = HAL_I2C_MODE_SLAVE; 1926 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 1927 1928 /* Prepare transfer parameters */ 1929 hi2c->pBuffPtr = pData; 1930 hi2c->XferCount = Size; 1931 hi2c->XferSize = hi2c->XferCount; 1932 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 1933 1934 /* Enable Address Acknowledge */ 1935 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1936 1937 /* Process Unlocked */ 1938 __HAL_UNLOCK(hi2c); 1939 1940 /* Note : The I2C interrupts must be enabled after unlocking current process 1941 to avoid the risk of I2C interrupt handle execution before current 1942 process unlock */ 1943 1944 /* Enable EVT, BUF and ERR interrupt */ 1945 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 1946 1947 return HAL_OK; 1948 } 1949 else 1950 { 1951 return HAL_BUSY; 1952 } 1953 } 1954 1955 /** 1956 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt 1957 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 1958 * the configuration information for the specified I2C. 1959 * @param pData Pointer to data buffer 1960 * @param Size Amount of data to be sent 1961 * @retval HAL status 1962 */ 1963 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) 1964 { 1965 1966 if (hi2c->State == HAL_I2C_STATE_READY) 1967 { 1968 if ((pData == NULL) || (Size == 0U)) 1969 { 1970 return HAL_ERROR; 1971 } 1972 1973 /* Process Locked */ 1974 __HAL_LOCK(hi2c); 1975 1976 /* Check if the I2C is already enabled */ 1977 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 1978 { 1979 /* Enable I2C peripheral */ 1980 __HAL_I2C_ENABLE(hi2c); 1981 } 1982 1983 /* Disable Pos */ 1984 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 1985 1986 hi2c->State = HAL_I2C_STATE_BUSY_RX; 1987 hi2c->Mode = HAL_I2C_MODE_SLAVE; 1988 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 1989 1990 /* Prepare transfer parameters */ 1991 hi2c->pBuffPtr = pData; 1992 hi2c->XferCount = Size; 1993 hi2c->XferSize = hi2c->XferCount; 1994 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 1995 1996 /* Enable Address Acknowledge */ 1997 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 1998 1999 /* Process Unlocked */ 2000 __HAL_UNLOCK(hi2c); 2001 2002 /* Note : The I2C interrupts must be enabled after unlocking current process 2003 to avoid the risk of I2C interrupt handle execution before current 2004 process unlock */ 2005 2006 /* Enable EVT, BUF and ERR interrupt */ 2007 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 2008 2009 return HAL_OK; 2010 } 2011 else 2012 { 2013 return HAL_BUSY; 2014 } 2015 } 2016 2017 /** 2018 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA 2019 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 2020 * the configuration information for the specified I2C. 2021 * @param DevAddress Target device address: The device 7 bits address value 2022 * in datasheet must be shifted to the left before calling the interface 2023 * @param pData Pointer to data buffer 2024 * @param Size Amount of data to be sent 2025 * @retval HAL status 2026 */ 2027 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) 2028 { 2029 __IO uint32_t count = 0U; 2030 HAL_StatusTypeDef dmaxferstatus; 2031 2032 if (hi2c->State == HAL_I2C_STATE_READY) 2033 { 2034 /* Wait until BUSY flag is reset */ 2035 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 2036 do 2037 { 2038 count--; 2039 if (count == 0U) 2040 { 2041 hi2c->PreviousState = I2C_STATE_NONE; 2042 hi2c->State = HAL_I2C_STATE_READY; 2043 hi2c->Mode = HAL_I2C_MODE_NONE; 2044 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 2045 2046 return HAL_BUSY; 2047 } 2048 } 2049 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 2050 2051 /* Process Locked */ 2052 __HAL_LOCK(hi2c); 2053 2054 /* Check if the I2C is already enabled */ 2055 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 2056 { 2057 /* Enable I2C peripheral */ 2058 __HAL_I2C_ENABLE(hi2c); 2059 } 2060 2061 /* Disable Pos */ 2062 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 2063 2064 hi2c->State = HAL_I2C_STATE_BUSY_TX; 2065 hi2c->Mode = HAL_I2C_MODE_MASTER; 2066 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 2067 2068 /* Prepare transfer parameters */ 2069 hi2c->pBuffPtr = pData; 2070 hi2c->XferCount = Size; 2071 hi2c->XferSize = hi2c->XferCount; 2072 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 2073 hi2c->Devaddress = DevAddress; 2074 2075 if (hi2c->XferSize > 0U) 2076 { 2077 if (hi2c->hdmatx != NULL) 2078 { 2079 /* Set the I2C DMA transfer complete callback */ 2080 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 2081 2082 /* Set the DMA error callback */ 2083 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 2084 2085 /* Set the unused DMA callbacks to NULL */ 2086 hi2c->hdmatx->XferHalfCpltCallback = NULL; 2087 hi2c->hdmatx->XferAbortCallback = NULL; 2088 2089 /* Enable the DMA channel */ 2090 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 2091 } 2092 else 2093 { 2094 /* Update I2C state */ 2095 hi2c->State = HAL_I2C_STATE_READY; 2096 hi2c->Mode = HAL_I2C_MODE_NONE; 2097 2098 /* Update I2C error code */ 2099 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 2100 2101 /* Process Unlocked */ 2102 __HAL_UNLOCK(hi2c); 2103 2104 return HAL_ERROR; 2105 } 2106 2107 if (dmaxferstatus == HAL_OK) 2108 { 2109 /* Process Unlocked */ 2110 __HAL_UNLOCK(hi2c); 2111 2112 /* Note : The I2C interrupts must be enabled after unlocking current process 2113 to avoid the risk of I2C interrupt handle execution before current 2114 process unlock */ 2115 2116 /* Enable EVT and ERR interrupt */ 2117 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 2118 2119 /* Enable DMA Request */ 2120 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 2121 2122 /* Enable Acknowledge */ 2123 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2124 2125 /* Generate Start */ 2126 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 2127 } 2128 else 2129 { 2130 /* Update I2C state */ 2131 hi2c->State = HAL_I2C_STATE_READY; 2132 hi2c->Mode = HAL_I2C_MODE_NONE; 2133 2134 /* Update I2C error code */ 2135 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 2136 2137 /* Process Unlocked */ 2138 __HAL_UNLOCK(hi2c); 2139 2140 return HAL_ERROR; 2141 } 2142 } 2143 else 2144 { 2145 /* Enable Acknowledge */ 2146 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2147 2148 /* Generate Start */ 2149 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 2150 2151 /* Process Unlocked */ 2152 __HAL_UNLOCK(hi2c); 2153 2154 /* Note : The I2C interrupts must be enabled after unlocking current process 2155 to avoid the risk of I2C interrupt handle execution before current 2156 process unlock */ 2157 2158 /* Enable EVT, BUF and ERR interrupt */ 2159 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 2160 } 2161 2162 return HAL_OK; 2163 } 2164 else 2165 { 2166 return HAL_BUSY; 2167 } 2168 } 2169 2170 /** 2171 * @brief Receive in master mode an amount of data in non-blocking mode with DMA 2172 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 2173 * the configuration information for the specified I2C. 2174 * @param DevAddress Target device address: The device 7 bits address value 2175 * in datasheet must be shifted to the left before calling the interface 2176 * @param pData Pointer to data buffer 2177 * @param Size Amount of data to be sent 2178 * @retval HAL status 2179 */ 2180 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) 2181 { 2182 __IO uint32_t count = 0U; 2183 HAL_StatusTypeDef dmaxferstatus; 2184 2185 if (hi2c->State == HAL_I2C_STATE_READY) 2186 { 2187 /* Wait until BUSY flag is reset */ 2188 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 2189 do 2190 { 2191 count--; 2192 if (count == 0U) 2193 { 2194 hi2c->PreviousState = I2C_STATE_NONE; 2195 hi2c->State = HAL_I2C_STATE_READY; 2196 hi2c->Mode = HAL_I2C_MODE_NONE; 2197 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 2198 2199 return HAL_BUSY; 2200 } 2201 } 2202 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 2203 2204 /* Process Locked */ 2205 __HAL_LOCK(hi2c); 2206 2207 /* Check if the I2C is already enabled */ 2208 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 2209 { 2210 /* Enable I2C peripheral */ 2211 __HAL_I2C_ENABLE(hi2c); 2212 } 2213 2214 /* Disable Pos */ 2215 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 2216 2217 hi2c->State = HAL_I2C_STATE_BUSY_RX; 2218 hi2c->Mode = HAL_I2C_MODE_MASTER; 2219 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 2220 2221 /* Prepare transfer parameters */ 2222 hi2c->pBuffPtr = pData; 2223 hi2c->XferCount = Size; 2224 hi2c->XferSize = hi2c->XferCount; 2225 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 2226 hi2c->Devaddress = DevAddress; 2227 2228 if (hi2c->XferSize > 0U) 2229 { 2230 if (hi2c->hdmarx != NULL) 2231 { 2232 /* Set the I2C DMA transfer complete callback */ 2233 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 2234 2235 /* Set the DMA error callback */ 2236 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 2237 2238 /* Set the unused DMA callbacks to NULL */ 2239 hi2c->hdmarx->XferHalfCpltCallback = NULL; 2240 hi2c->hdmarx->XferAbortCallback = NULL; 2241 2242 /* Enable the DMA channel */ 2243 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 2244 } 2245 else 2246 { 2247 /* Update I2C state */ 2248 hi2c->State = HAL_I2C_STATE_READY; 2249 hi2c->Mode = HAL_I2C_MODE_NONE; 2250 2251 /* Update I2C error code */ 2252 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 2253 2254 /* Process Unlocked */ 2255 __HAL_UNLOCK(hi2c); 2256 2257 return HAL_ERROR; 2258 } 2259 2260 if (dmaxferstatus == HAL_OK) 2261 { 2262 /* Enable Acknowledge */ 2263 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2264 2265 /* Generate Start */ 2266 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 2267 2268 /* Process Unlocked */ 2269 __HAL_UNLOCK(hi2c); 2270 2271 /* Note : The I2C interrupts must be enabled after unlocking current process 2272 to avoid the risk of I2C interrupt handle execution before current 2273 process unlock */ 2274 2275 /* Enable EVT and ERR interrupt */ 2276 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 2277 2278 /* Enable DMA Request */ 2279 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 2280 } 2281 else 2282 { 2283 /* Update I2C state */ 2284 hi2c->State = HAL_I2C_STATE_READY; 2285 hi2c->Mode = HAL_I2C_MODE_NONE; 2286 2287 /* Update I2C error code */ 2288 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 2289 2290 /* Process Unlocked */ 2291 __HAL_UNLOCK(hi2c); 2292 2293 return HAL_ERROR; 2294 } 2295 } 2296 else 2297 { 2298 /* Process Unlocked */ 2299 __HAL_UNLOCK(hi2c); 2300 2301 /* Note : The I2C interrupts must be enabled after unlocking current process 2302 to avoid the risk of I2C interrupt handle execution before current 2303 process unlock */ 2304 2305 /* Enable EVT, BUF and ERR interrupt */ 2306 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 2307 2308 /* Enable Acknowledge */ 2309 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2310 2311 /* Generate Start */ 2312 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 2313 } 2314 2315 return HAL_OK; 2316 } 2317 else 2318 { 2319 return HAL_BUSY; 2320 } 2321 } 2322 2323 /** 2324 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA 2325 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 2326 * the configuration information for the specified I2C. 2327 * @param pData Pointer to data buffer 2328 * @param Size Amount of data to be sent 2329 * @retval HAL status 2330 */ 2331 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) 2332 { 2333 HAL_StatusTypeDef dmaxferstatus; 2334 2335 if (hi2c->State == HAL_I2C_STATE_READY) 2336 { 2337 if ((pData == NULL) || (Size == 0U)) 2338 { 2339 return HAL_ERROR; 2340 } 2341 2342 /* Process Locked */ 2343 __HAL_LOCK(hi2c); 2344 2345 /* Check if the I2C is already enabled */ 2346 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 2347 { 2348 /* Enable I2C peripheral */ 2349 __HAL_I2C_ENABLE(hi2c); 2350 } 2351 2352 /* Disable Pos */ 2353 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 2354 2355 hi2c->State = HAL_I2C_STATE_BUSY_TX; 2356 hi2c->Mode = HAL_I2C_MODE_SLAVE; 2357 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 2358 2359 /* Prepare transfer parameters */ 2360 hi2c->pBuffPtr = pData; 2361 hi2c->XferCount = Size; 2362 hi2c->XferSize = hi2c->XferCount; 2363 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 2364 2365 if (hi2c->hdmatx != NULL) 2366 { 2367 /* Set the I2C DMA transfer complete callback */ 2368 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 2369 2370 /* Set the DMA error callback */ 2371 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 2372 2373 /* Set the unused DMA callbacks to NULL */ 2374 hi2c->hdmatx->XferHalfCpltCallback = NULL; 2375 hi2c->hdmatx->XferAbortCallback = NULL; 2376 2377 /* Enable the DMA channel */ 2378 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 2379 } 2380 else 2381 { 2382 /* Update I2C state */ 2383 hi2c->State = HAL_I2C_STATE_LISTEN; 2384 hi2c->Mode = HAL_I2C_MODE_NONE; 2385 2386 /* Update I2C error code */ 2387 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 2388 2389 /* Process Unlocked */ 2390 __HAL_UNLOCK(hi2c); 2391 2392 return HAL_ERROR; 2393 } 2394 2395 if (dmaxferstatus == HAL_OK) 2396 { 2397 /* Enable Address Acknowledge */ 2398 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2399 2400 /* Process Unlocked */ 2401 __HAL_UNLOCK(hi2c); 2402 2403 /* Note : The I2C interrupts must be enabled after unlocking current process 2404 to avoid the risk of I2C interrupt handle execution before current 2405 process unlock */ 2406 /* Enable EVT and ERR interrupt */ 2407 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 2408 2409 /* Enable DMA Request */ 2410 hi2c->Instance->CR2 |= I2C_CR2_DMAEN; 2411 2412 return HAL_OK; 2413 } 2414 else 2415 { 2416 /* Update I2C state */ 2417 hi2c->State = HAL_I2C_STATE_READY; 2418 hi2c->Mode = HAL_I2C_MODE_NONE; 2419 2420 /* Update I2C error code */ 2421 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 2422 2423 /* Process Unlocked */ 2424 __HAL_UNLOCK(hi2c); 2425 2426 return HAL_ERROR; 2427 } 2428 } 2429 else 2430 { 2431 return HAL_BUSY; 2432 } 2433 } 2434 2435 /** 2436 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA 2437 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 2438 * the configuration information for the specified I2C. 2439 * @param pData Pointer to data buffer 2440 * @param Size Amount of data to be sent 2441 * @retval HAL status 2442 */ 2443 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) 2444 { 2445 HAL_StatusTypeDef dmaxferstatus; 2446 2447 if (hi2c->State == HAL_I2C_STATE_READY) 2448 { 2449 if ((pData == NULL) || (Size == 0U)) 2450 { 2451 return HAL_ERROR; 2452 } 2453 2454 /* Process Locked */ 2455 __HAL_LOCK(hi2c); 2456 2457 /* Check if the I2C is already enabled */ 2458 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 2459 { 2460 /* Enable I2C peripheral */ 2461 __HAL_I2C_ENABLE(hi2c); 2462 } 2463 2464 /* Disable Pos */ 2465 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 2466 2467 hi2c->State = HAL_I2C_STATE_BUSY_RX; 2468 hi2c->Mode = HAL_I2C_MODE_SLAVE; 2469 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 2470 2471 /* Prepare transfer parameters */ 2472 hi2c->pBuffPtr = pData; 2473 hi2c->XferCount = Size; 2474 hi2c->XferSize = hi2c->XferCount; 2475 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 2476 2477 if (hi2c->hdmarx != NULL) 2478 { 2479 /* Set the I2C DMA transfer complete callback */ 2480 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 2481 2482 /* Set the DMA error callback */ 2483 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 2484 2485 /* Set the unused DMA callbacks to NULL */ 2486 hi2c->hdmarx->XferHalfCpltCallback = NULL; 2487 hi2c->hdmarx->XferAbortCallback = NULL; 2488 2489 /* Enable the DMA channel */ 2490 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 2491 } 2492 else 2493 { 2494 /* Update I2C state */ 2495 hi2c->State = HAL_I2C_STATE_LISTEN; 2496 hi2c->Mode = HAL_I2C_MODE_NONE; 2497 2498 /* Update I2C error code */ 2499 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 2500 2501 /* Process Unlocked */ 2502 __HAL_UNLOCK(hi2c); 2503 2504 return HAL_ERROR; 2505 } 2506 2507 if (dmaxferstatus == HAL_OK) 2508 { 2509 /* Enable Address Acknowledge */ 2510 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2511 2512 /* Process Unlocked */ 2513 __HAL_UNLOCK(hi2c); 2514 2515 /* Note : The I2C interrupts must be enabled after unlocking current process 2516 to avoid the risk of I2C interrupt handle execution before current 2517 process unlock */ 2518 /* Enable EVT and ERR interrupt */ 2519 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 2520 2521 /* Enable DMA Request */ 2522 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 2523 2524 return HAL_OK; 2525 } 2526 else 2527 { 2528 /* Update I2C state */ 2529 hi2c->State = HAL_I2C_STATE_READY; 2530 hi2c->Mode = HAL_I2C_MODE_NONE; 2531 2532 /* Update I2C error code */ 2533 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 2534 2535 /* Process Unlocked */ 2536 __HAL_UNLOCK(hi2c); 2537 2538 return HAL_ERROR; 2539 } 2540 } 2541 else 2542 { 2543 return HAL_BUSY; 2544 } 2545 } 2546 2547 /** 2548 * @brief Write an amount of data in blocking mode to a specific memory address 2549 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 2550 * the configuration information for the specified I2C. 2551 * @param DevAddress Target device address: The device 7 bits address value 2552 * in datasheet must be shifted to the left before calling the interface 2553 * @param MemAddress Internal memory address 2554 * @param MemAddSize Size of internal memory address 2555 * @param pData Pointer to data buffer 2556 * @param Size Amount of data to be sent 2557 * @param Timeout Timeout duration 2558 * @retval HAL status 2559 */ 2560 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) 2561 { 2562 /* Init tickstart for timeout management*/ 2563 uint32_t tickstart = HAL_GetTick(); 2564 2565 /* Check the parameters */ 2566 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 2567 2568 if (hi2c->State == HAL_I2C_STATE_READY) 2569 { 2570 /* Wait until BUSY flag is reset */ 2571 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 2572 { 2573 return HAL_BUSY; 2574 } 2575 2576 /* Process Locked */ 2577 __HAL_LOCK(hi2c); 2578 2579 /* Check if the I2C is already enabled */ 2580 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 2581 { 2582 /* Enable I2C peripheral */ 2583 __HAL_I2C_ENABLE(hi2c); 2584 } 2585 2586 /* Disable Pos */ 2587 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 2588 2589 hi2c->State = HAL_I2C_STATE_BUSY_TX; 2590 hi2c->Mode = HAL_I2C_MODE_MEM; 2591 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 2592 2593 /* Prepare transfer parameters */ 2594 hi2c->pBuffPtr = pData; 2595 hi2c->XferCount = Size; 2596 hi2c->XferSize = hi2c->XferCount; 2597 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 2598 2599 /* Send Slave Address and Memory Address */ 2600 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 2601 { 2602 return HAL_ERROR; 2603 } 2604 2605 while (hi2c->XferSize > 0U) 2606 { 2607 /* Wait until TXE flag is set */ 2608 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 2609 { 2610 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 2611 { 2612 /* Generate Stop */ 2613 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 2614 } 2615 return HAL_ERROR; 2616 } 2617 2618 /* Write data to DR */ 2619 hi2c->Instance->DR = *hi2c->pBuffPtr; 2620 2621 /* Increment Buffer pointer */ 2622 hi2c->pBuffPtr++; 2623 2624 /* Update counter */ 2625 hi2c->XferSize--; 2626 hi2c->XferCount--; 2627 2628 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 2629 { 2630 /* Write data to DR */ 2631 hi2c->Instance->DR = *hi2c->pBuffPtr; 2632 2633 /* Increment Buffer pointer */ 2634 hi2c->pBuffPtr++; 2635 2636 /* Update counter */ 2637 hi2c->XferSize--; 2638 hi2c->XferCount--; 2639 } 2640 } 2641 2642 /* Wait until BTF flag is set */ 2643 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 2644 { 2645 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 2646 { 2647 /* Generate Stop */ 2648 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 2649 } 2650 return HAL_ERROR; 2651 } 2652 2653 /* Generate Stop */ 2654 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 2655 2656 hi2c->State = HAL_I2C_STATE_READY; 2657 hi2c->Mode = HAL_I2C_MODE_NONE; 2658 2659 /* Process Unlocked */ 2660 __HAL_UNLOCK(hi2c); 2661 2662 return HAL_OK; 2663 } 2664 else 2665 { 2666 return HAL_BUSY; 2667 } 2668 } 2669 2670 /** 2671 * @brief Read an amount of data in blocking mode from a specific memory address 2672 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 2673 * the configuration information for the specified I2C. 2674 * @param DevAddress Target device address: The device 7 bits address value 2675 * in datasheet must be shifted to the left before calling the interface 2676 * @param MemAddress Internal memory address 2677 * @param MemAddSize Size of internal memory address 2678 * @param pData Pointer to data buffer 2679 * @param Size Amount of data to be sent 2680 * @param Timeout Timeout duration 2681 * @retval HAL status 2682 */ 2683 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) 2684 { 2685 __IO uint32_t count = 0U; 2686 2687 /* Init tickstart for timeout management*/ 2688 uint32_t tickstart = HAL_GetTick(); 2689 2690 /* Check the parameters */ 2691 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 2692 2693 if (hi2c->State == HAL_I2C_STATE_READY) 2694 { 2695 /* Wait until BUSY flag is reset */ 2696 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 2697 { 2698 return HAL_BUSY; 2699 } 2700 2701 /* Process Locked */ 2702 __HAL_LOCK(hi2c); 2703 2704 /* Check if the I2C is already enabled */ 2705 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 2706 { 2707 /* Enable I2C peripheral */ 2708 __HAL_I2C_ENABLE(hi2c); 2709 } 2710 2711 /* Disable Pos */ 2712 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 2713 2714 hi2c->State = HAL_I2C_STATE_BUSY_RX; 2715 hi2c->Mode = HAL_I2C_MODE_MEM; 2716 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 2717 2718 /* Prepare transfer parameters */ 2719 hi2c->pBuffPtr = pData; 2720 hi2c->XferCount = Size; 2721 hi2c->XferSize = hi2c->XferCount; 2722 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 2723 2724 /* Send Slave Address and Memory Address */ 2725 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 2726 { 2727 return HAL_ERROR; 2728 } 2729 2730 if (hi2c->XferSize == 0U) 2731 { 2732 /* Clear ADDR flag */ 2733 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 2734 2735 /* Generate Stop */ 2736 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 2737 } 2738 else if (hi2c->XferSize == 1U) 2739 { 2740 /* Disable Acknowledge */ 2741 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2742 2743 /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 2744 software sequence must complete before the current byte end of transfer */ 2745 __disable_irq(); 2746 2747 /* Clear ADDR flag */ 2748 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 2749 2750 /* Generate Stop */ 2751 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 2752 2753 /* Re-enable IRQs */ 2754 __enable_irq(); 2755 } 2756 else if (hi2c->XferSize == 2U) 2757 { 2758 /* Enable Pos */ 2759 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 2760 2761 /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 2762 software sequence must complete before the current byte end of transfer */ 2763 __disable_irq(); 2764 2765 /* Clear ADDR flag */ 2766 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 2767 2768 /* Disable Acknowledge */ 2769 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2770 2771 /* Re-enable IRQs */ 2772 __enable_irq(); 2773 } 2774 else 2775 { 2776 /* Enable Acknowledge */ 2777 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2778 /* Clear ADDR flag */ 2779 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 2780 } 2781 2782 while (hi2c->XferSize > 0U) 2783 { 2784 if (hi2c->XferSize <= 3U) 2785 { 2786 /* One byte */ 2787 if (hi2c->XferSize == 1U) 2788 { 2789 /* Wait until RXNE flag is set */ 2790 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 2791 { 2792 return HAL_ERROR; 2793 } 2794 2795 /* Read data from DR */ 2796 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 2797 2798 /* Increment Buffer pointer */ 2799 hi2c->pBuffPtr++; 2800 2801 /* Update counter */ 2802 hi2c->XferSize--; 2803 hi2c->XferCount--; 2804 } 2805 /* Two bytes */ 2806 else if (hi2c->XferSize == 2U) 2807 { 2808 /* Wait until BTF flag is set */ 2809 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 2810 { 2811 return HAL_ERROR; 2812 } 2813 2814 /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 2815 software sequence must complete before the current byte end of transfer */ 2816 __disable_irq(); 2817 2818 /* Generate Stop */ 2819 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 2820 2821 /* Read data from DR */ 2822 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 2823 2824 /* Increment Buffer pointer */ 2825 hi2c->pBuffPtr++; 2826 2827 /* Update counter */ 2828 hi2c->XferSize--; 2829 hi2c->XferCount--; 2830 2831 /* Re-enable IRQs */ 2832 __enable_irq(); 2833 2834 /* Read data from DR */ 2835 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 2836 2837 /* Increment Buffer pointer */ 2838 hi2c->pBuffPtr++; 2839 2840 /* Update counter */ 2841 hi2c->XferSize--; 2842 hi2c->XferCount--; 2843 } 2844 /* 3 Last bytes */ 2845 else 2846 { 2847 /* Wait until BTF flag is set */ 2848 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 2849 { 2850 return HAL_ERROR; 2851 } 2852 2853 /* Disable Acknowledge */ 2854 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2855 2856 /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 2857 software sequence must complete before the current byte end of transfer */ 2858 __disable_irq(); 2859 2860 /* Read data from DR */ 2861 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 2862 2863 /* Increment Buffer pointer */ 2864 hi2c->pBuffPtr++; 2865 2866 /* Update counter */ 2867 hi2c->XferSize--; 2868 hi2c->XferCount--; 2869 2870 /* Wait until BTF flag is set */ 2871 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 2872 do 2873 { 2874 count--; 2875 if (count == 0U) 2876 { 2877 hi2c->PreviousState = I2C_STATE_NONE; 2878 hi2c->State = HAL_I2C_STATE_READY; 2879 hi2c->Mode = HAL_I2C_MODE_NONE; 2880 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 2881 2882 /* Re-enable IRQs */ 2883 __enable_irq(); 2884 2885 /* Process Unlocked */ 2886 __HAL_UNLOCK(hi2c); 2887 2888 return HAL_ERROR; 2889 } 2890 } 2891 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); 2892 2893 /* Generate Stop */ 2894 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 2895 2896 /* Read data from DR */ 2897 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 2898 2899 /* Increment Buffer pointer */ 2900 hi2c->pBuffPtr++; 2901 2902 /* Update counter */ 2903 hi2c->XferSize--; 2904 hi2c->XferCount--; 2905 2906 /* Re-enable IRQs */ 2907 __enable_irq(); 2908 2909 /* Read data from DR */ 2910 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 2911 2912 /* Increment Buffer pointer */ 2913 hi2c->pBuffPtr++; 2914 2915 /* Update counter */ 2916 hi2c->XferSize--; 2917 hi2c->XferCount--; 2918 } 2919 } 2920 else 2921 { 2922 /* Wait until RXNE flag is set */ 2923 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 2924 { 2925 return HAL_ERROR; 2926 } 2927 2928 /* Read data from DR */ 2929 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 2930 2931 /* Increment Buffer pointer */ 2932 hi2c->pBuffPtr++; 2933 2934 /* Update counter */ 2935 hi2c->XferSize--; 2936 hi2c->XferCount--; 2937 2938 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 2939 { 2940 if (hi2c->XferSize == 3U) 2941 { 2942 /* Disable Acknowledge */ 2943 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 2944 } 2945 /* Read data from DR */ 2946 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 2947 2948 /* Increment Buffer pointer */ 2949 hi2c->pBuffPtr++; 2950 2951 /* Update counter */ 2952 hi2c->XferSize--; 2953 hi2c->XferCount--; 2954 } 2955 } 2956 } 2957 2958 hi2c->State = HAL_I2C_STATE_READY; 2959 hi2c->Mode = HAL_I2C_MODE_NONE; 2960 2961 /* Process Unlocked */ 2962 __HAL_UNLOCK(hi2c); 2963 2964 return HAL_OK; 2965 } 2966 else 2967 { 2968 return HAL_BUSY; 2969 } 2970 } 2971 2972 /** 2973 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address 2974 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 2975 * the configuration information for the specified I2C. 2976 * @param DevAddress Target device address: The device 7 bits address value 2977 * in datasheet must be shifted to the left before calling the interface 2978 * @param MemAddress Internal memory address 2979 * @param MemAddSize Size of internal memory address 2980 * @param pData Pointer to data buffer 2981 * @param Size Amount of data to be sent 2982 * @retval HAL status 2983 */ 2984 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) 2985 { 2986 __IO uint32_t count = 0U; 2987 2988 /* Check the parameters */ 2989 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 2990 2991 if (hi2c->State == HAL_I2C_STATE_READY) 2992 { 2993 /* Wait until BUSY flag is reset */ 2994 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 2995 do 2996 { 2997 count--; 2998 if (count == 0U) 2999 { 3000 hi2c->PreviousState = I2C_STATE_NONE; 3001 hi2c->State = HAL_I2C_STATE_READY; 3002 hi2c->Mode = HAL_I2C_MODE_NONE; 3003 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 3004 3005 return HAL_BUSY; 3006 } 3007 } 3008 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 3009 3010 /* Process Locked */ 3011 __HAL_LOCK(hi2c); 3012 3013 /* Check if the I2C is already enabled */ 3014 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 3015 { 3016 /* Enable I2C peripheral */ 3017 __HAL_I2C_ENABLE(hi2c); 3018 } 3019 3020 /* Disable Pos */ 3021 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 3022 3023 hi2c->State = HAL_I2C_STATE_BUSY_TX; 3024 hi2c->Mode = HAL_I2C_MODE_MEM; 3025 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3026 3027 /* Prepare transfer parameters */ 3028 hi2c->pBuffPtr = pData; 3029 hi2c->XferCount = Size; 3030 hi2c->XferSize = hi2c->XferCount; 3031 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 3032 hi2c->Devaddress = DevAddress; 3033 hi2c->Memaddress = MemAddress; 3034 hi2c->MemaddSize = MemAddSize; 3035 hi2c->EventCount = 0U; 3036 3037 /* Generate Start */ 3038 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 3039 3040 /* Process Unlocked */ 3041 __HAL_UNLOCK(hi2c); 3042 3043 /* Note : The I2C interrupts must be enabled after unlocking current process 3044 to avoid the risk of I2C interrupt handle execution before current 3045 process unlock */ 3046 3047 /* Enable EVT, BUF and ERR interrupt */ 3048 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 3049 3050 return HAL_OK; 3051 } 3052 else 3053 { 3054 return HAL_BUSY; 3055 } 3056 } 3057 3058 /** 3059 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address 3060 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 3061 * the configuration information for the specified I2C. 3062 * @param DevAddress Target device address 3063 * @param MemAddress Internal memory address 3064 * @param MemAddSize Size of internal memory address 3065 * @param pData Pointer to data buffer 3066 * @param Size Amount of data to be sent 3067 * @retval HAL status 3068 */ 3069 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) 3070 { 3071 __IO uint32_t count = 0U; 3072 3073 /* Check the parameters */ 3074 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 3075 3076 if (hi2c->State == HAL_I2C_STATE_READY) 3077 { 3078 /* Wait until BUSY flag is reset */ 3079 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 3080 do 3081 { 3082 count--; 3083 if (count == 0U) 3084 { 3085 hi2c->PreviousState = I2C_STATE_NONE; 3086 hi2c->State = HAL_I2C_STATE_READY; 3087 hi2c->Mode = HAL_I2C_MODE_NONE; 3088 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 3089 3090 return HAL_BUSY; 3091 } 3092 } 3093 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 3094 3095 /* Process Locked */ 3096 __HAL_LOCK(hi2c); 3097 3098 /* Check if the I2C is already enabled */ 3099 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 3100 { 3101 /* Enable I2C peripheral */ 3102 __HAL_I2C_ENABLE(hi2c); 3103 } 3104 3105 /* Disable Pos */ 3106 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 3107 3108 hi2c->State = HAL_I2C_STATE_BUSY_RX; 3109 hi2c->Mode = HAL_I2C_MODE_MEM; 3110 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3111 3112 /* Prepare transfer parameters */ 3113 hi2c->pBuffPtr = pData; 3114 hi2c->XferCount = Size; 3115 hi2c->XferSize = hi2c->XferCount; 3116 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 3117 hi2c->Devaddress = DevAddress; 3118 hi2c->Memaddress = MemAddress; 3119 hi2c->MemaddSize = MemAddSize; 3120 hi2c->EventCount = 0U; 3121 3122 /* Enable Acknowledge */ 3123 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 3124 3125 /* Generate Start */ 3126 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 3127 3128 /* Process Unlocked */ 3129 __HAL_UNLOCK(hi2c); 3130 3131 if (hi2c->XferSize > 0U) 3132 { 3133 /* Note : The I2C interrupts must be enabled after unlocking current process 3134 to avoid the risk of I2C interrupt handle execution before current 3135 process unlock */ 3136 3137 /* Enable EVT, BUF and ERR interrupt */ 3138 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 3139 } 3140 return HAL_OK; 3141 } 3142 else 3143 { 3144 return HAL_BUSY; 3145 } 3146 } 3147 3148 /** 3149 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address 3150 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 3151 * the configuration information for the specified I2C. 3152 * @param DevAddress Target device address: The device 7 bits address value 3153 * in datasheet must be shifted to the left before calling the interface 3154 * @param MemAddress Internal memory address 3155 * @param MemAddSize Size of internal memory address 3156 * @param pData Pointer to data buffer 3157 * @param Size Amount of data to be sent 3158 * @retval HAL status 3159 */ 3160 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) 3161 { 3162 __IO uint32_t count = 0U; 3163 HAL_StatusTypeDef dmaxferstatus; 3164 3165 /* Init tickstart for timeout management*/ 3166 uint32_t tickstart = HAL_GetTick(); 3167 3168 /* Check the parameters */ 3169 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 3170 3171 if (hi2c->State == HAL_I2C_STATE_READY) 3172 { 3173 /* Wait until BUSY flag is reset */ 3174 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 3175 do 3176 { 3177 count--; 3178 if (count == 0U) 3179 { 3180 hi2c->PreviousState = I2C_STATE_NONE; 3181 hi2c->State = HAL_I2C_STATE_READY; 3182 hi2c->Mode = HAL_I2C_MODE_NONE; 3183 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 3184 3185 return HAL_BUSY; 3186 } 3187 } 3188 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 3189 3190 /* Process Locked */ 3191 __HAL_LOCK(hi2c); 3192 3193 /* Check if the I2C is already enabled */ 3194 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 3195 { 3196 /* Enable I2C peripheral */ 3197 __HAL_I2C_ENABLE(hi2c); 3198 } 3199 3200 /* Disable Pos */ 3201 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 3202 3203 hi2c->State = HAL_I2C_STATE_BUSY_TX; 3204 hi2c->Mode = HAL_I2C_MODE_MEM; 3205 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3206 3207 /* Prepare transfer parameters */ 3208 hi2c->pBuffPtr = pData; 3209 hi2c->XferCount = Size; 3210 hi2c->XferSize = hi2c->XferCount; 3211 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 3212 hi2c->Devaddress = DevAddress; 3213 hi2c->Memaddress = MemAddress; 3214 hi2c->MemaddSize = MemAddSize; 3215 hi2c->EventCount = 0U; 3216 3217 if (hi2c->XferSize > 0U) 3218 { 3219 if (hi2c->hdmatx != NULL) 3220 { 3221 /* Set the I2C DMA transfer complete callback */ 3222 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 3223 3224 /* Set the DMA error callback */ 3225 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 3226 3227 /* Set the unused DMA callbacks to NULL */ 3228 hi2c->hdmatx->XferHalfCpltCallback = NULL; 3229 hi2c->hdmatx->XferAbortCallback = NULL; 3230 3231 /* Enable the DMA channel */ 3232 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 3233 } 3234 else 3235 { 3236 /* Update I2C state */ 3237 hi2c->State = HAL_I2C_STATE_READY; 3238 hi2c->Mode = HAL_I2C_MODE_NONE; 3239 3240 /* Update I2C error code */ 3241 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 3242 3243 /* Process Unlocked */ 3244 __HAL_UNLOCK(hi2c); 3245 3246 return HAL_ERROR; 3247 } 3248 3249 if (dmaxferstatus == HAL_OK) 3250 { 3251 /* Send Slave Address and Memory Address */ 3252 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) 3253 { 3254 /* Abort the ongoing DMA */ 3255 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); 3256 3257 /* Prevent unused argument(s) compilation and MISRA warning */ 3258 UNUSED(dmaxferstatus); 3259 3260 /* Set the unused I2C DMA transfer complete callback to NULL */ 3261 hi2c->hdmatx->XferCpltCallback = NULL; 3262 3263 /* Disable Acknowledge */ 3264 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 3265 3266 hi2c->XferSize = 0U; 3267 hi2c->XferCount = 0U; 3268 3269 /* Disable I2C peripheral to prevent dummy data in buffer */ 3270 __HAL_I2C_DISABLE(hi2c); 3271 3272 return HAL_ERROR; 3273 } 3274 3275 /* Clear ADDR flag */ 3276 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 3277 3278 /* Process Unlocked */ 3279 __HAL_UNLOCK(hi2c); 3280 3281 /* Note : The I2C interrupts must be enabled after unlocking current process 3282 to avoid the risk of I2C interrupt handle execution before current 3283 process unlock */ 3284 /* Enable ERR interrupt */ 3285 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); 3286 3287 /* Enable DMA Request */ 3288 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 3289 3290 return HAL_OK; 3291 } 3292 else 3293 { 3294 /* Update I2C state */ 3295 hi2c->State = HAL_I2C_STATE_READY; 3296 hi2c->Mode = HAL_I2C_MODE_NONE; 3297 3298 /* Update I2C error code */ 3299 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 3300 3301 /* Process Unlocked */ 3302 __HAL_UNLOCK(hi2c); 3303 3304 return HAL_ERROR; 3305 } 3306 } 3307 else 3308 { 3309 /* Update I2C state */ 3310 hi2c->State = HAL_I2C_STATE_READY; 3311 hi2c->Mode = HAL_I2C_MODE_NONE; 3312 3313 /* Update I2C error code */ 3314 hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; 3315 3316 /* Process Unlocked */ 3317 __HAL_UNLOCK(hi2c); 3318 3319 return HAL_ERROR; 3320 } 3321 } 3322 else 3323 { 3324 return HAL_BUSY; 3325 } 3326 } 3327 3328 /** 3329 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. 3330 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 3331 * the configuration information for the specified I2C. 3332 * @param DevAddress Target device address: The device 7 bits address value 3333 * in datasheet must be shifted to the left before calling the interface 3334 * @param MemAddress Internal memory address 3335 * @param MemAddSize Size of internal memory address 3336 * @param pData Pointer to data buffer 3337 * @param Size Amount of data to be read 3338 * @retval HAL status 3339 */ 3340 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) 3341 { 3342 /* Init tickstart for timeout management*/ 3343 uint32_t tickstart = HAL_GetTick(); 3344 __IO uint32_t count = 0U; 3345 HAL_StatusTypeDef dmaxferstatus; 3346 3347 /* Check the parameters */ 3348 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 3349 3350 if (hi2c->State == HAL_I2C_STATE_READY) 3351 { 3352 /* Wait until BUSY flag is reset */ 3353 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 3354 do 3355 { 3356 count--; 3357 if (count == 0U) 3358 { 3359 hi2c->PreviousState = I2C_STATE_NONE; 3360 hi2c->State = HAL_I2C_STATE_READY; 3361 hi2c->Mode = HAL_I2C_MODE_NONE; 3362 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 3363 3364 return HAL_BUSY; 3365 } 3366 } 3367 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 3368 3369 /* Process Locked */ 3370 __HAL_LOCK(hi2c); 3371 3372 /* Check if the I2C is already enabled */ 3373 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 3374 { 3375 /* Enable I2C peripheral */ 3376 __HAL_I2C_ENABLE(hi2c); 3377 } 3378 3379 /* Disable Pos */ 3380 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 3381 3382 hi2c->State = HAL_I2C_STATE_BUSY_RX; 3383 hi2c->Mode = HAL_I2C_MODE_MEM; 3384 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3385 3386 /* Prepare transfer parameters */ 3387 hi2c->pBuffPtr = pData; 3388 hi2c->XferCount = Size; 3389 hi2c->XferSize = hi2c->XferCount; 3390 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 3391 hi2c->Devaddress = DevAddress; 3392 hi2c->Memaddress = MemAddress; 3393 hi2c->MemaddSize = MemAddSize; 3394 hi2c->EventCount = 0U; 3395 3396 if (hi2c->XferSize > 0U) 3397 { 3398 if (hi2c->hdmarx != NULL) 3399 { 3400 /* Set the I2C DMA transfer complete callback */ 3401 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 3402 3403 /* Set the DMA error callback */ 3404 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 3405 3406 /* Set the unused DMA callbacks to NULL */ 3407 hi2c->hdmarx->XferHalfCpltCallback = NULL; 3408 hi2c->hdmarx->XferAbortCallback = NULL; 3409 3410 /* Enable the DMA channel */ 3411 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 3412 } 3413 else 3414 { 3415 /* Update I2C state */ 3416 hi2c->State = HAL_I2C_STATE_READY; 3417 hi2c->Mode = HAL_I2C_MODE_NONE; 3418 3419 /* Update I2C error code */ 3420 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 3421 3422 /* Process Unlocked */ 3423 __HAL_UNLOCK(hi2c); 3424 3425 return HAL_ERROR; 3426 } 3427 3428 if (dmaxferstatus == HAL_OK) 3429 { 3430 /* Send Slave Address and Memory Address */ 3431 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) 3432 { 3433 /* Abort the ongoing DMA */ 3434 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); 3435 3436 /* Prevent unused argument(s) compilation and MISRA warning */ 3437 UNUSED(dmaxferstatus); 3438 3439 /* Set the unused I2C DMA transfer complete callback to NULL */ 3440 hi2c->hdmarx->XferCpltCallback = NULL; 3441 3442 /* Disable Acknowledge */ 3443 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 3444 3445 hi2c->XferSize = 0U; 3446 hi2c->XferCount = 0U; 3447 3448 /* Disable I2C peripheral to prevent dummy data in buffer */ 3449 __HAL_I2C_DISABLE(hi2c); 3450 3451 return HAL_ERROR; 3452 } 3453 3454 if (hi2c->XferSize == 1U) 3455 { 3456 /* Disable Acknowledge */ 3457 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 3458 } 3459 else 3460 { 3461 /* Enable Last DMA bit */ 3462 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 3463 } 3464 3465 /* Clear ADDR flag */ 3466 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 3467 3468 /* Process Unlocked */ 3469 __HAL_UNLOCK(hi2c); 3470 3471 /* Note : The I2C interrupts must be enabled after unlocking current process 3472 to avoid the risk of I2C interrupt handle execution before current 3473 process unlock */ 3474 /* Enable ERR interrupt */ 3475 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); 3476 3477 /* Enable DMA Request */ 3478 hi2c->Instance->CR2 |= I2C_CR2_DMAEN; 3479 } 3480 else 3481 { 3482 /* Update I2C state */ 3483 hi2c->State = HAL_I2C_STATE_READY; 3484 hi2c->Mode = HAL_I2C_MODE_NONE; 3485 3486 /* Update I2C error code */ 3487 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 3488 3489 /* Process Unlocked */ 3490 __HAL_UNLOCK(hi2c); 3491 3492 return HAL_ERROR; 3493 } 3494 } 3495 else 3496 { 3497 /* Send Slave Address and Memory Address */ 3498 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) 3499 { 3500 return HAL_ERROR; 3501 } 3502 3503 /* Clear ADDR flag */ 3504 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 3505 3506 /* Generate Stop */ 3507 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 3508 3509 hi2c->State = HAL_I2C_STATE_READY; 3510 3511 /* Process Unlocked */ 3512 __HAL_UNLOCK(hi2c); 3513 } 3514 3515 return HAL_OK; 3516 } 3517 else 3518 { 3519 return HAL_BUSY; 3520 } 3521 } 3522 3523 /** 3524 * @brief Checks if target device is ready for communication. 3525 * @note This function is used with Memory devices 3526 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 3527 * the configuration information for the specified I2C. 3528 * @param DevAddress Target device address: The device 7 bits address value 3529 * in datasheet must be shifted to the left before calling the interface 3530 * @param Trials Number of trials 3531 * @param Timeout Timeout duration 3532 * @retval HAL status 3533 */ 3534 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) 3535 { 3536 /* Get tick */ 3537 uint32_t tickstart = HAL_GetTick(); 3538 uint32_t I2C_Trials = 0U; 3539 FlagStatus tmp1; 3540 FlagStatus tmp2; 3541 3542 if (hi2c->State == HAL_I2C_STATE_READY) 3543 { 3544 /* Wait until BUSY flag is reset */ 3545 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 3546 { 3547 return HAL_BUSY; 3548 } 3549 3550 /* Process Locked */ 3551 __HAL_LOCK(hi2c); 3552 3553 /* Check if the I2C is already enabled */ 3554 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 3555 { 3556 /* Enable I2C peripheral */ 3557 __HAL_I2C_ENABLE(hi2c); 3558 } 3559 3560 /* Disable Pos */ 3561 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 3562 3563 hi2c->State = HAL_I2C_STATE_BUSY; 3564 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3565 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 3566 3567 do 3568 { 3569 /* Generate Start */ 3570 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 3571 3572 /* Wait until SB flag is set */ 3573 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) 3574 { 3575 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 3576 { 3577 hi2c->ErrorCode = HAL_I2C_WRONG_START; 3578 } 3579 return HAL_TIMEOUT; 3580 } 3581 3582 /* Send slave address */ 3583 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 3584 3585 /* Wait until ADDR or AF flag are set */ 3586 /* Get tick */ 3587 tickstart = HAL_GetTick(); 3588 3589 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); 3590 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); 3591 while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) 3592 { 3593 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 3594 { 3595 hi2c->State = HAL_I2C_STATE_TIMEOUT; 3596 } 3597 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); 3598 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); 3599 } 3600 3601 hi2c->State = HAL_I2C_STATE_READY; 3602 3603 /* Check if the ADDR flag has been set */ 3604 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) 3605 { 3606 /* Generate Stop */ 3607 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 3608 3609 /* Clear ADDR Flag */ 3610 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 3611 3612 /* Wait until BUSY flag is reset */ 3613 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 3614 { 3615 return HAL_ERROR; 3616 } 3617 3618 hi2c->State = HAL_I2C_STATE_READY; 3619 3620 /* Process Unlocked */ 3621 __HAL_UNLOCK(hi2c); 3622 3623 return HAL_OK; 3624 } 3625 else 3626 { 3627 /* Generate Stop */ 3628 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 3629 3630 /* Clear AF Flag */ 3631 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 3632 3633 /* Wait until BUSY flag is reset */ 3634 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 3635 { 3636 return HAL_ERROR; 3637 } 3638 } 3639 3640 /* Increment Trials */ 3641 I2C_Trials++; 3642 } 3643 while (I2C_Trials < Trials); 3644 3645 hi2c->State = HAL_I2C_STATE_READY; 3646 3647 /* Process Unlocked */ 3648 __HAL_UNLOCK(hi2c); 3649 3650 return HAL_ERROR; 3651 } 3652 else 3653 { 3654 return HAL_BUSY; 3655 } 3656 } 3657 3658 /** 3659 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. 3660 * @note This interface allow to manage repeated start condition when a direction change during transfer 3661 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 3662 * the configuration information for the specified I2C. 3663 * @param DevAddress Target device address: The device 7 bits address value 3664 * in datasheet must be shifted to the left before calling the interface 3665 * @param pData Pointer to data buffer 3666 * @param Size Amount of data to be sent 3667 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 3668 * @retval HAL status 3669 */ 3670 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 3671 { 3672 __IO uint32_t Prev_State = 0x00U; 3673 __IO uint32_t count = 0x00U; 3674 3675 /* Check the parameters */ 3676 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 3677 3678 if (hi2c->State == HAL_I2C_STATE_READY) 3679 { 3680 /* Check Busy Flag only if FIRST call of Master interface */ 3681 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) 3682 { 3683 /* Wait until BUSY flag is reset */ 3684 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 3685 do 3686 { 3687 count--; 3688 if (count == 0U) 3689 { 3690 hi2c->PreviousState = I2C_STATE_NONE; 3691 hi2c->State = HAL_I2C_STATE_READY; 3692 hi2c->Mode = HAL_I2C_MODE_NONE; 3693 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 3694 3695 return HAL_BUSY; 3696 } 3697 } 3698 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 3699 } 3700 3701 /* Process Locked */ 3702 __HAL_LOCK(hi2c); 3703 3704 /* Check if the I2C is already enabled */ 3705 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 3706 { 3707 /* Enable I2C peripheral */ 3708 __HAL_I2C_ENABLE(hi2c); 3709 } 3710 3711 /* Disable Pos */ 3712 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 3713 3714 hi2c->State = HAL_I2C_STATE_BUSY_TX; 3715 hi2c->Mode = HAL_I2C_MODE_MASTER; 3716 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3717 3718 /* Prepare transfer parameters */ 3719 hi2c->pBuffPtr = pData; 3720 hi2c->XferCount = Size; 3721 hi2c->XferSize = hi2c->XferCount; 3722 hi2c->XferOptions = XferOptions; 3723 hi2c->Devaddress = DevAddress; 3724 3725 Prev_State = hi2c->PreviousState; 3726 3727 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 3728 /* Mean Previous state is same as current state */ 3729 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 3730 { 3731 /* Generate Start */ 3732 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 3733 } 3734 3735 /* Process Unlocked */ 3736 __HAL_UNLOCK(hi2c); 3737 3738 /* Note : The I2C interrupts must be enabled after unlocking current process 3739 to avoid the risk of I2C interrupt handle execution before current 3740 process unlock */ 3741 3742 /* Enable EVT, BUF and ERR interrupt */ 3743 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 3744 3745 return HAL_OK; 3746 } 3747 else 3748 { 3749 return HAL_BUSY; 3750 } 3751 } 3752 3753 /** 3754 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. 3755 * @note This interface allow to manage repeated start condition when a direction change during transfer 3756 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 3757 * the configuration information for the specified I2C. 3758 * @param DevAddress Target device address: The device 7 bits address value 3759 * in datasheet must be shifted to the left before calling the interface 3760 * @param pData Pointer to data buffer 3761 * @param Size Amount of data to be sent 3762 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 3763 * @retval HAL status 3764 */ 3765 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 3766 { 3767 __IO uint32_t Prev_State = 0x00U; 3768 __IO uint32_t count = 0x00U; 3769 HAL_StatusTypeDef dmaxferstatus; 3770 3771 /* Check the parameters */ 3772 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 3773 3774 if (hi2c->State == HAL_I2C_STATE_READY) 3775 { 3776 /* Check Busy Flag only if FIRST call of Master interface */ 3777 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) 3778 { 3779 /* Wait until BUSY flag is reset */ 3780 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 3781 do 3782 { 3783 count--; 3784 if (count == 0U) 3785 { 3786 hi2c->PreviousState = I2C_STATE_NONE; 3787 hi2c->State = HAL_I2C_STATE_READY; 3788 hi2c->Mode = HAL_I2C_MODE_NONE; 3789 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 3790 3791 return HAL_BUSY; 3792 } 3793 } 3794 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 3795 } 3796 3797 /* Process Locked */ 3798 __HAL_LOCK(hi2c); 3799 3800 /* Check if the I2C is already enabled */ 3801 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 3802 { 3803 /* Enable I2C peripheral */ 3804 __HAL_I2C_ENABLE(hi2c); 3805 } 3806 3807 /* Disable Pos */ 3808 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 3809 3810 hi2c->State = HAL_I2C_STATE_BUSY_TX; 3811 hi2c->Mode = HAL_I2C_MODE_MASTER; 3812 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3813 3814 /* Prepare transfer parameters */ 3815 hi2c->pBuffPtr = pData; 3816 hi2c->XferCount = Size; 3817 hi2c->XferSize = hi2c->XferCount; 3818 hi2c->XferOptions = XferOptions; 3819 hi2c->Devaddress = DevAddress; 3820 3821 Prev_State = hi2c->PreviousState; 3822 3823 if (hi2c->XferSize > 0U) 3824 { 3825 if (hi2c->hdmatx != NULL) 3826 { 3827 /* Set the I2C DMA transfer complete callback */ 3828 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 3829 3830 /* Set the DMA error callback */ 3831 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 3832 3833 /* Set the unused DMA callbacks to NULL */ 3834 hi2c->hdmatx->XferHalfCpltCallback = NULL; 3835 hi2c->hdmatx->XferAbortCallback = NULL; 3836 3837 /* Enable the DMA channel */ 3838 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 3839 } 3840 else 3841 { 3842 /* Update I2C state */ 3843 hi2c->State = HAL_I2C_STATE_READY; 3844 hi2c->Mode = HAL_I2C_MODE_NONE; 3845 3846 /* Update I2C error code */ 3847 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 3848 3849 /* Process Unlocked */ 3850 __HAL_UNLOCK(hi2c); 3851 3852 return HAL_ERROR; 3853 } 3854 3855 if (dmaxferstatus == HAL_OK) 3856 { 3857 /* Enable Acknowledge */ 3858 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 3859 3860 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 3861 /* Mean Previous state is same as current state */ 3862 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 3863 { 3864 /* Generate Start */ 3865 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 3866 } 3867 3868 /* Process Unlocked */ 3869 __HAL_UNLOCK(hi2c); 3870 3871 /* Note : The I2C interrupts must be enabled after unlocking current process 3872 to avoid the risk of I2C interrupt handle execution before current 3873 process unlock */ 3874 3875 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ 3876 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ 3877 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) 3878 { 3879 /* Enable DMA Request */ 3880 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 3881 } 3882 3883 /* Enable EVT and ERR interrupt */ 3884 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 3885 } 3886 else 3887 { 3888 /* Update I2C state */ 3889 hi2c->State = HAL_I2C_STATE_READY; 3890 hi2c->Mode = HAL_I2C_MODE_NONE; 3891 3892 /* Update I2C error code */ 3893 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 3894 3895 /* Process Unlocked */ 3896 __HAL_UNLOCK(hi2c); 3897 3898 return HAL_ERROR; 3899 } 3900 } 3901 else 3902 { 3903 /* Enable Acknowledge */ 3904 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 3905 3906 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 3907 /* Mean Previous state is same as current state */ 3908 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 3909 { 3910 /* Generate Start */ 3911 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 3912 } 3913 3914 /* Process Unlocked */ 3915 __HAL_UNLOCK(hi2c); 3916 3917 /* Note : The I2C interrupts must be enabled after unlocking current process 3918 to avoid the risk of I2C interrupt handle execution before current 3919 process unlock */ 3920 3921 /* Enable EVT, BUF and ERR interrupt */ 3922 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 3923 } 3924 3925 return HAL_OK; 3926 } 3927 else 3928 { 3929 return HAL_BUSY; 3930 } 3931 } 3932 3933 /** 3934 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt 3935 * @note This interface allow to manage repeated start condition when a direction change during transfer 3936 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 3937 * the configuration information for the specified I2C. 3938 * @param DevAddress Target device address: The device 7 bits address value 3939 * in datasheet must be shifted to the left before calling the interface 3940 * @param pData Pointer to data buffer 3941 * @param Size Amount of data to be sent 3942 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 3943 * @retval HAL status 3944 */ 3945 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 3946 { 3947 __IO uint32_t Prev_State = 0x00U; 3948 __IO uint32_t count = 0U; 3949 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 3950 3951 /* Check the parameters */ 3952 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 3953 3954 if (hi2c->State == HAL_I2C_STATE_READY) 3955 { 3956 /* Check Busy Flag only if FIRST call of Master interface */ 3957 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) 3958 { 3959 /* Wait until BUSY flag is reset */ 3960 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 3961 do 3962 { 3963 count--; 3964 if (count == 0U) 3965 { 3966 hi2c->PreviousState = I2C_STATE_NONE; 3967 hi2c->State = HAL_I2C_STATE_READY; 3968 hi2c->Mode = HAL_I2C_MODE_NONE; 3969 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 3970 3971 return HAL_BUSY; 3972 } 3973 } 3974 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 3975 } 3976 3977 /* Process Locked */ 3978 __HAL_LOCK(hi2c); 3979 3980 /* Check if the I2C is already enabled */ 3981 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 3982 { 3983 /* Enable I2C peripheral */ 3984 __HAL_I2C_ENABLE(hi2c); 3985 } 3986 3987 /* Disable Pos */ 3988 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 3989 3990 hi2c->State = HAL_I2C_STATE_BUSY_RX; 3991 hi2c->Mode = HAL_I2C_MODE_MASTER; 3992 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 3993 3994 /* Prepare transfer parameters */ 3995 hi2c->pBuffPtr = pData; 3996 hi2c->XferCount = Size; 3997 hi2c->XferSize = hi2c->XferCount; 3998 hi2c->XferOptions = XferOptions; 3999 hi2c->Devaddress = DevAddress; 4000 4001 Prev_State = hi2c->PreviousState; 4002 4003 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) 4004 { 4005 if (Prev_State == I2C_STATE_MASTER_BUSY_RX) 4006 { 4007 /* Disable Acknowledge */ 4008 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4009 4010 /* Enable Pos */ 4011 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 4012 4013 /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ 4014 enableIT &= ~I2C_IT_BUF; 4015 } 4016 else 4017 { 4018 /* Enable Acknowledge */ 4019 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4020 } 4021 } 4022 else 4023 { 4024 /* Enable Acknowledge */ 4025 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4026 } 4027 4028 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 4029 /* Mean Previous state is same as current state */ 4030 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 4031 { 4032 /* Generate Start */ 4033 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 4034 } 4035 4036 /* Process Unlocked */ 4037 __HAL_UNLOCK(hi2c); 4038 4039 /* Note : The I2C interrupts must be enabled after unlocking current process 4040 to avoid the risk of I2C interrupt handle execution before current 4041 process unlock */ 4042 4043 /* Enable interrupts */ 4044 __HAL_I2C_ENABLE_IT(hi2c, enableIT); 4045 4046 return HAL_OK; 4047 } 4048 else 4049 { 4050 return HAL_BUSY; 4051 } 4052 } 4053 4054 /** 4055 * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA 4056 * @note This interface allow to manage repeated start condition when a direction change during transfer 4057 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4058 * the configuration information for the specified I2C. 4059 * @param DevAddress Target device address: The device 7 bits address value 4060 * in datasheet must be shifted to the left before calling the interface 4061 * @param pData Pointer to data buffer 4062 * @param Size Amount of data to be sent 4063 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 4064 * @retval HAL status 4065 */ 4066 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 4067 { 4068 __IO uint32_t Prev_State = 0x00U; 4069 __IO uint32_t count = 0U; 4070 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 4071 HAL_StatusTypeDef dmaxferstatus; 4072 4073 /* Check the parameters */ 4074 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 4075 4076 if (hi2c->State == HAL_I2C_STATE_READY) 4077 { 4078 /* Check Busy Flag only if FIRST call of Master interface */ 4079 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) 4080 { 4081 /* Wait until BUSY flag is reset */ 4082 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 4083 do 4084 { 4085 count--; 4086 if (count == 0U) 4087 { 4088 hi2c->PreviousState = I2C_STATE_NONE; 4089 hi2c->State = HAL_I2C_STATE_READY; 4090 hi2c->Mode = HAL_I2C_MODE_NONE; 4091 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 4092 4093 return HAL_BUSY; 4094 } 4095 } 4096 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 4097 } 4098 4099 /* Process Locked */ 4100 __HAL_LOCK(hi2c); 4101 4102 /* Check if the I2C is already enabled */ 4103 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 4104 { 4105 /* Enable I2C peripheral */ 4106 __HAL_I2C_ENABLE(hi2c); 4107 } 4108 4109 /* Disable Pos */ 4110 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 4111 4112 /* Clear Last DMA bit */ 4113 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 4114 4115 hi2c->State = HAL_I2C_STATE_BUSY_RX; 4116 hi2c->Mode = HAL_I2C_MODE_MASTER; 4117 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 4118 4119 /* Prepare transfer parameters */ 4120 hi2c->pBuffPtr = pData; 4121 hi2c->XferCount = Size; 4122 hi2c->XferSize = hi2c->XferCount; 4123 hi2c->XferOptions = XferOptions; 4124 hi2c->Devaddress = DevAddress; 4125 4126 Prev_State = hi2c->PreviousState; 4127 4128 if (hi2c->XferSize > 0U) 4129 { 4130 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) 4131 { 4132 if (Prev_State == I2C_STATE_MASTER_BUSY_RX) 4133 { 4134 /* Disable Acknowledge */ 4135 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4136 4137 /* Enable Pos */ 4138 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 4139 4140 /* Enable Last DMA bit */ 4141 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 4142 } 4143 else 4144 { 4145 /* Enable Acknowledge */ 4146 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4147 } 4148 } 4149 else 4150 { 4151 /* Enable Acknowledge */ 4152 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4153 4154 if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) 4155 { 4156 /* Enable Last DMA bit */ 4157 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 4158 } 4159 } 4160 if (hi2c->hdmarx != NULL) 4161 { 4162 /* Set the I2C DMA transfer complete callback */ 4163 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 4164 4165 /* Set the DMA error callback */ 4166 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 4167 4168 /* Set the unused DMA callbacks to NULL */ 4169 hi2c->hdmarx->XferHalfCpltCallback = NULL; 4170 hi2c->hdmarx->XferAbortCallback = NULL; 4171 4172 /* Enable the DMA channel */ 4173 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 4174 } 4175 else 4176 { 4177 /* Update I2C state */ 4178 hi2c->State = HAL_I2C_STATE_READY; 4179 hi2c->Mode = HAL_I2C_MODE_NONE; 4180 4181 /* Update I2C error code */ 4182 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 4183 4184 /* Process Unlocked */ 4185 __HAL_UNLOCK(hi2c); 4186 4187 return HAL_ERROR; 4188 } 4189 if (dmaxferstatus == HAL_OK) 4190 { 4191 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 4192 /* Mean Previous state is same as current state */ 4193 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 4194 { 4195 /* Generate Start */ 4196 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 4197 4198 /* Update interrupt for only EVT and ERR */ 4199 enableIT = (I2C_IT_EVT | I2C_IT_ERR); 4200 } 4201 else 4202 { 4203 /* Update interrupt for only ERR */ 4204 enableIT = I2C_IT_ERR; 4205 } 4206 4207 /* Process Unlocked */ 4208 __HAL_UNLOCK(hi2c); 4209 4210 /* Note : The I2C interrupts must be enabled after unlocking current process 4211 to avoid the risk of I2C interrupt handle execution before current 4212 process unlock */ 4213 4214 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ 4215 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ 4216 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) 4217 { 4218 /* Enable DMA Request */ 4219 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 4220 } 4221 4222 /* Enable EVT and ERR interrupt */ 4223 __HAL_I2C_ENABLE_IT(hi2c, enableIT); 4224 } 4225 else 4226 { 4227 /* Update I2C state */ 4228 hi2c->State = HAL_I2C_STATE_READY; 4229 hi2c->Mode = HAL_I2C_MODE_NONE; 4230 4231 /* Update I2C error code */ 4232 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 4233 4234 /* Process Unlocked */ 4235 __HAL_UNLOCK(hi2c); 4236 4237 return HAL_ERROR; 4238 } 4239 } 4240 else 4241 { 4242 /* Enable Acknowledge */ 4243 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4244 4245 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 4246 /* Mean Previous state is same as current state */ 4247 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 4248 { 4249 /* Generate Start */ 4250 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 4251 } 4252 4253 /* Process Unlocked */ 4254 __HAL_UNLOCK(hi2c); 4255 4256 /* Note : The I2C interrupts must be enabled after unlocking current process 4257 to avoid the risk of I2C interrupt handle execution before current 4258 process unlock */ 4259 4260 /* Enable interrupts */ 4261 __HAL_I2C_ENABLE_IT(hi2c, enableIT); 4262 } 4263 return HAL_OK; 4264 } 4265 else 4266 { 4267 return HAL_BUSY; 4268 } 4269 } 4270 4271 /** 4272 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt 4273 * @note This interface allow to manage repeated start condition when a direction change during transfer 4274 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4275 * the configuration information for the specified I2C. 4276 * @param pData Pointer to data buffer 4277 * @param Size Amount of data to be sent 4278 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 4279 * @retval HAL status 4280 */ 4281 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 4282 { 4283 /* Check the parameters */ 4284 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 4285 4286 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 4287 { 4288 if ((pData == NULL) || (Size == 0U)) 4289 { 4290 return HAL_ERROR; 4291 } 4292 4293 /* Process Locked */ 4294 __HAL_LOCK(hi2c); 4295 4296 /* Check if the I2C is already enabled */ 4297 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 4298 { 4299 /* Enable I2C peripheral */ 4300 __HAL_I2C_ENABLE(hi2c); 4301 } 4302 4303 /* Disable Pos */ 4304 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 4305 4306 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; 4307 hi2c->Mode = HAL_I2C_MODE_SLAVE; 4308 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 4309 4310 /* Prepare transfer parameters */ 4311 hi2c->pBuffPtr = pData; 4312 hi2c->XferCount = Size; 4313 hi2c->XferSize = hi2c->XferCount; 4314 hi2c->XferOptions = XferOptions; 4315 4316 /* Clear ADDR flag */ 4317 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 4318 4319 /* Process Unlocked */ 4320 __HAL_UNLOCK(hi2c); 4321 4322 /* Note : The I2C interrupts must be enabled after unlocking current process 4323 to avoid the risk of I2C interrupt handle execution before current 4324 process unlock */ 4325 4326 /* Enable EVT, BUF and ERR interrupt */ 4327 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 4328 4329 return HAL_OK; 4330 } 4331 else 4332 { 4333 return HAL_BUSY; 4334 } 4335 } 4336 4337 /** 4338 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA 4339 * @note This interface allow to manage repeated start condition when a direction change during transfer 4340 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4341 * the configuration information for the specified I2C. 4342 * @param pData Pointer to data buffer 4343 * @param Size Amount of data to be sent 4344 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 4345 * @retval HAL status 4346 */ 4347 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 4348 { 4349 HAL_StatusTypeDef dmaxferstatus; 4350 4351 /* Check the parameters */ 4352 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 4353 4354 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 4355 { 4356 if ((pData == NULL) || (Size == 0U)) 4357 { 4358 return HAL_ERROR; 4359 } 4360 4361 /* Process Locked */ 4362 __HAL_LOCK(hi2c); 4363 4364 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ 4365 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 4366 4367 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ 4368 /* and then toggle the HAL slave RX state to TX state */ 4369 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 4370 { 4371 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 4372 { 4373 /* Abort DMA Xfer if any */ 4374 if (hi2c->hdmarx != NULL) 4375 { 4376 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 4377 4378 /* Set the I2C DMA Abort callback : 4379 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 4380 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 4381 4382 /* Abort DMA RX */ 4383 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 4384 { 4385 /* Call Directly XferAbortCallback function in case of error */ 4386 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 4387 } 4388 } 4389 } 4390 } 4391 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 4392 { 4393 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 4394 { 4395 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 4396 4397 /* Abort DMA Xfer if any */ 4398 if (hi2c->hdmatx != NULL) 4399 { 4400 /* Set the I2C DMA Abort callback : 4401 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 4402 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 4403 4404 /* Abort DMA TX */ 4405 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 4406 { 4407 /* Call Directly XferAbortCallback function in case of error */ 4408 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 4409 } 4410 } 4411 } 4412 } 4413 else 4414 { 4415 /* Nothing to do */ 4416 } 4417 4418 /* Check if the I2C is already enabled */ 4419 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 4420 { 4421 /* Enable I2C peripheral */ 4422 __HAL_I2C_ENABLE(hi2c); 4423 } 4424 4425 /* Disable Pos */ 4426 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 4427 4428 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; 4429 hi2c->Mode = HAL_I2C_MODE_SLAVE; 4430 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 4431 4432 /* Prepare transfer parameters */ 4433 hi2c->pBuffPtr = pData; 4434 hi2c->XferCount = Size; 4435 hi2c->XferSize = hi2c->XferCount; 4436 hi2c->XferOptions = XferOptions; 4437 4438 if (hi2c->hdmatx != NULL) 4439 { 4440 /* Set the I2C DMA transfer complete callback */ 4441 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 4442 4443 /* Set the DMA error callback */ 4444 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 4445 4446 /* Set the unused DMA callbacks to NULL */ 4447 hi2c->hdmatx->XferHalfCpltCallback = NULL; 4448 hi2c->hdmatx->XferAbortCallback = NULL; 4449 4450 /* Enable the DMA channel */ 4451 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 4452 } 4453 else 4454 { 4455 /* Update I2C state */ 4456 hi2c->State = HAL_I2C_STATE_LISTEN; 4457 hi2c->Mode = HAL_I2C_MODE_NONE; 4458 4459 /* Update I2C error code */ 4460 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 4461 4462 /* Process Unlocked */ 4463 __HAL_UNLOCK(hi2c); 4464 4465 return HAL_ERROR; 4466 } 4467 4468 if (dmaxferstatus == HAL_OK) 4469 { 4470 /* Enable Address Acknowledge */ 4471 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4472 4473 /* Clear ADDR flag */ 4474 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 4475 4476 /* Process Unlocked */ 4477 __HAL_UNLOCK(hi2c); 4478 4479 /* Note : The I2C interrupts must be enabled after unlocking current process 4480 to avoid the risk of I2C interrupt handle execution before current 4481 process unlock */ 4482 /* Enable EVT and ERR interrupt */ 4483 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 4484 4485 /* Enable DMA Request */ 4486 hi2c->Instance->CR2 |= I2C_CR2_DMAEN; 4487 4488 return HAL_OK; 4489 } 4490 else 4491 { 4492 /* Update I2C state */ 4493 hi2c->State = HAL_I2C_STATE_READY; 4494 hi2c->Mode = HAL_I2C_MODE_NONE; 4495 4496 /* Update I2C error code */ 4497 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 4498 4499 /* Process Unlocked */ 4500 __HAL_UNLOCK(hi2c); 4501 4502 return HAL_ERROR; 4503 } 4504 } 4505 else 4506 { 4507 return HAL_BUSY; 4508 } 4509 } 4510 4511 /** 4512 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt 4513 * @note This interface allow to manage repeated start condition when a direction change during transfer 4514 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4515 * the configuration information for the specified I2C. 4516 * @param pData Pointer to data buffer 4517 * @param Size Amount of data to be sent 4518 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 4519 * @retval HAL status 4520 */ 4521 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 4522 { 4523 /* Check the parameters */ 4524 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 4525 4526 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 4527 { 4528 if ((pData == NULL) || (Size == 0U)) 4529 { 4530 return HAL_ERROR; 4531 } 4532 4533 /* Process Locked */ 4534 __HAL_LOCK(hi2c); 4535 4536 /* Check if the I2C is already enabled */ 4537 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 4538 { 4539 /* Enable I2C peripheral */ 4540 __HAL_I2C_ENABLE(hi2c); 4541 } 4542 4543 /* Disable Pos */ 4544 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 4545 4546 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; 4547 hi2c->Mode = HAL_I2C_MODE_SLAVE; 4548 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 4549 4550 /* Prepare transfer parameters */ 4551 hi2c->pBuffPtr = pData; 4552 hi2c->XferCount = Size; 4553 hi2c->XferSize = hi2c->XferCount; 4554 hi2c->XferOptions = XferOptions; 4555 4556 /* Clear ADDR flag */ 4557 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 4558 4559 /* Process Unlocked */ 4560 __HAL_UNLOCK(hi2c); 4561 4562 /* Note : The I2C interrupts must be enabled after unlocking current process 4563 to avoid the risk of I2C interrupt handle execution before current 4564 process unlock */ 4565 4566 /* Enable EVT, BUF and ERR interrupt */ 4567 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 4568 4569 return HAL_OK; 4570 } 4571 else 4572 { 4573 return HAL_BUSY; 4574 } 4575 } 4576 4577 /** 4578 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA 4579 * @note This interface allow to manage repeated start condition when a direction change during transfer 4580 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4581 * the configuration information for the specified I2C. 4582 * @param pData Pointer to data buffer 4583 * @param Size Amount of data to be sent 4584 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 4585 * @retval HAL status 4586 */ 4587 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 4588 { 4589 HAL_StatusTypeDef dmaxferstatus; 4590 4591 /* Check the parameters */ 4592 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 4593 4594 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 4595 { 4596 if ((pData == NULL) || (Size == 0U)) 4597 { 4598 return HAL_ERROR; 4599 } 4600 4601 /* Process Locked */ 4602 __HAL_LOCK(hi2c); 4603 4604 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ 4605 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 4606 4607 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ 4608 /* and then toggle the HAL slave RX state to TX state */ 4609 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 4610 { 4611 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 4612 { 4613 /* Abort DMA Xfer if any */ 4614 if (hi2c->hdmarx != NULL) 4615 { 4616 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 4617 4618 /* Set the I2C DMA Abort callback : 4619 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 4620 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 4621 4622 /* Abort DMA RX */ 4623 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 4624 { 4625 /* Call Directly XferAbortCallback function in case of error */ 4626 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 4627 } 4628 } 4629 } 4630 } 4631 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 4632 { 4633 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 4634 { 4635 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 4636 4637 /* Abort DMA Xfer if any */ 4638 if (hi2c->hdmatx != NULL) 4639 { 4640 /* Set the I2C DMA Abort callback : 4641 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 4642 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 4643 4644 /* Abort DMA TX */ 4645 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 4646 { 4647 /* Call Directly XferAbortCallback function in case of error */ 4648 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 4649 } 4650 } 4651 } 4652 } 4653 else 4654 { 4655 /* Nothing to do */ 4656 } 4657 4658 /* Check if the I2C is already enabled */ 4659 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 4660 { 4661 /* Enable I2C peripheral */ 4662 __HAL_I2C_ENABLE(hi2c); 4663 } 4664 4665 /* Disable Pos */ 4666 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 4667 4668 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; 4669 hi2c->Mode = HAL_I2C_MODE_SLAVE; 4670 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 4671 4672 /* Prepare transfer parameters */ 4673 hi2c->pBuffPtr = pData; 4674 hi2c->XferCount = Size; 4675 hi2c->XferSize = hi2c->XferCount; 4676 hi2c->XferOptions = XferOptions; 4677 4678 if (hi2c->hdmarx != NULL) 4679 { 4680 /* Set the I2C DMA transfer complete callback */ 4681 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 4682 4683 /* Set the DMA error callback */ 4684 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 4685 4686 /* Set the unused DMA callbacks to NULL */ 4687 hi2c->hdmarx->XferHalfCpltCallback = NULL; 4688 hi2c->hdmarx->XferAbortCallback = NULL; 4689 4690 /* Enable the DMA channel */ 4691 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 4692 } 4693 else 4694 { 4695 /* Update I2C state */ 4696 hi2c->State = HAL_I2C_STATE_LISTEN; 4697 hi2c->Mode = HAL_I2C_MODE_NONE; 4698 4699 /* Update I2C error code */ 4700 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 4701 4702 /* Process Unlocked */ 4703 __HAL_UNLOCK(hi2c); 4704 4705 return HAL_ERROR; 4706 } 4707 4708 if (dmaxferstatus == HAL_OK) 4709 { 4710 /* Enable Address Acknowledge */ 4711 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4712 4713 /* Clear ADDR flag */ 4714 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 4715 4716 /* Process Unlocked */ 4717 __HAL_UNLOCK(hi2c); 4718 4719 /* Enable DMA Request */ 4720 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 4721 4722 /* Note : The I2C interrupts must be enabled after unlocking current process 4723 to avoid the risk of I2C interrupt handle execution before current 4724 process unlock */ 4725 /* Enable EVT and ERR interrupt */ 4726 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 4727 4728 return HAL_OK; 4729 } 4730 else 4731 { 4732 /* Update I2C state */ 4733 hi2c->State = HAL_I2C_STATE_READY; 4734 hi2c->Mode = HAL_I2C_MODE_NONE; 4735 4736 /* Update I2C error code */ 4737 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 4738 4739 /* Process Unlocked */ 4740 __HAL_UNLOCK(hi2c); 4741 4742 return HAL_ERROR; 4743 } 4744 } 4745 else 4746 { 4747 return HAL_BUSY; 4748 } 4749 } 4750 4751 /** 4752 * @brief Enable the Address listen mode with Interrupt. 4753 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4754 * the configuration information for the specified I2C. 4755 * @retval HAL status 4756 */ 4757 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) 4758 { 4759 if (hi2c->State == HAL_I2C_STATE_READY) 4760 { 4761 hi2c->State = HAL_I2C_STATE_LISTEN; 4762 4763 /* Check if the I2C is already enabled */ 4764 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 4765 { 4766 /* Enable I2C peripheral */ 4767 __HAL_I2C_ENABLE(hi2c); 4768 } 4769 4770 /* Enable Address Acknowledge */ 4771 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4772 4773 /* Enable EVT and ERR interrupt */ 4774 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 4775 4776 return HAL_OK; 4777 } 4778 else 4779 { 4780 return HAL_BUSY; 4781 } 4782 } 4783 4784 /** 4785 * @brief Disable the Address listen mode with Interrupt. 4786 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4787 * the configuration information for the specified I2C. 4788 * @retval HAL status 4789 */ 4790 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) 4791 { 4792 /* Declaration of tmp to prevent undefined behavior of volatile usage */ 4793 uint32_t tmp; 4794 4795 /* Disable Address listen mode only if a transfer is not ongoing */ 4796 if (hi2c->State == HAL_I2C_STATE_LISTEN) 4797 { 4798 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; 4799 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); 4800 hi2c->State = HAL_I2C_STATE_READY; 4801 hi2c->Mode = HAL_I2C_MODE_NONE; 4802 4803 /* Disable Address Acknowledge */ 4804 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4805 4806 /* Disable EVT and ERR interrupt */ 4807 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 4808 4809 return HAL_OK; 4810 } 4811 else 4812 { 4813 return HAL_BUSY; 4814 } 4815 } 4816 4817 /** 4818 * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. 4819 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4820 * the configuration information for the specified I2C. 4821 * @param DevAddress Target device address: The device 7 bits address value 4822 * in datasheet must be shifted to the left before calling the interface 4823 * @retval HAL status 4824 */ 4825 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) 4826 { 4827 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 4828 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 4829 4830 /* Prevent unused argument(s) compilation warning */ 4831 UNUSED(DevAddress); 4832 4833 /* Abort Master transfer during Receive or Transmit process */ 4834 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && ((CurrentMode == HAL_I2C_MODE_MASTER) || 4835 (CurrentMode == HAL_I2C_MODE_MEM))) 4836 { 4837 /* Process Locked */ 4838 __HAL_LOCK(hi2c); 4839 4840 hi2c->PreviousState = I2C_STATE_NONE; 4841 hi2c->State = HAL_I2C_STATE_ABORT; 4842 4843 /* Disable Acknowledge */ 4844 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 4845 4846 /* Generate Stop */ 4847 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 4848 4849 hi2c->XferCount = 0U; 4850 4851 /* Disable EVT, BUF and ERR interrupt */ 4852 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 4853 4854 /* Process Unlocked */ 4855 __HAL_UNLOCK(hi2c); 4856 4857 /* Call the corresponding callback to inform upper layer of End of Transfer */ 4858 I2C_ITError(hi2c); 4859 4860 return HAL_OK; 4861 } 4862 else 4863 { 4864 /* Wrong usage of abort function */ 4865 /* This function should be used only in case of abort monitored by master device */ 4866 /* Or periphal is not in busy state, mean there is no active sequence to be abort */ 4867 return HAL_ERROR; 4868 } 4869 } 4870 4871 /** 4872 * @} 4873 */ 4874 4875 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 4876 * @{ 4877 */ 4878 4879 /** 4880 * @brief This function handles I2C event interrupt request. 4881 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 4882 * the configuration information for the specified I2C. 4883 * @retval None 4884 */ 4885 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) 4886 { 4887 uint32_t sr1itflags; 4888 uint32_t sr2itflags = 0U; 4889 uint32_t itsources = READ_REG(hi2c->Instance->CR2); 4890 uint32_t CurrentXferOptions = hi2c->XferOptions; 4891 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 4892 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 4893 4894 /* Master or Memory mode selected */ 4895 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) 4896 { 4897 sr2itflags = READ_REG(hi2c->Instance->SR2); 4898 sr1itflags = READ_REG(hi2c->Instance->SR1); 4899 4900 /* Exit IRQ event until Start Bit detected in case of Other frame requested */ 4901 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) 4902 { 4903 return; 4904 } 4905 4906 /* SB Set ----------------------------------------------------------------*/ 4907 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 4908 { 4909 /* Convert OTHER_xxx XferOptions if any */ 4910 I2C_ConvertOtherXferOptions(hi2c); 4911 4912 I2C_Master_SB(hi2c); 4913 } 4914 /* ADD10 Set -------------------------------------------------------------*/ 4915 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 4916 { 4917 I2C_Master_ADD10(hi2c); 4918 } 4919 /* ADDR Set --------------------------------------------------------------*/ 4920 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 4921 { 4922 I2C_Master_ADDR(hi2c); 4923 } 4924 /* I2C in mode Transmitter -----------------------------------------------*/ 4925 else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) 4926 { 4927 /* Do not check buffer and BTF flag if a Xfer DMA is on going */ 4928 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) 4929 { 4930 /* TXE set and BTF reset -----------------------------------------------*/ 4931 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) 4932 { 4933 I2C_MasterTransmit_TXE(hi2c); 4934 } 4935 /* BTF set -------------------------------------------------------------*/ 4936 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 4937 { 4938 if (CurrentState == HAL_I2C_STATE_BUSY_TX) 4939 { 4940 I2C_MasterTransmit_BTF(hi2c); 4941 } 4942 else /* HAL_I2C_MODE_MEM */ 4943 { 4944 if (CurrentMode == HAL_I2C_MODE_MEM) 4945 { 4946 I2C_MemoryTransmit_TXE_BTF(hi2c); 4947 } 4948 } 4949 } 4950 else 4951 { 4952 /* Do nothing */ 4953 } 4954 } 4955 } 4956 /* I2C in mode Receiver --------------------------------------------------*/ 4957 else 4958 { 4959 /* Do not check buffer and BTF flag if a Xfer DMA is on going */ 4960 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) 4961 { 4962 /* RXNE set and BTF reset -----------------------------------------------*/ 4963 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) 4964 { 4965 I2C_MasterReceive_RXNE(hi2c); 4966 } 4967 /* BTF set -------------------------------------------------------------*/ 4968 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 4969 { 4970 I2C_MasterReceive_BTF(hi2c); 4971 } 4972 else 4973 { 4974 /* Do nothing */ 4975 } 4976 } 4977 } 4978 } 4979 /* Slave mode selected */ 4980 else 4981 { 4982 /* If an error is detected, read only SR1 register to prevent */ 4983 /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ 4984 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 4985 { 4986 sr1itflags = READ_REG(hi2c->Instance->SR1); 4987 } 4988 else 4989 { 4990 sr2itflags = READ_REG(hi2c->Instance->SR2); 4991 sr1itflags = READ_REG(hi2c->Instance->SR1); 4992 } 4993 4994 /* ADDR set --------------------------------------------------------------*/ 4995 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 4996 { 4997 /* Now time to read SR2, this will clear ADDR flag automatically */ 4998 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 4999 { 5000 sr2itflags = READ_REG(hi2c->Instance->SR2); 5001 } 5002 I2C_Slave_ADDR(hi2c, sr2itflags); 5003 } 5004 /* STOPF set --------------------------------------------------------------*/ 5005 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 5006 { 5007 I2C_Slave_STOPF(hi2c); 5008 } 5009 /* I2C in mode Transmitter -----------------------------------------------*/ 5010 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) 5011 { 5012 /* TXE set and BTF reset -----------------------------------------------*/ 5013 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) 5014 { 5015 I2C_SlaveTransmit_TXE(hi2c); 5016 } 5017 /* BTF set -------------------------------------------------------------*/ 5018 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 5019 { 5020 I2C_SlaveTransmit_BTF(hi2c); 5021 } 5022 else 5023 { 5024 /* Do nothing */ 5025 } 5026 } 5027 /* I2C in mode Receiver --------------------------------------------------*/ 5028 else 5029 { 5030 /* RXNE set and BTF reset ----------------------------------------------*/ 5031 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) 5032 { 5033 I2C_SlaveReceive_RXNE(hi2c); 5034 } 5035 /* BTF set -------------------------------------------------------------*/ 5036 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 5037 { 5038 I2C_SlaveReceive_BTF(hi2c); 5039 } 5040 else 5041 { 5042 /* Do nothing */ 5043 } 5044 } 5045 } 5046 } 5047 5048 /** 5049 * @brief This function handles I2C error interrupt request. 5050 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5051 * the configuration information for the specified I2C. 5052 * @retval None 5053 */ 5054 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) 5055 { 5056 HAL_I2C_ModeTypeDef tmp1; 5057 uint32_t tmp2; 5058 HAL_I2C_StateTypeDef tmp3; 5059 uint32_t tmp4; 5060 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); 5061 uint32_t itsources = READ_REG(hi2c->Instance->CR2); 5062 uint32_t error = HAL_I2C_ERROR_NONE; 5063 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 5064 5065 /* I2C Bus error interrupt occurred ----------------------------------------*/ 5066 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) 5067 { 5068 error |= HAL_I2C_ERROR_BERR; 5069 5070 /* Clear BERR flag */ 5071 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 5072 5073 /* Workaround: Start cannot be generated after a misplaced Stop */ 5074 SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST); 5075 } 5076 5077 /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ 5078 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) 5079 { 5080 error |= HAL_I2C_ERROR_ARLO; 5081 5082 /* Clear ARLO flag */ 5083 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 5084 } 5085 5086 /* I2C Acknowledge failure error interrupt occurred ------------------------*/ 5087 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) 5088 { 5089 tmp1 = CurrentMode; 5090 tmp2 = hi2c->XferCount; 5091 tmp3 = hi2c->State; 5092 tmp4 = hi2c->PreviousState; 5093 if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ 5094 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ 5095 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) 5096 { 5097 I2C_Slave_AF(hi2c); 5098 } 5099 else 5100 { 5101 /* Clear AF flag */ 5102 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 5103 5104 error |= HAL_I2C_ERROR_AF; 5105 5106 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ 5107 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) 5108 { 5109 /* Generate Stop */ 5110 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 5111 } 5112 } 5113 } 5114 5115 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ 5116 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) 5117 { 5118 error |= HAL_I2C_ERROR_OVR; 5119 /* Clear OVR flag */ 5120 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 5121 } 5122 5123 /* Call the Error Callback in case of Error detected -----------------------*/ 5124 if (error != HAL_I2C_ERROR_NONE) 5125 { 5126 hi2c->ErrorCode |= error; 5127 I2C_ITError(hi2c); 5128 } 5129 } 5130 5131 /** 5132 * @brief Master Tx Transfer completed callback. 5133 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5134 * the configuration information for the specified I2C. 5135 * @retval None 5136 */ 5137 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) 5138 { 5139 /* Prevent unused argument(s) compilation warning */ 5140 UNUSED(hi2c); 5141 5142 /* NOTE : This function should not be modified, when the callback is needed, 5143 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file 5144 */ 5145 } 5146 5147 /** 5148 * @brief Master Rx Transfer completed callback. 5149 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5150 * the configuration information for the specified I2C. 5151 * @retval None 5152 */ 5153 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) 5154 { 5155 /* Prevent unused argument(s) compilation warning */ 5156 UNUSED(hi2c); 5157 5158 /* NOTE : This function should not be modified, when the callback is needed, 5159 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file 5160 */ 5161 } 5162 5163 /** @brief Slave Tx Transfer completed callback. 5164 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5165 * the configuration information for the specified I2C. 5166 * @retval None 5167 */ 5168 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) 5169 { 5170 /* Prevent unused argument(s) compilation warning */ 5171 UNUSED(hi2c); 5172 5173 /* NOTE : This function should not be modified, when the callback is needed, 5174 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file 5175 */ 5176 } 5177 5178 /** 5179 * @brief Slave Rx Transfer completed callback. 5180 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5181 * the configuration information for the specified I2C. 5182 * @retval None 5183 */ 5184 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) 5185 { 5186 /* Prevent unused argument(s) compilation warning */ 5187 UNUSED(hi2c); 5188 5189 /* NOTE : This function should not be modified, when the callback is needed, 5190 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file 5191 */ 5192 } 5193 5194 /** 5195 * @brief Slave Address Match callback. 5196 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5197 * the configuration information for the specified I2C. 5198 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition 5199 * @param AddrMatchCode Address Match Code 5200 * @retval None 5201 */ 5202 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) 5203 { 5204 /* Prevent unused argument(s) compilation warning */ 5205 UNUSED(hi2c); 5206 UNUSED(TransferDirection); 5207 UNUSED(AddrMatchCode); 5208 5209 /* NOTE : This function should not be modified, when the callback is needed, 5210 the HAL_I2C_AddrCallback() could be implemented in the user file 5211 */ 5212 } 5213 5214 /** 5215 * @brief Listen Complete callback. 5216 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5217 * the configuration information for the specified I2C. 5218 * @retval None 5219 */ 5220 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) 5221 { 5222 /* Prevent unused argument(s) compilation warning */ 5223 UNUSED(hi2c); 5224 5225 /* NOTE : This function should not be modified, when the callback is needed, 5226 the HAL_I2C_ListenCpltCallback() could be implemented in the user file 5227 */ 5228 } 5229 5230 /** 5231 * @brief Memory Tx Transfer completed callback. 5232 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5233 * the configuration information for the specified I2C. 5234 * @retval None 5235 */ 5236 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) 5237 { 5238 /* Prevent unused argument(s) compilation warning */ 5239 UNUSED(hi2c); 5240 5241 /* NOTE : This function should not be modified, when the callback is needed, 5242 the HAL_I2C_MemTxCpltCallback could be implemented in the user file 5243 */ 5244 } 5245 5246 /** 5247 * @brief Memory Rx Transfer completed callback. 5248 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5249 * the configuration information for the specified I2C. 5250 * @retval None 5251 */ 5252 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) 5253 { 5254 /* Prevent unused argument(s) compilation warning */ 5255 UNUSED(hi2c); 5256 5257 /* NOTE : This function should not be modified, when the callback is needed, 5258 the HAL_I2C_MemRxCpltCallback could be implemented in the user file 5259 */ 5260 } 5261 5262 /** 5263 * @brief I2C error callback. 5264 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5265 * the configuration information for the specified I2C. 5266 * @retval None 5267 */ 5268 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) 5269 { 5270 /* Prevent unused argument(s) compilation warning */ 5271 UNUSED(hi2c); 5272 5273 /* NOTE : This function should not be modified, when the callback is needed, 5274 the HAL_I2C_ErrorCallback could be implemented in the user file 5275 */ 5276 } 5277 5278 /** 5279 * @brief I2C abort callback. 5280 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5281 * the configuration information for the specified I2C. 5282 * @retval None 5283 */ 5284 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) 5285 { 5286 /* Prevent unused argument(s) compilation warning */ 5287 UNUSED(hi2c); 5288 5289 /* NOTE : This function should not be modified, when the callback is needed, 5290 the HAL_I2C_AbortCpltCallback could be implemented in the user file 5291 */ 5292 } 5293 5294 /** 5295 * @} 5296 */ 5297 5298 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions 5299 * @brief Peripheral State, Mode and Error functions 5300 * 5301 @verbatim 5302 =============================================================================== 5303 ##### Peripheral State, Mode and Error functions ##### 5304 =============================================================================== 5305 [..] 5306 This subsection permit to get in run-time the status of the peripheral 5307 and the data flow. 5308 5309 @endverbatim 5310 * @{ 5311 */ 5312 5313 /** 5314 * @brief Return the I2C handle state. 5315 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5316 * the configuration information for the specified I2C. 5317 * @retval HAL state 5318 */ 5319 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) 5320 { 5321 /* Return I2C handle state */ 5322 return hi2c->State; 5323 } 5324 5325 /** 5326 * @brief Returns the I2C Master, Slave, Memory or no mode. 5327 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5328 * the configuration information for I2C module 5329 * @retval HAL mode 5330 */ 5331 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) 5332 { 5333 return hi2c->Mode; 5334 } 5335 5336 /** 5337 * @brief Return the I2C error code. 5338 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5339 * the configuration information for the specified I2C. 5340 * @retval I2C Error Code 5341 */ 5342 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) 5343 { 5344 return hi2c->ErrorCode; 5345 } 5346 5347 /** 5348 * @} 5349 */ 5350 5351 /** 5352 * @} 5353 */ 5354 5355 /** @addtogroup I2C_Private_Functions 5356 * @{ 5357 */ 5358 5359 /** 5360 * @brief Handle TXE flag for Master 5361 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5362 * the configuration information for I2C module 5363 * @retval None 5364 */ 5365 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) 5366 { 5367 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 5368 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 5369 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 5370 uint32_t CurrentXferOptions = hi2c->XferOptions; 5371 5372 if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) 5373 { 5374 /* Call TxCpltCallback() directly if no stop mode is set */ 5375 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) 5376 { 5377 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 5378 5379 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 5380 hi2c->Mode = HAL_I2C_MODE_NONE; 5381 hi2c->State = HAL_I2C_STATE_READY; 5382 5383 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5384 hi2c->MasterTxCpltCallback(hi2c); 5385 #else 5386 HAL_I2C_MasterTxCpltCallback(hi2c); 5387 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5388 } 5389 else /* Generate Stop condition then Call TxCpltCallback() */ 5390 { 5391 /* Disable EVT, BUF and ERR interrupt */ 5392 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 5393 5394 /* Generate Stop */ 5395 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 5396 5397 hi2c->PreviousState = I2C_STATE_NONE; 5398 hi2c->State = HAL_I2C_STATE_READY; 5399 5400 if (hi2c->Mode == HAL_I2C_MODE_MEM) 5401 { 5402 hi2c->Mode = HAL_I2C_MODE_NONE; 5403 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5404 hi2c->MemTxCpltCallback(hi2c); 5405 #else 5406 HAL_I2C_MemTxCpltCallback(hi2c); 5407 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5408 } 5409 else 5410 { 5411 hi2c->Mode = HAL_I2C_MODE_NONE; 5412 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5413 hi2c->MasterTxCpltCallback(hi2c); 5414 #else 5415 HAL_I2C_MasterTxCpltCallback(hi2c); 5416 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5417 } 5418 } 5419 } 5420 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ 5421 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) 5422 { 5423 if (hi2c->XferCount == 0U) 5424 { 5425 /* Disable BUF interrupt */ 5426 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 5427 } 5428 else 5429 { 5430 if (hi2c->Mode == HAL_I2C_MODE_MEM) 5431 { 5432 I2C_MemoryTransmit_TXE_BTF(hi2c); 5433 } 5434 else 5435 { 5436 /* Write data to DR */ 5437 hi2c->Instance->DR = *hi2c->pBuffPtr; 5438 5439 /* Increment Buffer pointer */ 5440 hi2c->pBuffPtr++; 5441 5442 /* Update counter */ 5443 hi2c->XferCount--; 5444 } 5445 } 5446 } 5447 else 5448 { 5449 /* Do nothing */ 5450 } 5451 } 5452 5453 /** 5454 * @brief Handle BTF flag for Master transmitter 5455 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5456 * the configuration information for I2C module 5457 * @retval None 5458 */ 5459 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) 5460 { 5461 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 5462 uint32_t CurrentXferOptions = hi2c->XferOptions; 5463 5464 if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 5465 { 5466 if (hi2c->XferCount != 0U) 5467 { 5468 /* Write data to DR */ 5469 hi2c->Instance->DR = *hi2c->pBuffPtr; 5470 5471 /* Increment Buffer pointer */ 5472 hi2c->pBuffPtr++; 5473 5474 /* Update counter */ 5475 hi2c->XferCount--; 5476 } 5477 else 5478 { 5479 /* Call TxCpltCallback() directly if no stop mode is set */ 5480 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) 5481 { 5482 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 5483 5484 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 5485 hi2c->Mode = HAL_I2C_MODE_NONE; 5486 hi2c->State = HAL_I2C_STATE_READY; 5487 5488 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5489 hi2c->MasterTxCpltCallback(hi2c); 5490 #else 5491 HAL_I2C_MasterTxCpltCallback(hi2c); 5492 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5493 } 5494 else /* Generate Stop condition then Call TxCpltCallback() */ 5495 { 5496 /* Disable EVT, BUF and ERR interrupt */ 5497 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 5498 5499 /* Generate Stop */ 5500 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 5501 5502 hi2c->PreviousState = I2C_STATE_NONE; 5503 hi2c->State = HAL_I2C_STATE_READY; 5504 if (hi2c->Mode == HAL_I2C_MODE_MEM) 5505 { 5506 hi2c->Mode = HAL_I2C_MODE_NONE; 5507 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5508 hi2c->MemTxCpltCallback(hi2c); 5509 #else 5510 HAL_I2C_MemTxCpltCallback(hi2c); 5511 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5512 } 5513 else 5514 { 5515 hi2c->Mode = HAL_I2C_MODE_NONE; 5516 5517 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5518 hi2c->MasterTxCpltCallback(hi2c); 5519 #else 5520 HAL_I2C_MasterTxCpltCallback(hi2c); 5521 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5522 } 5523 } 5524 } 5525 } 5526 else 5527 { 5528 /* Do nothing */ 5529 } 5530 } 5531 5532 /** 5533 * @brief Handle TXE and BTF flag for Memory transmitter 5534 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5535 * the configuration information for I2C module 5536 * @retval None 5537 */ 5538 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) 5539 { 5540 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 5541 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 5542 5543 if (hi2c->EventCount == 0U) 5544 { 5545 /* If Memory address size is 8Bit */ 5546 if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) 5547 { 5548 /* Send Memory Address */ 5549 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); 5550 5551 hi2c->EventCount += 2U; 5552 } 5553 /* If Memory address size is 16Bit */ 5554 else 5555 { 5556 /* Send MSB of Memory Address */ 5557 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); 5558 5559 hi2c->EventCount++; 5560 } 5561 } 5562 else if (hi2c->EventCount == 1U) 5563 { 5564 /* Send LSB of Memory Address */ 5565 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); 5566 5567 hi2c->EventCount++; 5568 } 5569 else if (hi2c->EventCount == 2U) 5570 { 5571 if (CurrentState == HAL_I2C_STATE_BUSY_RX) 5572 { 5573 /* Generate Restart */ 5574 hi2c->Instance->CR1 |= I2C_CR1_START; 5575 5576 hi2c->EventCount++; 5577 } 5578 else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) 5579 { 5580 /* Write data to DR */ 5581 hi2c->Instance->DR = *hi2c->pBuffPtr; 5582 5583 /* Increment Buffer pointer */ 5584 hi2c->pBuffPtr++; 5585 5586 /* Update counter */ 5587 hi2c->XferCount--; 5588 } 5589 else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) 5590 { 5591 /* Generate Stop condition then Call TxCpltCallback() */ 5592 /* Disable EVT, BUF and ERR interrupt */ 5593 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 5594 5595 /* Generate Stop */ 5596 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 5597 5598 hi2c->PreviousState = I2C_STATE_NONE; 5599 hi2c->State = HAL_I2C_STATE_READY; 5600 hi2c->Mode = HAL_I2C_MODE_NONE; 5601 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5602 hi2c->MemTxCpltCallback(hi2c); 5603 #else 5604 HAL_I2C_MemTxCpltCallback(hi2c); 5605 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5606 } 5607 else 5608 { 5609 /* Do nothing */ 5610 } 5611 } 5612 else 5613 { 5614 /* Clear TXE and BTF flags */ 5615 I2C_Flush_DR(hi2c); 5616 } 5617 } 5618 5619 /** 5620 * @brief Handle RXNE flag for Master 5621 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5622 * the configuration information for I2C module 5623 * @retval None 5624 */ 5625 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) 5626 { 5627 if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 5628 { 5629 uint32_t tmp; 5630 uint32_t CurrentXferOptions; 5631 5632 CurrentXferOptions = hi2c->XferOptions; 5633 tmp = hi2c->XferCount; 5634 if (tmp > 3U) 5635 { 5636 /* Read data from DR */ 5637 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 5638 5639 /* Increment Buffer pointer */ 5640 hi2c->pBuffPtr++; 5641 5642 /* Update counter */ 5643 hi2c->XferCount--; 5644 5645 if (hi2c->XferCount == (uint16_t)3) 5646 { 5647 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes 5648 on BTF subroutine */ 5649 /* Disable BUF interrupt */ 5650 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 5651 } 5652 } 5653 else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) 5654 { 5655 if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) 5656 { 5657 /* Disable Acknowledge */ 5658 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 5659 5660 /* Disable EVT, BUF and ERR interrupt */ 5661 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 5662 5663 /* Read data from DR */ 5664 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 5665 5666 /* Increment Buffer pointer */ 5667 hi2c->pBuffPtr++; 5668 5669 /* Update counter */ 5670 hi2c->XferCount--; 5671 5672 hi2c->State = HAL_I2C_STATE_READY; 5673 5674 if (hi2c->Mode == HAL_I2C_MODE_MEM) 5675 { 5676 hi2c->Mode = HAL_I2C_MODE_NONE; 5677 hi2c->PreviousState = I2C_STATE_NONE; 5678 5679 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5680 hi2c->MemRxCpltCallback(hi2c); 5681 #else 5682 HAL_I2C_MemRxCpltCallback(hi2c); 5683 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5684 } 5685 else 5686 { 5687 hi2c->Mode = HAL_I2C_MODE_NONE; 5688 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) 5689 { 5690 hi2c->PreviousState = I2C_STATE_NONE; 5691 } 5692 else 5693 { 5694 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 5695 } 5696 5697 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5698 hi2c->MasterRxCpltCallback(hi2c); 5699 #else 5700 HAL_I2C_MasterRxCpltCallback(hi2c); 5701 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5702 } 5703 } 5704 else 5705 { 5706 /* Disable EVT, BUF and ERR interrupt */ 5707 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 5708 5709 /* Read data from DR */ 5710 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 5711 5712 /* Increment Buffer pointer */ 5713 hi2c->pBuffPtr++; 5714 5715 /* Update counter */ 5716 hi2c->XferCount--; 5717 5718 hi2c->State = HAL_I2C_STATE_READY; 5719 hi2c->Mode = HAL_I2C_MODE_NONE; 5720 5721 /* Call user error callback */ 5722 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5723 hi2c->ErrorCallback(hi2c); 5724 #else 5725 HAL_I2C_ErrorCallback(hi2c); 5726 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5727 } 5728 } 5729 else 5730 { 5731 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes 5732 on BTF subroutine if there is a reception delay between N-1 and N byte */ 5733 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 5734 } 5735 } 5736 } 5737 5738 /** 5739 * @brief Handle BTF flag for Master receiver 5740 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5741 * the configuration information for I2C module 5742 * @retval None 5743 */ 5744 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) 5745 { 5746 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 5747 uint32_t CurrentXferOptions = hi2c->XferOptions; 5748 5749 if (hi2c->XferCount == 4U) 5750 { 5751 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes 5752 on BTF subroutine if there is a reception delay between N-1 and N byte */ 5753 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 5754 5755 /* Read data from DR */ 5756 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 5757 5758 /* Increment Buffer pointer */ 5759 hi2c->pBuffPtr++; 5760 5761 /* Update counter */ 5762 hi2c->XferCount--; 5763 } 5764 else if (hi2c->XferCount == 3U) 5765 { 5766 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes 5767 on BTF subroutine if there is a reception delay between N-1 and N byte */ 5768 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 5769 5770 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) 5771 { 5772 /* Disable Acknowledge */ 5773 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 5774 } 5775 5776 /* Read data from DR */ 5777 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 5778 5779 /* Increment Buffer pointer */ 5780 hi2c->pBuffPtr++; 5781 5782 /* Update counter */ 5783 hi2c->XferCount--; 5784 } 5785 else if (hi2c->XferCount == 2U) 5786 { 5787 /* Prepare next transfer or stop current transfer */ 5788 if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) 5789 { 5790 /* Disable Acknowledge */ 5791 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 5792 } 5793 else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) 5794 { 5795 /* Enable Acknowledge */ 5796 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 5797 } 5798 else 5799 { 5800 /* Generate Stop */ 5801 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 5802 } 5803 5804 /* Read data from DR */ 5805 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 5806 5807 /* Increment Buffer pointer */ 5808 hi2c->pBuffPtr++; 5809 5810 /* Update counter */ 5811 hi2c->XferCount--; 5812 5813 /* Read data from DR */ 5814 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 5815 5816 /* Increment Buffer pointer */ 5817 hi2c->pBuffPtr++; 5818 5819 /* Update counter */ 5820 hi2c->XferCount--; 5821 5822 /* Disable EVT and ERR interrupt */ 5823 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 5824 5825 hi2c->State = HAL_I2C_STATE_READY; 5826 if (hi2c->Mode == HAL_I2C_MODE_MEM) 5827 { 5828 hi2c->Mode = HAL_I2C_MODE_NONE; 5829 hi2c->PreviousState = I2C_STATE_NONE; 5830 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5831 hi2c->MemRxCpltCallback(hi2c); 5832 #else 5833 HAL_I2C_MemRxCpltCallback(hi2c); 5834 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5835 } 5836 else 5837 { 5838 hi2c->Mode = HAL_I2C_MODE_NONE; 5839 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) 5840 { 5841 hi2c->PreviousState = I2C_STATE_NONE; 5842 } 5843 else 5844 { 5845 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 5846 } 5847 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 5848 hi2c->MasterRxCpltCallback(hi2c); 5849 #else 5850 HAL_I2C_MasterRxCpltCallback(hi2c); 5851 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 5852 } 5853 } 5854 else 5855 { 5856 /* Read data from DR */ 5857 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 5858 5859 /* Increment Buffer pointer */ 5860 hi2c->pBuffPtr++; 5861 5862 /* Update counter */ 5863 hi2c->XferCount--; 5864 } 5865 } 5866 5867 /** 5868 * @brief Handle SB flag for Master 5869 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5870 * the configuration information for I2C module 5871 * @retval None 5872 */ 5873 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) 5874 { 5875 if (hi2c->Mode == HAL_I2C_MODE_MEM) 5876 { 5877 if (hi2c->EventCount == 0U) 5878 { 5879 /* Send slave address */ 5880 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); 5881 } 5882 else 5883 { 5884 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); 5885 } 5886 } 5887 else 5888 { 5889 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 5890 { 5891 /* Send slave 7 Bits address */ 5892 if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 5893 { 5894 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); 5895 } 5896 else 5897 { 5898 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); 5899 } 5900 5901 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) 5902 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) 5903 { 5904 /* Enable DMA Request */ 5905 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 5906 } 5907 } 5908 else 5909 { 5910 if (hi2c->EventCount == 0U) 5911 { 5912 /* Send header of slave address */ 5913 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); 5914 } 5915 else if (hi2c->EventCount == 1U) 5916 { 5917 /* Send header of slave address */ 5918 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); 5919 } 5920 else 5921 { 5922 /* Do nothing */ 5923 } 5924 } 5925 } 5926 } 5927 5928 /** 5929 * @brief Handle ADD10 flag for Master 5930 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5931 * the configuration information for I2C module 5932 * @retval None 5933 */ 5934 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) 5935 { 5936 /* Send slave address */ 5937 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); 5938 5939 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) 5940 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) 5941 { 5942 /* Enable DMA Request */ 5943 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 5944 } 5945 } 5946 5947 /** 5948 * @brief Handle ADDR flag for Master 5949 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 5950 * the configuration information for I2C module 5951 * @retval None 5952 */ 5953 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) 5954 { 5955 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 5956 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 5957 uint32_t CurrentXferOptions = hi2c->XferOptions; 5958 uint32_t Prev_State = hi2c->PreviousState; 5959 5960 if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 5961 { 5962 if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) 5963 { 5964 /* Clear ADDR flag */ 5965 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 5966 } 5967 else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) 5968 { 5969 /* Clear ADDR flag */ 5970 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 5971 5972 /* Generate Restart */ 5973 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 5974 5975 hi2c->EventCount++; 5976 } 5977 else 5978 { 5979 if (hi2c->XferCount == 0U) 5980 { 5981 /* Clear ADDR flag */ 5982 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 5983 5984 /* Generate Stop */ 5985 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 5986 } 5987 else if (hi2c->XferCount == 1U) 5988 { 5989 if (CurrentXferOptions == I2C_NO_OPTION_FRAME) 5990 { 5991 /* Disable Acknowledge */ 5992 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 5993 5994 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 5995 { 5996 /* Disable Acknowledge */ 5997 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 5998 5999 /* Clear ADDR flag */ 6000 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6001 } 6002 else 6003 { 6004 /* Clear ADDR flag */ 6005 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6006 6007 /* Generate Stop */ 6008 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 6009 } 6010 } 6011 /* Prepare next transfer or stop current transfer */ 6012 else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ 6013 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) 6014 { 6015 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) 6016 { 6017 /* Disable Acknowledge */ 6018 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6019 } 6020 else 6021 { 6022 /* Enable Acknowledge */ 6023 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6024 } 6025 6026 /* Clear ADDR flag */ 6027 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6028 } 6029 else 6030 { 6031 /* Disable Acknowledge */ 6032 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6033 6034 /* Clear ADDR flag */ 6035 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6036 6037 /* Generate Stop */ 6038 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 6039 } 6040 } 6041 else if (hi2c->XferCount == 2U) 6042 { 6043 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) 6044 { 6045 /* Enable Pos */ 6046 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 6047 6048 /* Clear ADDR flag */ 6049 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6050 6051 /* Disable Acknowledge */ 6052 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6053 } 6054 else 6055 { 6056 /* Enable Acknowledge */ 6057 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6058 6059 /* Clear ADDR flag */ 6060 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6061 } 6062 6063 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) 6064 { 6065 /* Enable Last DMA bit */ 6066 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 6067 } 6068 } 6069 else 6070 { 6071 /* Enable Acknowledge */ 6072 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6073 6074 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) 6075 { 6076 /* Enable Last DMA bit */ 6077 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 6078 } 6079 6080 /* Clear ADDR flag */ 6081 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6082 } 6083 6084 /* Reset Event counter */ 6085 hi2c->EventCount = 0U; 6086 } 6087 } 6088 else 6089 { 6090 /* Clear ADDR flag */ 6091 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6092 } 6093 } 6094 6095 /** 6096 * @brief Handle TXE flag for Slave 6097 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6098 * the configuration information for I2C module 6099 * @retval None 6100 */ 6101 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) 6102 { 6103 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 6104 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 6105 6106 if (hi2c->XferCount != 0U) 6107 { 6108 /* Write data to DR */ 6109 hi2c->Instance->DR = *hi2c->pBuffPtr; 6110 6111 /* Increment Buffer pointer */ 6112 hi2c->pBuffPtr++; 6113 6114 /* Update counter */ 6115 hi2c->XferCount--; 6116 6117 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) 6118 { 6119 /* Last Byte is received, disable Interrupt */ 6120 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 6121 6122 /* Set state at HAL_I2C_STATE_LISTEN */ 6123 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 6124 hi2c->State = HAL_I2C_STATE_LISTEN; 6125 6126 /* Call the corresponding callback to inform upper layer of End of Transfer */ 6127 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6128 hi2c->SlaveTxCpltCallback(hi2c); 6129 #else 6130 HAL_I2C_SlaveTxCpltCallback(hi2c); 6131 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6132 } 6133 } 6134 } 6135 6136 /** 6137 * @brief Handle BTF flag for Slave transmitter 6138 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6139 * the configuration information for I2C module 6140 * @retval None 6141 */ 6142 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) 6143 { 6144 if (hi2c->XferCount != 0U) 6145 { 6146 /* Write data to DR */ 6147 hi2c->Instance->DR = *hi2c->pBuffPtr; 6148 6149 /* Increment Buffer pointer */ 6150 hi2c->pBuffPtr++; 6151 6152 /* Update counter */ 6153 hi2c->XferCount--; 6154 } 6155 } 6156 6157 /** 6158 * @brief Handle RXNE flag for Slave 6159 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6160 * the configuration information for I2C module 6161 * @retval None 6162 */ 6163 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) 6164 { 6165 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 6166 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 6167 6168 if (hi2c->XferCount != 0U) 6169 { 6170 /* Read data from DR */ 6171 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 6172 6173 /* Increment Buffer pointer */ 6174 hi2c->pBuffPtr++; 6175 6176 /* Update counter */ 6177 hi2c->XferCount--; 6178 6179 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) 6180 { 6181 /* Last Byte is received, disable Interrupt */ 6182 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 6183 6184 /* Set state at HAL_I2C_STATE_LISTEN */ 6185 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 6186 hi2c->State = HAL_I2C_STATE_LISTEN; 6187 6188 /* Call the corresponding callback to inform upper layer of End of Transfer */ 6189 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6190 hi2c->SlaveRxCpltCallback(hi2c); 6191 #else 6192 HAL_I2C_SlaveRxCpltCallback(hi2c); 6193 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6194 } 6195 } 6196 } 6197 6198 /** 6199 * @brief Handle BTF flag for Slave receiver 6200 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6201 * the configuration information for I2C module 6202 * @retval None 6203 */ 6204 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) 6205 { 6206 if (hi2c->XferCount != 0U) 6207 { 6208 /* Read data from DR */ 6209 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 6210 6211 /* Increment Buffer pointer */ 6212 hi2c->pBuffPtr++; 6213 6214 /* Update counter */ 6215 hi2c->XferCount--; 6216 } 6217 } 6218 6219 /** 6220 * @brief Handle ADD flag for Slave 6221 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6222 * the configuration information for I2C module 6223 * @param IT2Flags Interrupt2 flags to handle. 6224 * @retval None 6225 */ 6226 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) 6227 { 6228 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; 6229 uint16_t SlaveAddrCode; 6230 6231 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 6232 { 6233 /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ 6234 __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); 6235 6236 /* Transfer Direction requested by Master */ 6237 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) 6238 { 6239 TransferDirection = I2C_DIRECTION_TRANSMIT; 6240 } 6241 6242 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) 6243 { 6244 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; 6245 } 6246 else 6247 { 6248 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; 6249 } 6250 6251 /* Process Unlocked */ 6252 __HAL_UNLOCK(hi2c); 6253 6254 /* Call Slave Addr callback */ 6255 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6256 hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); 6257 #else 6258 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); 6259 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6260 } 6261 else 6262 { 6263 /* Clear ADDR flag */ 6264 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6265 6266 /* Process Unlocked */ 6267 __HAL_UNLOCK(hi2c); 6268 } 6269 } 6270 6271 /** 6272 * @brief Handle STOPF flag for Slave 6273 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6274 * the configuration information for I2C module 6275 * @retval None 6276 */ 6277 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) 6278 { 6279 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 6280 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 6281 6282 /* Disable EVT, BUF and ERR interrupt */ 6283 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 6284 6285 /* Clear STOPF flag */ 6286 __HAL_I2C_CLEAR_STOPFLAG(hi2c); 6287 6288 /* Disable Acknowledge */ 6289 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6290 6291 /* If a DMA is ongoing, Update handle size context */ 6292 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 6293 { 6294 if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) 6295 { 6296 hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx)); 6297 6298 if (hi2c->XferCount != 0U) 6299 { 6300 /* Set ErrorCode corresponding to a Non-Acknowledge */ 6301 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 6302 } 6303 6304 /* Disable, stop the current DMA */ 6305 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 6306 6307 /* Abort DMA Xfer if any */ 6308 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 6309 { 6310 /* Set the I2C DMA Abort callback : 6311 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 6312 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 6313 6314 /* Abort DMA RX */ 6315 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 6316 { 6317 /* Call Directly XferAbortCallback function in case of error */ 6318 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 6319 } 6320 } 6321 } 6322 else 6323 { 6324 hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx)); 6325 6326 if (hi2c->XferCount != 0U) 6327 { 6328 /* Set ErrorCode corresponding to a Non-Acknowledge */ 6329 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 6330 } 6331 6332 /* Disable, stop the current DMA */ 6333 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 6334 6335 /* Abort DMA Xfer if any */ 6336 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 6337 { 6338 /* Set the I2C DMA Abort callback : 6339 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 6340 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 6341 6342 /* Abort DMA TX */ 6343 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 6344 { 6345 /* Call Directly XferAbortCallback function in case of error */ 6346 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 6347 } 6348 } 6349 } 6350 } 6351 6352 /* All data are not transferred, so set error code accordingly */ 6353 if (hi2c->XferCount != 0U) 6354 { 6355 /* Store Last receive data if any */ 6356 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 6357 { 6358 /* Read data from DR */ 6359 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 6360 6361 /* Increment Buffer pointer */ 6362 hi2c->pBuffPtr++; 6363 6364 /* Update counter */ 6365 hi2c->XferCount--; 6366 } 6367 6368 /* Store Last receive data if any */ 6369 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) 6370 { 6371 /* Read data from DR */ 6372 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 6373 6374 /* Increment Buffer pointer */ 6375 hi2c->pBuffPtr++; 6376 6377 /* Update counter */ 6378 hi2c->XferCount--; 6379 } 6380 6381 if (hi2c->XferCount != 0U) 6382 { 6383 /* Set ErrorCode corresponding to a Non-Acknowledge */ 6384 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 6385 } 6386 } 6387 6388 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 6389 { 6390 /* Call the corresponding callback to inform upper layer of End of Transfer */ 6391 I2C_ITError(hi2c); 6392 } 6393 else 6394 { 6395 if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) 6396 { 6397 /* Set state at HAL_I2C_STATE_LISTEN */ 6398 hi2c->PreviousState = I2C_STATE_NONE; 6399 hi2c->State = HAL_I2C_STATE_LISTEN; 6400 6401 /* Call the corresponding callback to inform upper layer of End of Transfer */ 6402 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6403 hi2c->SlaveRxCpltCallback(hi2c); 6404 #else 6405 HAL_I2C_SlaveRxCpltCallback(hi2c); 6406 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6407 } 6408 6409 if (hi2c->State == HAL_I2C_STATE_LISTEN) 6410 { 6411 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 6412 hi2c->PreviousState = I2C_STATE_NONE; 6413 hi2c->State = HAL_I2C_STATE_READY; 6414 hi2c->Mode = HAL_I2C_MODE_NONE; 6415 6416 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ 6417 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6418 hi2c->ListenCpltCallback(hi2c); 6419 #else 6420 HAL_I2C_ListenCpltCallback(hi2c); 6421 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6422 } 6423 else 6424 { 6425 if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) 6426 { 6427 hi2c->PreviousState = I2C_STATE_NONE; 6428 hi2c->State = HAL_I2C_STATE_READY; 6429 hi2c->Mode = HAL_I2C_MODE_NONE; 6430 6431 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6432 hi2c->SlaveRxCpltCallback(hi2c); 6433 #else 6434 HAL_I2C_SlaveRxCpltCallback(hi2c); 6435 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6436 } 6437 } 6438 } 6439 } 6440 6441 /** 6442 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6443 * the configuration information for I2C module 6444 * @retval None 6445 */ 6446 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) 6447 { 6448 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 6449 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 6450 uint32_t CurrentXferOptions = hi2c->XferOptions; 6451 6452 if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ 6453 (CurrentState == HAL_I2C_STATE_LISTEN)) 6454 { 6455 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 6456 6457 /* Disable EVT, BUF and ERR interrupt */ 6458 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 6459 6460 /* Clear AF flag */ 6461 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 6462 6463 /* Disable Acknowledge */ 6464 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6465 6466 hi2c->PreviousState = I2C_STATE_NONE; 6467 hi2c->State = HAL_I2C_STATE_READY; 6468 hi2c->Mode = HAL_I2C_MODE_NONE; 6469 6470 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ 6471 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6472 hi2c->ListenCpltCallback(hi2c); 6473 #else 6474 HAL_I2C_ListenCpltCallback(hi2c); 6475 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6476 } 6477 else if (CurrentState == HAL_I2C_STATE_BUSY_TX) 6478 { 6479 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 6480 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 6481 hi2c->State = HAL_I2C_STATE_READY; 6482 hi2c->Mode = HAL_I2C_MODE_NONE; 6483 6484 /* Disable EVT, BUF and ERR interrupt */ 6485 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 6486 6487 /* Clear AF flag */ 6488 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 6489 6490 /* Disable Acknowledge */ 6491 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6492 6493 /* Clear TXE flag */ 6494 I2C_Flush_DR(hi2c); 6495 6496 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6497 hi2c->SlaveTxCpltCallback(hi2c); 6498 #else 6499 HAL_I2C_SlaveTxCpltCallback(hi2c); 6500 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6501 } 6502 else 6503 { 6504 /* Clear AF flag only */ 6505 /* State Listen, but XferOptions == FIRST or NEXT */ 6506 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 6507 } 6508 } 6509 6510 /** 6511 * @brief I2C interrupts error process 6512 * @param hi2c I2C handle. 6513 * @retval None 6514 */ 6515 static void I2C_ITError(I2C_HandleTypeDef *hi2c) 6516 { 6517 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 6518 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 6519 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 6520 uint32_t CurrentError; 6521 6522 if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) 6523 { 6524 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ 6525 hi2c->Instance->CR1 &= ~I2C_CR1_POS; 6526 } 6527 6528 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 6529 { 6530 /* keep HAL_I2C_STATE_LISTEN */ 6531 hi2c->PreviousState = I2C_STATE_NONE; 6532 hi2c->State = HAL_I2C_STATE_LISTEN; 6533 } 6534 else 6535 { 6536 /* If state is an abort treatment on going, don't change state */ 6537 /* This change will be do later */ 6538 if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) 6539 { 6540 hi2c->State = HAL_I2C_STATE_READY; 6541 hi2c->Mode = HAL_I2C_MODE_NONE; 6542 } 6543 hi2c->PreviousState = I2C_STATE_NONE; 6544 } 6545 6546 /* Abort DMA transfer */ 6547 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 6548 { 6549 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; 6550 6551 if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) 6552 { 6553 /* Set the DMA Abort callback : 6554 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 6555 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 6556 6557 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 6558 { 6559 /* Disable I2C peripheral to prevent dummy data in buffer */ 6560 __HAL_I2C_DISABLE(hi2c); 6561 6562 hi2c->State = HAL_I2C_STATE_READY; 6563 6564 /* Call Directly XferAbortCallback function in case of error */ 6565 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 6566 } 6567 } 6568 else 6569 { 6570 /* Set the DMA Abort callback : 6571 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 6572 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 6573 6574 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 6575 { 6576 /* Store Last receive data if any */ 6577 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) 6578 { 6579 /* Read data from DR */ 6580 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 6581 6582 /* Increment Buffer pointer */ 6583 hi2c->pBuffPtr++; 6584 } 6585 6586 /* Disable I2C peripheral to prevent dummy data in buffer */ 6587 __HAL_I2C_DISABLE(hi2c); 6588 6589 hi2c->State = HAL_I2C_STATE_READY; 6590 6591 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ 6592 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 6593 } 6594 } 6595 } 6596 else if (hi2c->State == HAL_I2C_STATE_ABORT) 6597 { 6598 hi2c->State = HAL_I2C_STATE_READY; 6599 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 6600 6601 /* Store Last receive data if any */ 6602 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) 6603 { 6604 /* Read data from DR */ 6605 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 6606 6607 /* Increment Buffer pointer */ 6608 hi2c->pBuffPtr++; 6609 } 6610 6611 /* Disable I2C peripheral to prevent dummy data in buffer */ 6612 __HAL_I2C_DISABLE(hi2c); 6613 6614 /* Call the corresponding callback to inform upper layer of End of Transfer */ 6615 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6616 hi2c->AbortCpltCallback(hi2c); 6617 #else 6618 HAL_I2C_AbortCpltCallback(hi2c); 6619 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6620 } 6621 else 6622 { 6623 /* Store Last receive data if any */ 6624 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) 6625 { 6626 /* Read data from DR */ 6627 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 6628 6629 /* Increment Buffer pointer */ 6630 hi2c->pBuffPtr++; 6631 } 6632 6633 /* Call user error callback */ 6634 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6635 hi2c->ErrorCallback(hi2c); 6636 #else 6637 HAL_I2C_ErrorCallback(hi2c); 6638 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6639 } 6640 6641 /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ 6642 CurrentError = hi2c->ErrorCode; 6643 6644 if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ 6645 ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ 6646 ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ 6647 ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) 6648 { 6649 /* Disable EVT, BUF and ERR interrupt */ 6650 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 6651 } 6652 6653 /* So may inform upper layer that listen phase is stopped */ 6654 /* during NACK error treatment */ 6655 CurrentState = hi2c->State; 6656 if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) 6657 { 6658 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 6659 hi2c->PreviousState = I2C_STATE_NONE; 6660 hi2c->State = HAL_I2C_STATE_READY; 6661 hi2c->Mode = HAL_I2C_MODE_NONE; 6662 6663 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ 6664 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 6665 hi2c->ListenCpltCallback(hi2c); 6666 #else 6667 HAL_I2C_ListenCpltCallback(hi2c); 6668 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 6669 } 6670 } 6671 6672 /** 6673 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6674 * the configuration information for I2C module 6675 * @param DevAddress Target device address: The device 7 bits address value 6676 * in datasheet must be shifted to the left before calling the interface 6677 * @param Timeout Timeout duration 6678 * @param Tickstart Tick start value 6679 * @retval HAL status 6680 */ 6681 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) 6682 { 6683 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 6684 uint32_t CurrentXferOptions = hi2c->XferOptions; 6685 6686 /* Generate Start condition if first transfer */ 6687 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) 6688 { 6689 /* Generate Start */ 6690 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 6691 } 6692 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) 6693 { 6694 /* Generate ReStart */ 6695 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 6696 } 6697 else 6698 { 6699 /* Do nothing */ 6700 } 6701 6702 /* Wait until SB flag is set */ 6703 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 6704 { 6705 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 6706 { 6707 hi2c->ErrorCode = HAL_I2C_WRONG_START; 6708 } 6709 return HAL_TIMEOUT; 6710 } 6711 6712 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 6713 { 6714 /* Send slave address */ 6715 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 6716 } 6717 else 6718 { 6719 /* Send header of slave address */ 6720 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); 6721 6722 /* Wait until ADD10 flag is set */ 6723 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) 6724 { 6725 return HAL_ERROR; 6726 } 6727 6728 /* Send slave address */ 6729 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); 6730 } 6731 6732 /* Wait until ADDR flag is set */ 6733 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 6734 { 6735 return HAL_ERROR; 6736 } 6737 6738 return HAL_OK; 6739 } 6740 6741 /** 6742 * @brief Master sends target device address for read request. 6743 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6744 * the configuration information for I2C module 6745 * @param DevAddress Target device address: The device 7 bits address value 6746 * in datasheet must be shifted to the left before calling the interface 6747 * @param Timeout Timeout duration 6748 * @param Tickstart Tick start value 6749 * @retval HAL status 6750 */ 6751 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) 6752 { 6753 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 6754 uint32_t CurrentXferOptions = hi2c->XferOptions; 6755 6756 /* Enable Acknowledge */ 6757 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6758 6759 /* Generate Start condition if first transfer */ 6760 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) 6761 { 6762 /* Generate Start */ 6763 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 6764 } 6765 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) 6766 { 6767 /* Generate ReStart */ 6768 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 6769 } 6770 else 6771 { 6772 /* Do nothing */ 6773 } 6774 6775 /* Wait until SB flag is set */ 6776 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 6777 { 6778 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 6779 { 6780 hi2c->ErrorCode = HAL_I2C_WRONG_START; 6781 } 6782 return HAL_TIMEOUT; 6783 } 6784 6785 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 6786 { 6787 /* Send slave address */ 6788 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); 6789 } 6790 else 6791 { 6792 /* Send header of slave address */ 6793 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); 6794 6795 /* Wait until ADD10 flag is set */ 6796 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) 6797 { 6798 return HAL_ERROR; 6799 } 6800 6801 /* Send slave address */ 6802 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); 6803 6804 /* Wait until ADDR flag is set */ 6805 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 6806 { 6807 return HAL_ERROR; 6808 } 6809 6810 /* Clear ADDR flag */ 6811 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6812 6813 /* Generate Restart */ 6814 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 6815 6816 /* Wait until SB flag is set */ 6817 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 6818 { 6819 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 6820 { 6821 hi2c->ErrorCode = HAL_I2C_WRONG_START; 6822 } 6823 return HAL_TIMEOUT; 6824 } 6825 6826 /* Send header of slave address */ 6827 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); 6828 } 6829 6830 /* Wait until ADDR flag is set */ 6831 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 6832 { 6833 return HAL_ERROR; 6834 } 6835 6836 return HAL_OK; 6837 } 6838 6839 /** 6840 * @brief Master sends target device address followed by internal memory address for write request. 6841 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6842 * the configuration information for I2C module 6843 * @param DevAddress Target device address: The device 7 bits address value 6844 * in datasheet must be shifted to the left before calling the interface 6845 * @param MemAddress Internal memory address 6846 * @param MemAddSize Size of internal memory address 6847 * @param Timeout Timeout duration 6848 * @param Tickstart Tick start value 6849 * @retval HAL status 6850 */ 6851 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) 6852 { 6853 /* Generate Start */ 6854 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 6855 6856 /* Wait until SB flag is set */ 6857 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 6858 { 6859 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 6860 { 6861 hi2c->ErrorCode = HAL_I2C_WRONG_START; 6862 } 6863 return HAL_TIMEOUT; 6864 } 6865 6866 /* Send slave address */ 6867 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 6868 6869 /* Wait until ADDR flag is set */ 6870 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 6871 { 6872 return HAL_ERROR; 6873 } 6874 6875 /* Clear ADDR flag */ 6876 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6877 6878 /* Wait until TXE flag is set */ 6879 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 6880 { 6881 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 6882 { 6883 /* Generate Stop */ 6884 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 6885 } 6886 return HAL_ERROR; 6887 } 6888 6889 /* If Memory address size is 8Bit */ 6890 if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 6891 { 6892 /* Send Memory Address */ 6893 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); 6894 } 6895 /* If Memory address size is 16Bit */ 6896 else 6897 { 6898 /* Send MSB of Memory Address */ 6899 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); 6900 6901 /* Wait until TXE flag is set */ 6902 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 6903 { 6904 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 6905 { 6906 /* Generate Stop */ 6907 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 6908 } 6909 return HAL_ERROR; 6910 } 6911 6912 /* Send LSB of Memory Address */ 6913 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); 6914 } 6915 6916 return HAL_OK; 6917 } 6918 6919 /** 6920 * @brief Master sends target device address followed by internal memory address for read request. 6921 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 6922 * the configuration information for I2C module 6923 * @param DevAddress Target device address: The device 7 bits address value 6924 * in datasheet must be shifted to the left before calling the interface 6925 * @param MemAddress Internal memory address 6926 * @param MemAddSize Size of internal memory address 6927 * @param Timeout Timeout duration 6928 * @param Tickstart Tick start value 6929 * @retval HAL status 6930 */ 6931 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) 6932 { 6933 /* Enable Acknowledge */ 6934 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 6935 6936 /* Generate Start */ 6937 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 6938 6939 /* Wait until SB flag is set */ 6940 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 6941 { 6942 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 6943 { 6944 hi2c->ErrorCode = HAL_I2C_WRONG_START; 6945 } 6946 return HAL_TIMEOUT; 6947 } 6948 6949 /* Send slave address */ 6950 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 6951 6952 /* Wait until ADDR flag is set */ 6953 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 6954 { 6955 return HAL_ERROR; 6956 } 6957 6958 /* Clear ADDR flag */ 6959 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 6960 6961 /* Wait until TXE flag is set */ 6962 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 6963 { 6964 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 6965 { 6966 /* Generate Stop */ 6967 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 6968 } 6969 return HAL_ERROR; 6970 } 6971 6972 /* If Memory address size is 8Bit */ 6973 if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 6974 { 6975 /* Send Memory Address */ 6976 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); 6977 } 6978 /* If Memory address size is 16Bit */ 6979 else 6980 { 6981 /* Send MSB of Memory Address */ 6982 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); 6983 6984 /* Wait until TXE flag is set */ 6985 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 6986 { 6987 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 6988 { 6989 /* Generate Stop */ 6990 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 6991 } 6992 return HAL_ERROR; 6993 } 6994 6995 /* Send LSB of Memory Address */ 6996 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); 6997 } 6998 6999 /* Wait until TXE flag is set */ 7000 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 7001 { 7002 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 7003 { 7004 /* Generate Stop */ 7005 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 7006 } 7007 return HAL_ERROR; 7008 } 7009 7010 /* Generate Restart */ 7011 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 7012 7013 /* Wait until SB flag is set */ 7014 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 7015 { 7016 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 7017 { 7018 hi2c->ErrorCode = HAL_I2C_WRONG_START; 7019 } 7020 return HAL_TIMEOUT; 7021 } 7022 7023 /* Send slave address */ 7024 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); 7025 7026 /* Wait until ADDR flag is set */ 7027 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 7028 { 7029 return HAL_ERROR; 7030 } 7031 7032 return HAL_OK; 7033 } 7034 7035 /** 7036 * @brief DMA I2C process complete callback. 7037 * @param hdma DMA handle 7038 * @retval None 7039 */ 7040 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) 7041 { 7042 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ 7043 7044 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 7045 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 7046 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 7047 uint32_t CurrentXferOptions = hi2c->XferOptions; 7048 7049 /* Disable EVT and ERR interrupt */ 7050 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 7051 7052 /* Clear Complete callback */ 7053 if (hi2c->hdmatx != NULL) 7054 { 7055 hi2c->hdmatx->XferCpltCallback = NULL; 7056 } 7057 if (hi2c->hdmarx != NULL) 7058 { 7059 hi2c->hdmarx->XferCpltCallback = NULL; 7060 } 7061 7062 if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) 7063 { 7064 /* Disable DMA Request */ 7065 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 7066 7067 hi2c->XferCount = 0U; 7068 7069 if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) 7070 { 7071 /* Set state at HAL_I2C_STATE_LISTEN */ 7072 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 7073 hi2c->State = HAL_I2C_STATE_LISTEN; 7074 7075 /* Call the corresponding callback to inform upper layer of End of Transfer */ 7076 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 7077 hi2c->SlaveTxCpltCallback(hi2c); 7078 #else 7079 HAL_I2C_SlaveTxCpltCallback(hi2c); 7080 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 7081 } 7082 else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) 7083 { 7084 /* Set state at HAL_I2C_STATE_LISTEN */ 7085 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 7086 hi2c->State = HAL_I2C_STATE_LISTEN; 7087 7088 /* Call the corresponding callback to inform upper layer of End of Transfer */ 7089 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 7090 hi2c->SlaveRxCpltCallback(hi2c); 7091 #else 7092 HAL_I2C_SlaveRxCpltCallback(hi2c); 7093 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 7094 } 7095 else 7096 { 7097 /* Do nothing */ 7098 } 7099 7100 /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ 7101 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 7102 } 7103 /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ 7104 else if (hi2c->Mode != HAL_I2C_MODE_NONE) 7105 { 7106 if (hi2c->XferCount == (uint16_t)1) 7107 { 7108 /* Disable Acknowledge */ 7109 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 7110 } 7111 7112 /* Disable EVT and ERR interrupt */ 7113 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 7114 7115 /* Prepare next transfer or stop current transfer */ 7116 if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) 7117 { 7118 /* Generate Stop */ 7119 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 7120 } 7121 7122 /* Disable Last DMA */ 7123 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 7124 7125 /* Disable DMA Request */ 7126 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 7127 7128 hi2c->XferCount = 0U; 7129 7130 /* Check if Errors has been detected during transfer */ 7131 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 7132 { 7133 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 7134 hi2c->ErrorCallback(hi2c); 7135 #else 7136 HAL_I2C_ErrorCallback(hi2c); 7137 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 7138 } 7139 else 7140 { 7141 hi2c->State = HAL_I2C_STATE_READY; 7142 7143 if (hi2c->Mode == HAL_I2C_MODE_MEM) 7144 { 7145 hi2c->Mode = HAL_I2C_MODE_NONE; 7146 hi2c->PreviousState = I2C_STATE_NONE; 7147 7148 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 7149 hi2c->MemRxCpltCallback(hi2c); 7150 #else 7151 HAL_I2C_MemRxCpltCallback(hi2c); 7152 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 7153 } 7154 else 7155 { 7156 hi2c->Mode = HAL_I2C_MODE_NONE; 7157 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) 7158 { 7159 hi2c->PreviousState = I2C_STATE_NONE; 7160 } 7161 else 7162 { 7163 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 7164 } 7165 7166 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 7167 hi2c->MasterRxCpltCallback(hi2c); 7168 #else 7169 HAL_I2C_MasterRxCpltCallback(hi2c); 7170 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 7171 } 7172 } 7173 } 7174 else 7175 { 7176 /* Do nothing */ 7177 } 7178 } 7179 7180 /** 7181 * @brief DMA I2C communication error callback. 7182 * @param hdma DMA handle 7183 * @retval None 7184 */ 7185 static void I2C_DMAError(DMA_HandleTypeDef *hdma) 7186 { 7187 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ 7188 7189 /* Clear Complete callback */ 7190 if (hi2c->hdmatx != NULL) 7191 { 7192 hi2c->hdmatx->XferCpltCallback = NULL; 7193 } 7194 if (hi2c->hdmarx != NULL) 7195 { 7196 hi2c->hdmarx->XferCpltCallback = NULL; 7197 } 7198 7199 /* Disable Acknowledge */ 7200 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 7201 7202 hi2c->XferCount = 0U; 7203 hi2c->State = HAL_I2C_STATE_READY; 7204 hi2c->Mode = HAL_I2C_MODE_NONE; 7205 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 7206 7207 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 7208 hi2c->ErrorCallback(hi2c); 7209 #else 7210 HAL_I2C_ErrorCallback(hi2c); 7211 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 7212 } 7213 7214 /** 7215 * @brief DMA I2C communication abort callback 7216 * (To be called at end of DMA Abort procedure). 7217 * @param hdma DMA handle. 7218 * @retval None 7219 */ 7220 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) 7221 { 7222 __IO uint32_t count = 0U; 7223 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ 7224 7225 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 7226 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 7227 7228 /* During abort treatment, check that there is no pending STOP request */ 7229 /* Wait until STOP flag is reset */ 7230 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 7231 do 7232 { 7233 if (count == 0U) 7234 { 7235 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 7236 break; 7237 } 7238 count--; 7239 } 7240 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); 7241 7242 /* Clear Complete callback */ 7243 if (hi2c->hdmatx != NULL) 7244 { 7245 hi2c->hdmatx->XferCpltCallback = NULL; 7246 } 7247 if (hi2c->hdmarx != NULL) 7248 { 7249 hi2c->hdmarx->XferCpltCallback = NULL; 7250 } 7251 7252 /* Disable Acknowledge */ 7253 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 7254 7255 hi2c->XferCount = 0U; 7256 7257 /* Reset XferAbortCallback */ 7258 if (hi2c->hdmatx != NULL) 7259 { 7260 hi2c->hdmatx->XferAbortCallback = NULL; 7261 } 7262 if (hi2c->hdmarx != NULL) 7263 { 7264 hi2c->hdmarx->XferAbortCallback = NULL; 7265 } 7266 7267 /* Disable I2C peripheral to prevent dummy data in buffer */ 7268 __HAL_I2C_DISABLE(hi2c); 7269 7270 /* Check if come from abort from user */ 7271 if (hi2c->State == HAL_I2C_STATE_ABORT) 7272 { 7273 hi2c->State = HAL_I2C_STATE_READY; 7274 hi2c->Mode = HAL_I2C_MODE_NONE; 7275 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 7276 7277 /* Call the corresponding callback to inform upper layer of End of Transfer */ 7278 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 7279 hi2c->AbortCpltCallback(hi2c); 7280 #else 7281 HAL_I2C_AbortCpltCallback(hi2c); 7282 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 7283 } 7284 else 7285 { 7286 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 7287 { 7288 /* Renable I2C peripheral */ 7289 __HAL_I2C_ENABLE(hi2c); 7290 7291 /* Enable Acknowledge */ 7292 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 7293 7294 /* keep HAL_I2C_STATE_LISTEN */ 7295 hi2c->PreviousState = I2C_STATE_NONE; 7296 hi2c->State = HAL_I2C_STATE_LISTEN; 7297 } 7298 else 7299 { 7300 hi2c->State = HAL_I2C_STATE_READY; 7301 hi2c->Mode = HAL_I2C_MODE_NONE; 7302 } 7303 7304 /* Call the corresponding callback to inform upper layer of End of Transfer */ 7305 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 7306 hi2c->ErrorCallback(hi2c); 7307 #else 7308 HAL_I2C_ErrorCallback(hi2c); 7309 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 7310 } 7311 } 7312 7313 /** 7314 * @brief This function handles I2C Communication Timeout. 7315 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 7316 * the configuration information for I2C module 7317 * @param Flag specifies the I2C flag to check. 7318 * @param Status The new Flag status (SET or RESET). 7319 * @param Timeout Timeout duration 7320 * @param Tickstart Tick start value 7321 * @retval HAL status 7322 */ 7323 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) 7324 { 7325 /* Wait until flag is set */ 7326 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 7327 { 7328 /* Check for the Timeout */ 7329 if (Timeout != HAL_MAX_DELAY) 7330 { 7331 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 7332 { 7333 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) 7334 { 7335 hi2c->PreviousState = I2C_STATE_NONE; 7336 hi2c->State = HAL_I2C_STATE_READY; 7337 hi2c->Mode = HAL_I2C_MODE_NONE; 7338 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 7339 7340 /* Process Unlocked */ 7341 __HAL_UNLOCK(hi2c); 7342 7343 return HAL_ERROR; 7344 } 7345 } 7346 } 7347 } 7348 return HAL_OK; 7349 } 7350 7351 /** 7352 * @brief This function handles I2C Communication Timeout for Master addressing phase. 7353 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 7354 * the configuration information for I2C module 7355 * @param Flag specifies the I2C flag to check. 7356 * @param Timeout Timeout duration 7357 * @param Tickstart Tick start value 7358 * @retval HAL status 7359 */ 7360 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) 7361 { 7362 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) 7363 { 7364 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 7365 { 7366 /* Generate Stop */ 7367 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 7368 7369 /* Clear AF Flag */ 7370 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 7371 7372 hi2c->PreviousState = I2C_STATE_NONE; 7373 hi2c->State = HAL_I2C_STATE_READY; 7374 hi2c->Mode = HAL_I2C_MODE_NONE; 7375 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 7376 7377 /* Process Unlocked */ 7378 __HAL_UNLOCK(hi2c); 7379 7380 return HAL_ERROR; 7381 } 7382 7383 /* Check for the Timeout */ 7384 if (Timeout != HAL_MAX_DELAY) 7385 { 7386 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 7387 { 7388 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)) 7389 { 7390 hi2c->PreviousState = I2C_STATE_NONE; 7391 hi2c->State = HAL_I2C_STATE_READY; 7392 hi2c->Mode = HAL_I2C_MODE_NONE; 7393 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 7394 7395 /* Process Unlocked */ 7396 __HAL_UNLOCK(hi2c); 7397 7398 return HAL_ERROR; 7399 } 7400 } 7401 } 7402 } 7403 return HAL_OK; 7404 } 7405 7406 /** 7407 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. 7408 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 7409 * the configuration information for the specified I2C. 7410 * @param Timeout Timeout duration 7411 * @param Tickstart Tick start value 7412 * @retval HAL status 7413 */ 7414 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) 7415 { 7416 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 7417 { 7418 /* Check if a NACK is detected */ 7419 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) 7420 { 7421 return HAL_ERROR; 7422 } 7423 7424 /* Check for the Timeout */ 7425 if (Timeout != HAL_MAX_DELAY) 7426 { 7427 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 7428 { 7429 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)) 7430 { 7431 hi2c->PreviousState = I2C_STATE_NONE; 7432 hi2c->State = HAL_I2C_STATE_READY; 7433 hi2c->Mode = HAL_I2C_MODE_NONE; 7434 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 7435 7436 /* Process Unlocked */ 7437 __HAL_UNLOCK(hi2c); 7438 7439 return HAL_ERROR; 7440 } 7441 } 7442 } 7443 } 7444 return HAL_OK; 7445 } 7446 7447 /** 7448 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. 7449 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 7450 * the configuration information for the specified I2C. 7451 * @param Timeout Timeout duration 7452 * @param Tickstart Tick start value 7453 * @retval HAL status 7454 */ 7455 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) 7456 { 7457 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) 7458 { 7459 /* Check if a NACK is detected */ 7460 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) 7461 { 7462 return HAL_ERROR; 7463 } 7464 7465 /* Check for the Timeout */ 7466 if (Timeout != HAL_MAX_DELAY) 7467 { 7468 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 7469 { 7470 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) 7471 { 7472 hi2c->PreviousState = I2C_STATE_NONE; 7473 hi2c->State = HAL_I2C_STATE_READY; 7474 hi2c->Mode = HAL_I2C_MODE_NONE; 7475 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 7476 7477 /* Process Unlocked */ 7478 __HAL_UNLOCK(hi2c); 7479 7480 return HAL_ERROR; 7481 } 7482 } 7483 } 7484 } 7485 return HAL_OK; 7486 } 7487 7488 /** 7489 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. 7490 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 7491 * the configuration information for the specified I2C. 7492 * @param Timeout Timeout duration 7493 * @param Tickstart Tick start value 7494 * @retval HAL status 7495 */ 7496 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) 7497 { 7498 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 7499 { 7500 /* Check if a NACK is detected */ 7501 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) 7502 { 7503 return HAL_ERROR; 7504 } 7505 7506 /* Check for the Timeout */ 7507 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 7508 { 7509 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) 7510 { 7511 hi2c->PreviousState = I2C_STATE_NONE; 7512 hi2c->State = HAL_I2C_STATE_READY; 7513 hi2c->Mode = HAL_I2C_MODE_NONE; 7514 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 7515 7516 /* Process Unlocked */ 7517 __HAL_UNLOCK(hi2c); 7518 7519 return HAL_ERROR; 7520 } 7521 } 7522 } 7523 return HAL_OK; 7524 } 7525 7526 /** 7527 * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. 7528 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 7529 * the configuration information for the specified I2C. 7530 * @retval HAL status 7531 */ 7532 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) 7533 { 7534 __IO uint32_t count = 0U; 7535 7536 /* Wait until STOP flag is reset */ 7537 count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); 7538 do 7539 { 7540 count--; 7541 if (count == 0U) 7542 { 7543 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 7544 7545 return HAL_ERROR; 7546 } 7547 } 7548 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); 7549 7550 return HAL_OK; 7551 } 7552 7553 /** 7554 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. 7555 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 7556 * the configuration information for the specified I2C. 7557 * @param Timeout Timeout duration 7558 * @param Tickstart Tick start value 7559 * @retval HAL status 7560 */ 7561 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) 7562 { 7563 7564 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 7565 { 7566 /* Check if a STOPF is detected */ 7567 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 7568 { 7569 /* Clear STOP Flag */ 7570 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 7571 7572 hi2c->PreviousState = I2C_STATE_NONE; 7573 hi2c->State = HAL_I2C_STATE_READY; 7574 hi2c->Mode = HAL_I2C_MODE_NONE; 7575 hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; 7576 7577 /* Process Unlocked */ 7578 __HAL_UNLOCK(hi2c); 7579 7580 return HAL_ERROR; 7581 } 7582 7583 /* Check for the Timeout */ 7584 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 7585 { 7586 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) 7587 { 7588 hi2c->PreviousState = I2C_STATE_NONE; 7589 hi2c->State = HAL_I2C_STATE_READY; 7590 hi2c->Mode = HAL_I2C_MODE_NONE; 7591 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 7592 7593 /* Process Unlocked */ 7594 __HAL_UNLOCK(hi2c); 7595 7596 return HAL_ERROR; 7597 } 7598 } 7599 } 7600 return HAL_OK; 7601 } 7602 7603 /** 7604 * @brief This function handles Acknowledge failed detection during an I2C Communication. 7605 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 7606 * the configuration information for the specified I2C. 7607 * @retval HAL status 7608 */ 7609 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) 7610 { 7611 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 7612 { 7613 /* Clear NACKF Flag */ 7614 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 7615 7616 hi2c->PreviousState = I2C_STATE_NONE; 7617 hi2c->State = HAL_I2C_STATE_READY; 7618 hi2c->Mode = HAL_I2C_MODE_NONE; 7619 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 7620 7621 /* Process Unlocked */ 7622 __HAL_UNLOCK(hi2c); 7623 7624 return HAL_ERROR; 7625 } 7626 return HAL_OK; 7627 } 7628 7629 /** 7630 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. 7631 * @param hi2c I2C handle. 7632 * @retval None 7633 */ 7634 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) 7635 { 7636 /* if user set XferOptions to I2C_OTHER_FRAME */ 7637 /* it request implicitly to generate a restart condition */ 7638 /* set XferOptions to I2C_FIRST_FRAME */ 7639 if (hi2c->XferOptions == I2C_OTHER_FRAME) 7640 { 7641 hi2c->XferOptions = I2C_FIRST_FRAME; 7642 } 7643 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ 7644 /* it request implicitly to generate a restart condition */ 7645 /* then generate a stop condition at the end of transfer */ 7646 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ 7647 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) 7648 { 7649 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; 7650 } 7651 else 7652 { 7653 /* Nothing to do */ 7654 } 7655 } 7656 7657 /** 7658 * @} 7659 */ 7660 7661 #endif /* HAL_I2C_MODULE_ENABLED */ 7662 /** 7663 * @} 7664 */ 7665 7666 /** 7667 * @} 7668 */ 7669